)]}'
{
  "commit": "516031078c9bc188111a27fc3faf43e13827a9e4",
  "tree": "c626055f1cafc86b7fc693189d76d0813a8bc3d5",
  "parents": [
    "d3440737cc56a4d1b20c72181d9a37f194bd3ce5"
  ],
  "author": {
    "name": "Zhuoran Yin",
    "email": "zhuoryin@amd.com",
    "time": "Tue Dec 02 11:41:57 2025 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Dec 02 11:41:57 2025 -0500"
  },
  "message": "[Codegen][GPU] Enable 3-stage pipelining with hipblaslt compute-\u003ewrite-\u003eread ordering (#22788)\n\n3-stage uses different cluster ordering to maximize distance between\nread and use. Stage definitions remain the same. The changes are mostly\ntrivial and the new pipelined code work out of box.\n\nOn MI300, the tracked gemm configs improve performance by 4.5% on\naverage for NN and NT layouts.\n\nRight now there\u0027s no easy way to experiment this through a compiler\nflag, and the only way to experiment this is to change the tablegen\ndefault number of stage to 3. I plan to expose it properly in the next\nPR.\n\n---------\n\nSigned-off-by: jerryyin \u003czhuoryin@amd.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d5cf5c51a6459d2f73f2089a658041218ee3b97f",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Utils/ROCDLPrefetchSharedMemoryCopy.cpp",
      "new_id": "863ab7a3e351b21395986d76cb5d1248b1a1ee4e",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/Utils/ROCDLPrefetchSharedMemoryCopy.cpp"
    },
    {
      "type": "modify",
      "old_id": "4f7fdc9c0625943a40ffaefa3398f17014406a80",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/prefetch_shared_memory.mlir",
      "new_id": "3f5aff20b2124e0b3efb9179d8cc383c545672ad",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/prefetch_shared_memory.mlir"
    }
  ]
}