)]}'
{
  "commit": "4f990431a73902c02288fd5892ddf4540b72998b",
  "tree": "d5873749815a8d57c29a3cfc4839f03396a5269c",
  "parents": [
    "5fbfe29bc4ca9e3e0c93931fbe394ac21537a72f"
  ],
  "author": {
    "name": "Zhewen Yu",
    "email": "zhewenyu@amd.com",
    "time": "Wed May 06 22:08:25 2026 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed May 06 22:08:25 2026 +0100"
  },
  "message": "Reapply \"[Codegen] Enable DMA by default for F16/BF16 Gemm on gfx950 (#24117)\" (#24235) (#24373)\n\nThis reverts commit 75ffbc37144de79cc9428f97827251b2242b230f.\n\nThe previously reported numerical issues have now been resolved through\nthe following changes:\n- https://github.com/iree-org/iree/pull/24241\n- https://github.com/iree-org/iree/pull/24242\n- https://github.com/iree-org/iree/pull/24254\n\n---------\n\nSigned-off-by: Yu-Zhewen \u003czhewenyu@amd.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "888f2950483c7f7ec90e371f0c3aacb5dc91a9f0",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp",
      "new_id": "08c4d773302cf4b04faea0ffaaf959deafc60dde",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Common/GPU/GPUConvertToCoalescedDMA.cpp"
    },
    {
      "type": "modify",
      "old_id": "9ab5d4ea8ce2e0f7c9872e322ccfec0d997ae875",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp",
      "new_id": "626c21055d238c9adfe8efd41f9d896f07e7fa6a",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TargetUtils/ConfigUtils.cpp"
    },
    {
      "type": "modify",
      "old_id": "8a5f83d9f82e5b8db492db488d59a35c277f192b",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp",
      "new_id": "1f28efff59e33b451f847f05753d218711fdf556",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp"
    },
    {
      "type": "modify",
      "old_id": "dc91220f3bbbbb9b9d23a5ce9a3626601f300d86",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_tile_and_fuse_gfx950.mlir",
      "new_id": "2673f4c05732d85cfbb328cfd373cead1cb2abe7",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/config_tile_and_fuse_gfx950.mlir"
    },
    {
      "type": "modify",
      "old_id": "e1adfa543badb4e8ed31f6cbedf76c3892191c7d",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Utils/GPUUtils.cpp",
      "new_id": "dc5e343d345f66e31657a51de31ca431cfb6c72e",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Utils/GPUUtils.cpp"
    },
    {
      "type": "modify",
      "old_id": "631e0207670d1cdfa9371c4deccbcfa42f544431",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Utils/GPUUtils.h",
      "new_id": "8037d8e785c351b6ec2d90e32baf6bfd14c9ae02",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Utils/GPUUtils.h"
    }
  ]
}