tree c9a14d595a0898f8374cc06ceca06e40df7e8086
parent 656c80a5dc55b3c80b062d8ad3dafe112229decf
author Lei Zhang <antiagainst@google.com> 1628792839 -0400
committer MaheshRavishankar <ravishankarm@google.com> 1629150849 -0700

[spirv] Fix convolution tiling and vectorization (#6739)

* [spirv] Fix convolution tiling and vectorization

Convolution vectorization requires static shape. The difficulty
here is the indexing map for the input operand, which is

```
n, oh * strides[0] + kh * dilations[0], ow * strides[1] + kw * dilations[1], ic
```

This creates `affine.min` ops used in memref subview sizes. Those
`affine.min` ops involve processor IDs; in order to fold them
away, we need to get the range of processor IDs. This is done
by the pass `SPIRVFoldGPUProcessorIDUses`. We need to query such
information from the entry point workgroup count region, which should
return constant values. This commit fixes it for that.

Along the way, the functionality of `materializeStaticLaunchInformation`
is merged into `SetNumWorkgroupsPass` as that's the only user
of the utility now.