)]}'
{
  "commit": "4cf1a7cd7e5a15140c1e7679d784dd75923a2bc9",
  "tree": "758fe6ecbd640f90e42d7567bef5ec687619aef9",
  "parents": [
    "a869dc3c51071fe9942c59706ec193ca88395dc6"
  ],
  "author": {
    "name": "pstarkcdpr",
    "email": "paul.stark@cdprojektred.com",
    "time": "Mon Jul 20 04:59:29 2026 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jul 20 13:59:29 2026 +0200"
  },
  "message": "[CPU] Vectorize parallel dims for non-AVX512 x86 matmul defaults (#24701)\n\nSee GitHub issue: https://github.com/iree-org/iree/issues/24700\n\n`getDefaultMatmulVectorSizes` used `{1, 1, vectorSize}` for non-AVX512\nx86, which vectorizes only the reduction (`K`) dim and leaves the\nparallel/output dims scalar. This forces a horizontal reduction per\noutput element and is dramatically slower for f32 matmul_like /\nbatch_matmul kernels compared to v3.5 (~2.4x end-to-end regression on an\naffected model; ~92x on an isolated `512x512x512` matmul at `x86-64-v3`,\n`-O1`). Mirror the AArch64/RISC-V defaults by register-blocking the\nmatmul with `{8, vectorSize, vectorSize}`, vectorizing both parallel\ndims (`M` unroll, `N` vector) in addition to `K`.\n\nNumerics are unchanged. As a side effect, dynamic-shape accumulating\nGEMMs may now hoist a couple of tiny fixed-size remainder scratch\nbuffers (`memref.alloca`) from register-blocked peeling; the accumulator\nstays in registers and is written directly to the destination (no heap\nalloc, no `linalg.generic` copy). The `pipeline_tests.mlir`\naccumulating-GEMM guard is relaxed to forbid only heap allocation, and\nthe `select_x86_64` expected configs are updated `([1, 1, 0] -\u003e [8, 4,\n0])`.\n\n---------\n\nSigned-off-by: Paul Stark \u003cpaul.stark@cdprojektred.com\u003e\nCo-authored-by: Claude Opus 4.8 \u003cnoreply@anthropic.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c075923be8085dbfb9aa4fd01fe48ab693552997",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "600ade9e31e792963d34b80b950cf4e32ef2d8a9",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "edf62600b330f3a00121027b58bbd7d0916c626e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_tests.mlir",
      "new_id": "d0acc85df5679f131ed2f3b4ae67609a7d5ebd76",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/pipeline_tests.mlir"
    },
    {
      "type": "modify",
      "old_id": "d73394e519836407bbc78da09ac368ee63bcae5c",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir",
      "new_id": "a551c3c5f209af07dbf3800ca33564559558bce3",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir"
    }
  ]
}