)]}'
{
  "commit": "4cc6671320e881d4b3f112417fcd253ad6b031ce",
  "tree": "acf5811a96818b00d2d2db9224a09aacd0208b8c",
  "parents": [
    "d0269f3830a88a89f1faadd1e15019be8e911d40"
  ],
  "author": {
    "name": "Cullen Rhodes",
    "email": "cullen.rhodes@arm.com",
    "time": "Tue Oct 22 08:18:56 2024 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Oct 22 08:18:56 2024 +0100"
  },
  "message": "[CPU] Limit vectorization tile sizes for SVE (#18846)\n\nThis prevents large vector sizes. A regression test is included with a\r\nlinalg.pooling_nchw_max operation that currently fails to compile with\r\n\r\nerror: One or more operations with large vector sizes (8192 bytes) were\r\nfound:\r\n\r\nwhen SVE is enabled, even though SVE isn\u0027t used.\r\n\r\n---------\r\n\r\nSigned-off-by: Cullen Rhodes \u003ccullen.rhodes@arm.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "6f9983454af57103f87799666a76e8f5cd7eb537",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "5111b7668958c24577d8d0ed4317e65334022a67",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "757a039ed119783d129928c3f425cbb82d6bc10e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "1308442f23bf2042c8ce51bdbeaa9453e8fd0486",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    }
  ]
}