)]}'
{
  "commit": "4b11e1da59b1303d497ebf2f0c49c4d4bb422188",
  "tree": "6e8b6af4e054fddd0877b0b50591696a1e69272a",
  "parents": [
    "dd3505291ac1dfa2c6d05f67cc5d72ae763a263a"
  ],
  "author": {
    "name": "Federico Bruzzone",
    "email": "federico.bruzzone.i@gmail.com",
    "time": "Thu Jul 16 18:02:54 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jul 16 16:02:54 2026 +0000"
  },
  "message": "[LLVMCPU] Add SME lowering-strategy tests for f64 and unsupported i8 matmuls (#24656)\n\n`getMatmulAArch64SMEVectorSizes` (within `KernelDispatch.cpp`) only had\ntest coverage for the f32 matmul case.\n\nThis PR add two tests:\n- `f64` which uses `[4]x[8]` SME tiles instead of the `[8]x[8]` used for\nf32.\n\nhttps://github.com/iree-org/iree/blob/50d0addfb49254e0b7b746959b360c79437281cc/compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp#L1465-L1471\n- `i8` which SME does not support\n\nhttps://github.com/iree-org/iree/blob/50d0addfb49254e0b7b746959b360c79437281cc/compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp#L1488-L1502\n\n_AI disclaimer_: I used `Claude:Sonnet5` to write the checks.\n\n---------\n\nSigned-off-by: Federico Bruzzone \u003cfederico.bruzzone.i@gmail.com\u003e\nCo-authored-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "12f828533081fd41ad523cb9506280f987d07ddc",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/BUILD.bazel",
      "new_id": "d39c820a43cf1b0b7ed92bb76ffba49e4eec1158",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/BUILD.bazel"
    },
    {
      "type": "modify",
      "old_id": "e8d26a095c0369029834f0e51cf69f68fb11ab12",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/CMakeLists.txt",
      "new_id": "abc526f2d48a0be8ad82ca0bb8e622d84ff28d09",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/CMakeLists.txt"
    },
    {
      "type": "modify",
      "old_id": "9b20c0ec5530866ba26eefe6a048e57b41340bf9",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sme_lowering_strategy.mlir",
      "new_id": "2d053655787555ab8d2150b69de94e574cbe78c7",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sme_lowering_strategy.mlir"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "840d702471cdc6c5d41c243fe3f5a814cd33a703",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_ssve_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "b5d9cf8328bee4356b884358a9e68b770ce51fc3",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "7f79c40e775e0ac7dd02971b2e96cd87d3c55b7c",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    }
  ]
}