| commit | 4983668103817e5f6c58b410e6ebd6c49aa03b2b | [log] [tgz] |
|---|---|---|
| author | bjacob <benoitjacob@google.com> | Wed Oct 11 16:21:21 2023 -0400 |
| committer | GitHub <noreply@github.com> | Wed Oct 11 16:21:21 2023 -0400 |
| tree | 90c7b0f4d121ae7a3e8a4670d5471bda7f9733cf | |
| parent | a7a784e1f3f2df1080525c41f19a942771694480 [diff] |
`mmt4d` ukernel for the `bf16*bf16->f32` case using AVX-512-BF16 (#15089) `bf16*bf16->f32` is the one floating-point element type that can perform faster than regular `f32` on widely-available x86 CPUs, as AVX-512-BF16 is available on Intel Cooper Lake and AMD Zen4 microarchitectures. By contrast, AVX-512-FP16 is only available on Intel Sapphire Rapids. The below benchmark results show this being a 2x speedup over `f32` and matching current `i8*i8->i32` performance with VNNI, which could make it quite useful as rounding f32 to the nearest bf16 is easier and less accuracy-compromising than i8-quantizing. The accumulator is still f32 so there's no change there. ### Crazy idea Rewriting `f32` matmuls into rounding LHS/RHS to `bf16` then doing a `bf16*bf16->f32` matmul is something that we could do as an (opt-in) automatic rewrite for people who have a `f32` workload on their hands and who would like a quick flag to try to get a cheap speedup. Accuracy is likely to be good enough for a majority of workloads, unlike much harder `i8` quantization. Try this flag, get 2x speedup on f32 workloads on recent x86 CPU, and a 4x speedup on recent ARM. By contrast, an equivalent flag for fp16 would be a 2x slowdown on x86 (except Sapphire Rapids) and a 2x speedup on recent ARM. ### Benchmark on AMD Zen4 (Ryzen 9 7940HS), `mmt4d_benchmark` (single-thread microbenchmark): |Benchmark |Gop/s| |-------------------------------------------------------|-----| |BM_mmt4d_f32f32f32_tile_1x8x1_avx2_fma |25.5 | |BM_mmt4d_f32f32f32_tile_2x8x1_avx2_fma |43.3 | |BM_mmt4d_f32f32f32_tile_4x8x1_avx2_fma |82.3 | |BM_mmt4d_f32f32f32_tile_8x8x1_avx2_fma |132.9| |BM_mmt4d_f32f32f32_tile_1x16x1_avx512_base |44.1 | |BM_mmt4d_f32f32f32_tile_2x16x1_avx512_base |87.8 | |BM_mmt4d_f32f32f32_tile_4x16x1_avx512_base |167.1| |BM_mmt4d_f32f32f32_tile_8x16x1_avx512_base |166.7| |BM_mmt4d_f32f32f32_tile_16x16x1_avx512_base |166.3| |BM_mmt4d_f16f16f32_tile_1x8x1_avx2_fma |21.6 | |BM_mmt4d_f16f16f32_tile_2x8x1_avx2_fma |41.0 | |BM_mmt4d_f16f16f32_tile_4x8x1_avx2_fma |74.1 | |BM_mmt4d_f16f16f32_tile_8x8x1_avx2_fma |81.0 | |BM_mmt4d_f16f16f32_tile_1x16x1_avx512_base |38.6 | |BM_mmt4d_f16f16f32_tile_2x16x1_avx512_base |64.5 | |BM_mmt4d_f16f16f32_tile_4x16x1_avx512_base |73.5 | |BM_mmt4d_f16f16f32_tile_8x16x1_avx512_base |79.4 | |BM_mmt4d_f16f16f32_tile_16x16x1_avx512_base |82.6 | |BM_mmt4d_f16f16f16_tile_1x8x1_avx2_fma |21.6 | |BM_mmt4d_f16f16f16_tile_2x8x1_avx2_fma |40.9 | |BM_mmt4d_f16f16f16_tile_4x8x1_avx2_fma |73.8 | |BM_mmt4d_f16f16f16_tile_8x8x1_avx2_fma |80.1 | |BM_mmt4d_f16f16f16_tile_1x16x1_avx512_base |39.1 | |BM_mmt4d_f16f16f16_tile_2x16x1_avx512_base |66.5 | |BM_mmt4d_f16f16f16_tile_4x16x1_avx512_base |73.7 | |BM_mmt4d_f16f16f16_tile_8x16x1_avx512_base |79.3 | |BM_mmt4d_f16f16f16_tile_16x16x1_avx512_base |82.3 | |BM_mmt4d_bf16bf16f32_tile_1x16x2_avx512_bf16 |68.0 | |BM_mmt4d_bf16bf16f32_tile_2x16x2_avx512_bf16 |123.2| |BM_mmt4d_bf16bf16f32_tile_4x16x2_avx512_bf16 |228.9| |BM_mmt4d_bf16bf16f32_tile_8x16x2_avx512_bf16 |333.6| |BM_mmt4d_bf16bf16f32_tile_16x16x2_avx512_bf16 |332.2| |BM_mmt4d_i8i8i32_tile_1x8x2_avx2_fma |57.6 | |BM_mmt4d_i8i8i32_tile_2x8x2_avx2_fma |78.3 | |BM_mmt4d_i8i8i32_tile_4x8x2_avx2_fma |92.9 | |BM_mmt4d_i8i8i32_tile_8x8x2_avx2_fma |186.0| |BM_mmt4d_i8i8i32_tile_1x16x2_avx512_base |37.8 | |BM_mmt4d_i8i8i32_tile_2x16x2_avx512_base |49.0 | |BM_mmt4d_i8i8i32_tile_4x16x2_avx512_base |59.2 | |BM_mmt4d_i8i8i32_tile_8x16x2_avx512_base |118.4| |BM_mmt4d_i8i8i32_tile_16x16x2_avx512_base |231.8| |BM_mmt4d_i8i8i32_tile_1x16x2_avx512_vnni |50.8 | |BM_mmt4d_i8i8i32_tile_2x16x2_avx512_vnni |70.0 | |BM_mmt4d_i8i8i32_tile_4x16x2_avx512_vnni |83.3 | |BM_mmt4d_i8i8i32_tile_8x16x2_avx512_vnni |165.5| |BM_mmt4d_i8i8i32_tile_16x16x2_avx512_vnni |328.1|
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
IREE is still in its early phase. We have settled down on the overarching infrastructure and are actively improving various software components as well as project logistics. It is still quite far from ready for everyday use and is made available without any support at the moment. With that said, we welcome any kind of feedback on any communication channels!
See our website for more information.
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.