[LLVMCPU] Fix ArmSME requiring classic SVE, breaking SME-only targets (e.g., Apple Silicon) (#24661)

`enableAArch64SME` required `hasAnySVEFeature` in addition to
`hasSMEFeature`, even though SME runs in Streaming SVE mode and does not
architecturally need classic (non-streaming) SVE. On SME-only targets
(e.g. Apple Silicon, which implements `FEAT_SME`/`FEAT_SME2` but not
`FEAT_SVE`), this meant:

- **`+sme` alone**: `enableAArch64SME` was `false`, so the ArmSME
lowering pipeline never ran. Vectorization silently fell back to scalar
code, but a leftover `vscale` was never inside a function marked
"streaming", so it had no legal instruction-selection pattern:
`iree-compile` crashed with `LLVM ERROR: Cannot select: vscale`.
- **`+sve,+sme` together** (the only combination the existing SME e2e
tests use): compiles fine, but a separate, Darwin-specific mechanism in
`AArch64FrameLowering`/`AArch64PrologueEpilogue` is gated on `hasSVE()`.
With `+sve` set, LLVM emits `cntd` directly in the function prologue
*before* `smstart`, which is illegal on hardware without non-streaming
SVE and crashes at runtime with `SIGILL`.

Neither combination worked; does that mean that, prior to this PR, it
wasn't possible to use IREE's SME support on this class of hardware? If
so, it implies that, until now, IREE couldn't leverage SME on Apple M4
Pro processors.
But I feel like I might be missing something...

Fixes #24660.

See: https://github.com/llvm/llvm-project/issues/204853


@banach-space @egebeysel @AGindinson @maxbartel

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Signed-off-by: Federico Bruzzone <federico.bruzzone.i@gmail.com>
Co-authored-by: Ege Beysel <beyselege@gmail.com>