[ARM64] Add base bf16 mmt4d tiles for cores without the BF16 extension (#24900) On Arm64 cores without the Armv8.6 BF16 extension, bf16 `mmt4d` currently falls back to the scalar generic kernel. All existing Arm64 bf16 tiles require the `_bf16` feature: ```text IREE_UK_MMT4D_TILE(arm_64, bf16, bf16, f32, 1..8, 8, 4, _bf16) IREE_UK_MMT4D_TILE(arm_64, bf16, bf16, bf16, 1..8, 8, 4, _bf16) ``` This PR adds base Arm64 bf16 tiles for cores without that extension. The new tiles widen bf16 operands to f32 using NEON, accumulate with FMLA, and narrow back to bf16 on store when required. The same implementation serves both bf16 and f32 accumulator/output variants. No compiler changes are required: `enumerateMatmulTileArm64` already selects `8x8x1` tiles for bf16 when the BF16 extension is unavailable. ## Performance i.MX95 (Cortex-A55, six cores), 512x512x512, median of three runs: | case | before | after | speedup | |---|---:|---:|---:| | bf16 -> bf16 | 216 ms | 7.64 ms | 28x | | bf16 -> f32 | 216 ms | 7.53 ms | 29x | | f32 -> f32 | — | 8.22 ms | — | For narrow M, using Mx512 by 512x512: | M | before | after | speedup | |---|---:|---:|---:| | 1 | 1.52 ms | 0.879 ms | 1.7x | | 2 | 2.31 ms | 0.874 ms | 2.6x | | 4 | 3.37 ms | 0.887 ms | 3.8x | ## Correctness Tested on device with `iree-run-module` for M=1,2,4,8 for bf16 -> bf16 and M=8 for bf16 -> f32. The registered tiles match the generic implementation for normal inputs. The widening behavior for bf16 subnormals and NaN payloads follows the native NEON conversion behavior and can differ from the scalar helper, similarly to the existing Arm64 f16 tiles. The bf16 -> bf16 path accumulates in f32 and rounds once when storing, matching the behavior of the existing Arm64 f16 tile. Assisted by: Claude --------- Signed-off-by: Thomas Ziereis <ziereis@roofline.ai> Co-authored-by: Claude Opus 5 (1M context) <noreply@anthropic.com>
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
Releases notes are published on GitHub releases.
| Package | Release status |
|---|---|
| GitHub release (stable) | |
| GitHub release (nightly) | |
iree-base-compiler | |
iree-base-runtime |
For more details on the release process, see https://iree.dev/developers/general/release-management/.
| Operating system | Build status |
|---|---|
| Linux | |
| macOS |
For the full list of workflows see https://iree.dev/developers/general/github-actions/.
See our website for more information.
Community meeting recordings: IREE YouTube channel
| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.