[ROCM] Name gfx1250 CDNA5 and add MI455X target details (#24923) AMD published the CDNA5 architecture and MI455X specifications a few weeks ago: https://www.amd.com/content/dam/amd/en/documents/products/technologies/cdna/amd-cdna5-whitepaper.pdf Move the existing gfx1250 WGP definition alongside the other CDNA families and add cdna5 and mi455x target aliases. Populate the MI455X chip definition with the published WGP count, memory bandwidth, and peak compute rates. Document the confirmed WGP limits and update the architecture naming in compiler and runtime documentation. Normalize SKU and architecture aliases before forming executable target IDs for the amdgpu device. Without this, mi455x and cdna5 are emitted as executable formats that the runtime cannot match, even though the embedded target_info already names gfx1250. Add coverage for target metadata, Wave32 serialization, and canonical AMDGPU executable formats with feature suffixes. Assisted-by: codex (gpt-6-astra)
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
Releases notes are published on GitHub releases.
| Package | Release status |
|---|---|
| GitHub release (stable) |  |
| GitHub release (nightly) |  |
iree-base-compiler |  |
iree-base-runtime |  |
For more details on the release process, see https://iree.dev/developers/general/release-management/.
| Operating system | Build status |
|---|---|
| Linux |  |
| macOS |  |
For the full list of workflows see https://iree.dev/developers/general/github-actions/.
See our website for more information.
Community meeting recordings: IREE YouTube channel
| Date | Title | Recording | Slides |
|---|---|---|---|
| 2025-06-10 | Data-Tiling in IREE: Achieving High Performance Through Compiler Design (AsiaLLVM) | recording | slides |
| 2025-05-17 | Introduction to GPU architecture and IREE's GPU CodeGen Pipeline | recording | slides |
| 2025-02-12 | The Long Tail of AI: SPIR-V in IREE and MLIR (Vulkanised) | recording | slides |
| 2024-10-01 | Unveiling the Inner Workings of IREE: An MLIR-Based Compiler for Diverse Hardware | recording | |
| 2021-06-09 | IREE Runtime Design Tech Talk | recording | slides |
| 2020-08-20 | IREE CodeGen (MLIR Open Design Meeting) | recording | slides |
| 2020-03-18 | Interactive HAL IR Walkthrough | recording | |
| 2020-01-31 | End-to-end MLIR Workflow in IREE (MLIR Open Design Meeting) | recording | slides |
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.