)]}'
{
  "commit": "45ca23e0cf3387ff834105ed6481e8dfbf282cfc",
  "tree": "950a70c6df38d7f03eece05bf339007a810eda9b",
  "parents": [
    "a8930d7c056021e3507e4ddf7c3dfb20d79f1881"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanhan0912@gmail.com",
    "time": "Mon May 13 09:03:36 2024 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon May 13 09:03:36 2024 -0700"
  },
  "message": "[CPU] Take native_vector_size into accounts for attention op tiling. (#17349)\n\nThe second tile size maps the matmul M/N dimensions after decomposition.\r\nThe revision makes it have more reasonable tile sizes for the matmuls.\r\nWe are not able to force the size to native_vector_size because of the\r\nbufferization issue, see https://github.com/iree-org/iree/issues/16956",
  "tree_diff": [
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      "type": "modify",
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "8802ec6488b2ca6d31258f666359f1c37fc204be",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "96a4a010427b765659548b6b35d7131affa5ec82",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir",
      "new_id": "5241b027da0d4a6fb1095154bedf7ef2a2a07c29",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir"
    }
  ]
}