[LLVMGPU] Add NVIDIA FP8 mma.sync intrinsics for sm_89 and sm_120 (#24659)

Part of #24654

## Summary
Adds NVIDIA FP8 `mma.sync` (m16n8k32) strategy-selection support for Ada
(sm_89) and Blackwell (sm_120). IREE previously had no NVIDIA FP8
support at all — FP8 matmuls silently fell back to SIMT tiling on both
targets.

## Not included
FP8 lowering pipeline support. The TileAndFuse LHS transpose is
hardcoded for element[K]=2 (F16); FP8's element[K]=4 causes a
vector.shape_cast shape mismatch. Will do this in the next PR.

## Test (on RTX PRO 6000 Blackwell, sm_120)

```
PATH=/workspace/iree-build/tools:/workspace/iree-build/llvm-project/bin:$PATH \
  ./llvm-project/bin/llvm-lit -v \
  /workspace/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm89.mlir \
  /workspace/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir \
  /workspace/compiler/src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir
```

```
-- Testing: 3 tests, 3 workers --
PASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm89.mlir (1 of 3)
PASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/config_tile_and_fuse_sm120.mlir (2 of 3)
PASS: IREE :: src/iree/compiler/Codegen/LLVMGPU/test/NVVM/pipeline_tile_and_fuse_mma_sync.mlir (3 of 3)

Testing Time: 0.20s

Total Discovered Tests: 3
  Passed: 3 (100.00%)
```

---------

Signed-off-by: weimin023 <tnwilly@gmail.com>