commit 4247e987d0fdb8a0ead464ceb716d4aff107541e
author Thomas <thomasraoux@google.com> Wed Sep 29 11:16:11 2021 -0700
committer GitHub <noreply@github.com> Wed Sep 29 11:16:11 2021 -0700
tree d461a46f3eec879f019a60e0a39fbf6d5ad60140
parent 5c49556fc7a361a634120b584fdfbaaf8af3ff3d

Fix asan failure in CUDA backend (#7206)

iree/compiler/Codegen/LLVMGPU/LLVMGPUTileAndDistribute.cpp

diff --git a/iree/compiler/Codegen/LLVMGPU/LLVMGPUTileAndDistribute.cpp b/iree/compiler/Codegen/LLVMGPU/LLVMGPUTileAndDistribute.cpp
index 165d711..d06d28a 100644
--- a/iree/compiler/Codegen/LLVMGPU/LLVMGPUTileAndDistribute.cpp
+++ b/iree/compiler/Codegen/LLVMGPU/LLVMGPUTileAndDistribute.cpp
@@ -69,7 +69,8 @@
 /// Patterns for thread level tiling.
 static void populateTilingToInvocationPatterns(
     MLIRContext *context, OwningRewritePatternList &patterns,
-    ArrayRef<int64_t> workgroupSize, ArrayRef<int64_t> workloadPerWorkgroup) {
+    SmallVector<int64_t, 4> &workgroupSize,
+    SmallVector<int64_t, 4> &workloadPerWorkgroup) {
   linalg::TileSizeComputationFunction getInnerTileSizeFn =
       [&](OpBuilder &builder, Operation *operation) {
         SmallVector<Value, 4> tileSizesVal;