)]}'
{
  "commit": "37c79f07d346d969bab825eef37d333c56c7f729",
  "tree": "9b7425c90593a7a71cc8a56ba667988d476dff2a",
  "parents": [
    "fc0dd6ba6899bad16f10ec1d1964592ff1695b0b"
  ],
  "author": {
    "name": "MaheshRavishankar",
    "email": "1663364+MaheshRavishankar@users.noreply.github.com",
    "time": "Tue Jun 27 11:31:33 2023 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 27 11:31:33 2023 -0700"
  },
  "message": "Add support for lowering ops that implement the `UKernelOpInterface` on the CUDA path. (#14101)\n\nThis change add support for lowering operations that implement the\r\n`UKernelOpInterface` on the CUDA backend. This allows custom\r\ndispatches to use ops that implement and be compiled down to CUDA.\r\n\r\nUnlike the CPU side, the CUDA side needs more information than just\r\nthe number of workgroups to use. It also needs the workgroup size. To\r\nallow specifying this, an #iree_codegen.export_config attribute is\r\nadded. This allows specifying the workgroup size to use on the custom\r\ndispatch. This information is used to set the workgroup size to use\r\nduring `MaterializeInterfaces` in HAL.\r\n\r\nAn example of the bitcode usage is added with this PR. Since there are\r\nno in-tree examples of CUDA micro-kernels, the bit code is linked\r\nusing the `iree-link-bitcode` (which is the\r\n`iree-llvmcpu-link-bitcode` renamed).\r\n\r\nFixes #14028",
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