[LLVMCPU][ArmSME] Add `2d-scalable-to-1d-scalable` pass (#16712)

Currently, IREE requires `lowering_config`s to be propagated to all
compute ops within a dispatch region (this was recently implemented for
scalable vectors in #16350). This can be problematic for SME, as it does
not make sense to use 2D-scalability for all ops within a dispatch
region. ArmSME only supports 2D scalable outer products, so if it's not
an outer product, we can only scalably vectorize in one dimension.

The solution here is to add a new pass that runs just before
vectorization, that drops unsupported scalable tile/vector sizes,
producing loops of ops that will only be vectorized scalably in one
dimension. This allows earlier passes like `tile-and-fuse` to still
function correctly.

Take this simple example:

```mlir
// Lowering configs propagated (from matmul):
linalg.fill {lowering_config = [[4], [4]]
linalg.matmul {lowering_config = [[4], [4], 1]
linalg.generic {lowering_config = [[4], [4]]
```
Here the `linalg.generic` cannot be vectorized with 2D scalable vectors.

After `tile-and-fuse` (which requires consistent lowering configs):
```mlir
scf.for i in range(0, 1000) step 4 x vscale {
  scf.for j in range(0, 2000) step 4 x vscale {
    linalg.fill {lowering_config = [[4], [4]]
    for k in range(0, 100) step 1 {
      linalg.matmul {lowering_config = [[4], [4], 1]
    }
    // 2D scalable vectorization unsupported here:
    linalg.generic {lowering_config = [[4], [4]]
  }
}
```

Unsupported scalability removed (by the pass proposed here):
```mlir
scf.for i in range(0, 1000) step 4 x vscale {
  scf.for j in range(0, 2000) step 4 x vscale {
    linalg.fill {lowering_config = [[4], [4]]
    for k in range(0, 100) step 1 {
      linalg.matmul {lowering_config = [[4], [4], 1]
    }
    // Insert a new loop:
    for n in range(0, 4 x vscale) step 4 {
       // Drop a scalable dim:
       linalg.generic {lowering_config = [4, [4]]
    }
  }
}
```

This can now be vectorized and lowered successfully, which produces a
dispatch that mixes SME and SVE.