Integrate LLVM at f59b151f
Signed-off-by: Alan Li <me@alanli.org>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
index c2f002a..23bddd8 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/ROCDL/pipeline_tile_and_fuse.mlir
@@ -832,14 +832,10 @@
// CHECK-DAG: %[[A_READ:.+]] = vector.transfer_read %[[A_ALLOC]]{{.*}} vector<8x1x1x4xf32>
// CHECK-DAG: %[[B_READ:.+]] = vector.transfer_read %[[B_ALLOC]]{{.*}} vector<2x1x1x4xf32>
// CHECK-DAG: %[[C_READ:.+]] = vector.transfer_read %[[BINDING_C]]{{.*}} vector<8x1x2x1x1x4xf32>
-// CHECK-DAG: %[[C_SLICE00:.+]] = vector.extract_strided_slice %[[C_READ]] {{.*}}offsets = [0, 0, 0, 0, 0, 0]{{.*}} : vector<8x1x2x1x1x4xf32> to vector<1x1x1x1x1x4xf32>
-// CHECK-DAG: %[[C_SLICE01:.+]] = vector.extract_strided_slice %[[C_READ]] {{.*}}offsets = [0, 0, 1, 0, 0, 0]{{.*}} : vector<8x1x2x1x1x4xf32> to vector<1x1x1x1x1x4xf32>
-// CHECK-DAG: %[[C_SLICE70:.+]] = vector.extract_strided_slice %[[C_READ]] {{.*}}offsets = [7, 0, 0, 0, 0, 0]{{.*}} : vector<8x1x2x1x1x4xf32> to vector<1x1x1x1x1x4xf32>
-// CHECK-DAG: %[[C_SLICE71:.+]] = vector.extract_strided_slice %[[C_READ]] {{.*}}offsets = [7, 0, 1, 0, 0, 0]{{.*}} : vector<8x1x2x1x1x4xf32> to vector<1x1x1x1x1x4xf32>
-// CHECK-DAG: %[[C_00_0:.+]] = vector.shape_cast %[[C_SLICE00]] : vector<1x1x1x1x1x4xf32> to vector<4xf32>
-// CHECK-DAG: %[[C_01_0:.+]] = vector.shape_cast %[[C_SLICE01]] : vector<1x1x1x1x1x4xf32> to vector<4xf32>
-// CHECK-DAG: %[[C_70_0:.+]] = vector.shape_cast %[[C_SLICE70]] : vector<1x1x1x1x1x4xf32> to vector<4xf32>
-// CHECK-DAG: %[[C_71_0:.+]] = vector.shape_cast %[[C_SLICE71]] : vector<1x1x1x1x1x4xf32> to vector<4xf32>
+// CHECK-DAG: %[[C_00_0:.+]] = vector.extract %[[C_READ]][0, 0, 0, 0, 0] : vector<4xf32> from vector<8x1x2x1x1x4xf32>
+// CHECK-DAG: %[[C_01_0:.+]] = vector.extract %[[C_READ]][0, 0, 1, 0, 0] : vector<4xf32> from vector<8x1x2x1x1x4xf32>
+// CHECK-DAG: %[[C_70_0:.+]] = vector.extract %[[C_READ]][7, 0, 0, 0, 0] : vector<4xf32> from vector<8x1x2x1x1x4xf32>
+// CHECK-DAG: %[[C_71_0:.+]] = vector.extract %[[C_READ]][7, 0, 1, 0, 0] : vector<4xf32> from vector<8x1x2x1x1x4xf32>
// CHECK-DAG: %[[A_EXTRACT00:.+]] = vector.extract %[[A_READ]][0, 0, 0, 0] : f32 from vector<8x1x1x4xf32>
// CHECK-DAG: %[[A_EXTRACT01:.+]] = vector.extract %[[A_READ]][0, 0, 0, 1] : f32 from vector<8x1x1x4xf32>
// CHECK-DAG: %[[A_EXTRACT02:.+]] = vector.extract %[[A_READ]][0, 0, 0, 2] : f32 from vector<8x1x1x4xf32>
diff --git a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/winograd_pipeline_test.mlir b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/winograd_pipeline_test.mlir
index 4173142..135c324 100644
--- a/compiler/src/iree/compiler/Codegen/LLVMGPU/test/winograd_pipeline_test.mlir
+++ b/compiler/src/iree/compiler/Codegen/LLVMGPU/test/winograd_pipeline_test.mlir
@@ -43,9 +43,9 @@
}
// CHECK-LABEL: func.func @winograd_input_transform
// CHECK-NOT: memref.alloc
+// CHECK: vector.transfer_read
+// CHECK: vector.transfer_read
// CHECK: scf.for
-// CHECK: vector.transfer_read
-// CHECK: vector.transfer_read
// CHECK: scf.for
// CHECK: scf.for
// CHECK: vector.transfer_read
@@ -71,9 +71,9 @@
}
// CHECK-LABEL: func.func @winograd_output_transform
// CHECK-NOT: memref.alloc
+// CHECK: vector.transfer_read
+// CHECK: vector.transfer_read
// CHECK: scf.for
-// CHECK: vector.transfer_read
-// CHECK: vector.transfer_read
// CHECK: scf.for
// CHECK: scf.for
// CHECK: vector.transfer_read
diff --git a/third_party/llvm-project b/third_party/llvm-project
index 634c57d..f59b151 160000
--- a/third_party/llvm-project
+++ b/third_party/llvm-project
@@ -1 +1 @@
-Subproject commit 634c57d738e07754b63160b38e3639467c902cdb
+Subproject commit f59b151f094376e135955810f523dcf6b5acde80
