)]}'
{
  "commit": "1c50edd18edcee766cd9d5cd7aa7c9ae8e33b38d",
  "tree": "0fa594793d84f608cccdd792942edd0cf6d8093b",
  "parents": [
    "3a290390659596747fa5cf1bf569710689d1b1e1"
  ],
  "author": {
    "name": "Max191",
    "email": "44243577+Max191@users.noreply.github.com",
    "time": "Tue Aug 06 08:09:06 2024 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Aug 06 11:09:06 2024 -0400"
  },
  "message": "[LLVMGPU] Support i8 MFMA intrinsics in GPUTileAndFuse pipeline (#18104)\n\nThis PR simply adds `MFMA_I8_16x16x32_I32` to the list of allowed enums\r\nin `MMAAttr::populateOperandOffsetsSizesStrides`. This enables the logic\r\nto pack and lower a contraction to this intrinsic with the\r\n`GPUTileAndFuse`. The layout for `MFMA_I8_16x16x32_I32` is very similar\r\nto the layout for `MFMA_F16_16x16x16_F32`, which is already supported,\r\nso the pipeline is already ready to handle the i8 intrinsic case.\r\nNumerical correctness has been verified on an MI300 card for a\r\n256x256x256 matmul.\r\n\r\nSigned-off-by: Max Dawkins \u003cmax.dawkins@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0cfe17e3f96d9e0b0dbd1bccf9db894f1ecc3819",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp",
      "new_id": "c5f99c0ff0312df837209054c34fd3fb26efc158",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.cpp"
    },
    {
      "type": "modify",
      "old_id": "a723155b8bf7c1688c6b57bca194b908cdd40255",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/distribute_multi_mma.mlir",
      "new_id": "ef8ca4b58e1db72f5696a047b9219c4ad5471754",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/Dialect/GPU/TransformExtensions/test/distribute_multi_mma.mlir"
    }
  ]
}