)]}'
{
  "commit": "15008e0e2f9532ef5b8ad3dd1a2d34afefa7d245",
  "tree": "55897b30a0ddf39814a0d9e2cb1a9d72a0164843",
  "parents": [
    "7ead77edbc6212cf232b749744de898b16979959"
  ],
  "author": {
    "name": "Benoit Jacob",
    "email": "jacob.benoit.1@gmail.com",
    "time": "Tue Apr 14 13:54:48 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Apr 14 13:54:48 2026 -0400"
  },
  "message": "[CPU] Stop scaling PackOp distribution tiles by inner pack sizes (#24107)\n\nUndo a 3-year old tiling tweak (#11873) that should not be necessary,\nthough if it ever helped performance, that would indicate suboptimal\ncodegen.\n\nThe rationale, stated in a comment, is that as packing is an\nelement-wise operation, the only reason to need multiple tiles is to\ndistribute work to multiple threads. Memory locality should not be a\nconcern; if it were a concern, that would be a codegen bug (suboptimal\ntraversal within the tile).\n\n\n[Benchmark](https://docs.google.com/spreadsheets/d/1q0pY8uAI4ApGSUndJYAdSq7CKGRzTJgaWlEzMkvSL9A/edit?usp\u003dsharing)\n(3 PRs together: #24107, #24108, #24109) showing no regression across\nmany matmul shapes and slight improvement to scaling SDXL-clip to many\nthreads.\n\nThe point is not the tiny perf improvement per se, but ensuring that\nexisting parameters have the intended semantics.\n\nMade-with: Cursor\n\nSigned-off-by: Benoit Jacob \u003cjacob.benoit.1@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "08a43624467e886e8ecbe953cdc4f0cf35f4cc88",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "bf927ccc3113e91fe504b7ddec1a78db322bfe1d",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "5219b6ec0a42c1e4bc4d4b4d670e3a6890de76df",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "e42e15ffefd809b1f45d7ad84cb2862ed72e56b1",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    },
    {
      "type": "modify",
      "old_id": "2d091d43777381005cbd642eae8a1b692d92932e",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir",
      "new_id": "67dc26996597963edb9ceca1cb65263045840cf1",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_x86_64_lowering_strategy.mlir"
    }
  ]
}