| commit | 988f7c560f484640e910af6f284fa08565bf98dc | [log] [tgz] |
|---|---|---|
| author | bjacob <benoitjacob@google.com> | Fri Nov 03 13:06:02 2023 -0400 |
| committer | GitHub <noreply@github.com> | Fri Nov 03 13:06:02 2023 -0400 |
| tree | 0451d9507e57480c5716157d6c39fc5f569722a0 | |
| parent | a2a2e8d1477b36287b1e67ff8702b596c08c91b6 [diff] |
optimized s16s16s32 mmt4d tile functions on x86 (#15365) This performs well -- faster than `s8s8s32`, as on x86 all the s32-accumulator arithmetic wants s16 LHS/RHS, so the `s8s8s32` ukernels have to extend s8->s16 and this doesn't need to. The main motivation for this though is as a stepping stone towards `s16u4s32` and a more generically useful thing to have to support any bit-width quantization scheme by extending any narrow integers to s16. By contrast, the `s16u4s32` ukernel work that will follow up will be more specialized to one specific use case. `mmt4d_benchmark` results for integer types on AMD Ryzen 9 7950X3D: | benchmark | Gop/s | | ----------------------------------------------------- | ----- | | BM_mmt4d_s8s8s32_tile_1x8x2_avx2_fma/real_time | 56.5 | | BM_mmt4d_s8s8s32_tile_2x8x2_avx2_fma/real_time | 76.6 | | BM_mmt4d_s8s8s32_tile_4x8x2_avx2_fma/real_time | 92.6 | | BM_mmt4d_s8s8s32_tile_8x8x2_avx2_fma/real_time | 184.2 | | BM_mmt4d_s8s8s32_tile_1x16x2_avx512_base/real_time | 39.2 | | BM_mmt4d_s8s8s32_tile_2x16x2_avx512_base/real_time | 50.1 | | BM_mmt4d_s8s8s32_tile_4x16x2_avx512_base/real_time | 57.1 | | BM_mmt4d_s8s8s32_tile_8x16x2_avx512_base/real_time | 114.8 | | BM_mmt4d_s8s8s32_tile_16x16x2_avx512_base/real_time | 241.1 | | BM_mmt4d_s8s8s32_tile_1x16x2_avx512_vnni/real_time | 55.1 | | BM_mmt4d_s8s8s32_tile_2x16x2_avx512_vnni/real_time | 77.9 | | BM_mmt4d_s8s8s32_tile_4x16x2_avx512_vnni/real_time | 88.2 | | BM_mmt4d_s8s8s32_tile_8x16x2_avx512_vnni/real_time | 175.8 | | BM_mmt4d_s8s8s32_tile_16x16x2_avx512_vnni/real_time | 346.8 | | BM_mmt4d_s16s16s32_tile_1x8x2_avx2_fma/real_time | 87.7 | | BM_mmt4d_s16s16s32_tile_2x8x2_avx2_fma/real_time | 86.9 | | BM_mmt4d_s16s16s32_tile_4x8x2_avx2_fma/real_time | 128.0 | | BM_mmt4d_s16s16s32_tile_8x8x2_avx2_fma/real_time | 237.2 | | BM_mmt4d_s16s16s32_tile_1x16x2_avx512_base/real_time | 51.8 | | BM_mmt4d_s16s16s32_tile_2x16x2_avx512_base/real_time | 59.6 | | BM_mmt4d_s16s16s32_tile_4x16x2_avx512_base/real_time | 66.6 | | BM_mmt4d_s16s16s32_tile_8x16x2_avx512_base/real_time | 130.0 | | BM_mmt4d_s16s16s32_tile_16x16x2_avx512_base/real_time | 249.8 | | BM_mmt4d_s16s16s32_tile_1x16x2_avx512_vnni/real_time | 70.3 | | BM_mmt4d_s16s16s32_tile_2x16x2_avx512_vnni/real_time | 86.5 | | BM_mmt4d_s16s16s32_tile_4x16x2_avx512_vnni/real_time | 86.0 | | BM_mmt4d_s16s16s32_tile_8x16x2_avx512_vnni/real_time | 175.8 | | BM_mmt4d_s16s16s32_tile_16x16x2_avx512_vnni/real_time | 345.2 |
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
IREE is still in its early phase. We have settled down on the overarching infrastructure and are actively improving various software components as well as project logistics. It is still quite far from ready for everyday use and is made available without any support at the moment. With that said, we welcome any kind of feedback on any communication channels!
See our website for more information.
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.