Cullen's fix for 16bit shifts in VMVX (#11826)

Fixes #11792. (The diff and testcase are as provided by Cullen there,
plus the i64 case).

Co-authored-by: Cullen Rhodes <cullen.rhodes@arm.com>
diff --git a/compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/ConvertStandardToVM.cpp b/compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/ConvertStandardToVM.cpp
index 26c9eaa..d9f5cc0 100644
--- a/compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/ConvertStandardToVM.cpp
+++ b/compiler/src/iree/compiler/Dialect/VM/Conversion/StandardToVM/ConvertStandardToVM.cpp
@@ -741,11 +741,11 @@
     }
     switch (adaptor.getLhs().getType().getIntOrFloatBitWidth()) {
       case 32:
-        rewriter.replaceOpWithNewOp<Dst32OpTy>(srcOp, srcOp.getType(),
+        rewriter.replaceOpWithNewOp<Dst32OpTy>(srcOp, rewriter.getI32Type(),
                                                adaptor.getLhs(), amount);
         break;
       case 64:
-        rewriter.replaceOpWithNewOp<Dst64OpTy>(srcOp, srcOp.getType(),
+        rewriter.replaceOpWithNewOp<Dst64OpTy>(srcOp, rewriter.getI64Type(),
                                                adaptor.getLhs(), amount);
         break;
       default:
diff --git a/tests/e2e/tosa_ops/BUILD b/tests/e2e/tosa_ops/BUILD
index c970989..acdefb4 100644
--- a/tests/e2e/tosa_ops/BUILD
+++ b/tests/e2e/tosa_ops/BUILD
@@ -41,6 +41,7 @@
         "log.mlir",
         "logical_left_shift.mlir",
         "logical_right_shift.mlir",
+        "logical_right_shift_16.mlir",
         "matmul.mlir",
         "max_pool.mlir",
         "maximum.mlir",
@@ -95,6 +96,7 @@
         "log.mlir",
         "logical_left_shift.mlir",
         "logical_right_shift.mlir",
+        "logical_right_shift_16.mlir",
         "matmul.mlir",
         "max_pool.mlir",
         "maximum.mlir",
@@ -153,6 +155,7 @@
         "log.mlir",
         "logical_left_shift.mlir",
         "logical_right_shift.mlir",
+        "logical_right_shift_16.mlir",
         "matmul.mlir",
         "max_pool.mlir",
         "maximum.mlir",
@@ -231,7 +234,10 @@
         "while.mlir",
     ],
     include = ["*.mlir"],
-    exclude = ["mul_shift.mlir"],  # TODO(#11571)
+    exclude = [
+        "logical_right_shift_16.mlir",  # TODO(#11828)
+        "mul_shift.mlir",  # TODO(#11571)
+    ],
 )
 
 iree_check_single_backend_test_suite(
diff --git a/tests/e2e/tosa_ops/CMakeLists.txt b/tests/e2e/tosa_ops/CMakeLists.txt
index 2b55579..0dca9dd 100644
--- a/tests/e2e/tosa_ops/CMakeLists.txt
+++ b/tests/e2e/tosa_ops/CMakeLists.txt
@@ -35,6 +35,7 @@
     "log.mlir"
     "logical_left_shift.mlir"
     "logical_right_shift.mlir"
+    "logical_right_shift_16.mlir"
     "matmul.mlir"
     "max_pool.mlir"
     "maximum.mlir"
@@ -87,6 +88,7 @@
     "log.mlir"
     "logical_left_shift.mlir"
     "logical_right_shift.mlir"
+    "logical_right_shift_16.mlir"
     "matmul.mlir"
     "max_pool.mlir"
     "maximum.mlir"
@@ -138,6 +140,7 @@
     "log.mlir"
     "logical_left_shift.mlir"
     "logical_right_shift.mlir"
+    "logical_right_shift_16.mlir"
     "matmul.mlir"
     "max_pool.mlir"
     "maximum.mlir"
diff --git a/tests/e2e/tosa_ops/logical_right_shift.mlir b/tests/e2e/tosa_ops/logical_right_shift.mlir
index 4815b28..4d5d357 100644
--- a/tests/e2e/tosa_ops/logical_right_shift.mlir
+++ b/tests/e2e/tosa_ops/logical_right_shift.mlir
@@ -1,4 +1,4 @@
-func.func @tensor() {
+func.func @logical_right_shift() {
   %0 = util.unfoldable_constant dense<[5, 8, 9, 256]> : tensor<4xi32>
   %1 = util.unfoldable_constant dense<[0, 1, 2, 8]> : tensor<4xi32>
   %result = "tosa.logical_right_shift"(%0, %1) : (tensor<4xi32>, tensor<4xi32>) -> tensor<4xi32>
diff --git a/tests/e2e/tosa_ops/logical_right_shift_16.mlir b/tests/e2e/tosa_ops/logical_right_shift_16.mlir
new file mode 100644
index 0000000..7b8c99a
--- /dev/null
+++ b/tests/e2e/tosa_ops/logical_right_shift_16.mlir
@@ -0,0 +1,7 @@
+func.func @logical_right_shift_16() {
+  %0 = util.unfoldable_constant dense<[5, 8, 9, 256]> : tensor<4xi16>
+  %1 = util.unfoldable_constant dense<[0, 1, 2, 8]> : tensor<4xi16>
+  %result = "tosa.logical_right_shift"(%0, %1) : (tensor<4xi16>, tensor<4xi16>) -> tensor<4xi16>
+  check.expect_eq_const(%result, dense<[5, 4, 2, 1]> : tensor<4xi16>) : tensor<4xi16>
+  return
+}