)]}'
{
  "commit": "0df50f9a8e40ab1878479124b952f45d9f8c0650",
  "tree": "9edbe91607d5128aef0f806bbb8d7741d1d5b98c",
  "parents": [
    "d7e6e3925d6a57787ec3bd9b03545d2516a7e60d"
  ],
  "author": {
    "name": "Ege Beysel",
    "email": "beysel@roofline.ai",
    "time": "Fri Sep 11 13:38:17 2026 +0300"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Sep 11 13:38:17 2026 +0300"
  },
  "message": "[LLVMCPU] `vlen` attribute for DataTiledMMAAttr for RISCV + FP16 port (#24858)\n\nFor RISC-V, the vector length per SIMD register is not fixed and is configurable. Therefore, the tile shape of an intrinsic and the total SIMD register bit budget is also parameterized by the vector length. In order for all of these vector length configurations to share a single intrinsic and not duplicate it per-configurable-vlen, we add a `vlen` parameter to the `DataTiledMMAAttr`, which in combination with the intrinsic itself gives the exact shape information, as well as the register budget. These are derived from the `+zvl*b` flags.\n\nFurthermore, add materialization for data-tiled f16 matmul encodings to `iree_codegen.inner_tiled` on RISC-V V targets with Zvfh, as the first consumer of the `vlen` attribute parameter. Lowering to LLVM intrinsics\nis not included.\n\nTowards https://github.com/iree-org/iree/issues/24311\n\nAssisted-by: Claude Code\n\n---------\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
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