)]}'
{
  "commit": "0ce54d6fa2200125f4686ff7f7a898cbb976116b",
  "tree": "17c41c451a720866f37457434ba94e63d715d524",
  "parents": [
    "1a8b8cc56ea97eef9b92ddc0a43607504e82bc61"
  ],
  "author": {
    "name": "Ege Beysel",
    "email": "beysel@roofline.ai",
    "time": "Fri Aug 28 12:08:04 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Aug 28 10:08:04 2026 +0000"
  },
  "message": "[LLVMCPU] infer inner-tile alignment hints for mixed scalability (#24857)\n\nAn inner-tile alignment hint was only captured when the pack/unpack\ninner tile itself was scalable, on the assumption that a static inner\ntile is resolved by static shape inference downstream. That only holds\nwhen the loop tile is static too. A static inner tile under a scalable\nloop tile also needs a hint.\n\nAssisted-by: Claude Code\n\nSigned-off-by: Ege Beysel \u003cbeyselege@gmail.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "a1896ecf0b150354b6b09b39b3e0b7e734b0a897",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
    },
    {
      "type": "modify",
      "old_id": "eae3c8889fd7784bc868ac7e4de8a0467f478b7a",
      "old_mode": 33188,
      "old_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir",
      "new_id": "4f10ee8ed01a5676079cef8e335c58c1a33fde0c",
      "new_mode": 33188,
      "new_path": "compiler/src/iree/compiler/Codegen/LLVMCPU/test/select_aarch64_sve_lowering_strategy.mlir"
    }
  ]
}