)]}'
{
  "commit": "0c9c8aed1ce0019ca77ba061ab39332da8ababfc",
  "tree": "05b0c632eee0bdbbb93e0b3cc845531f1ceb97a7",
  "parents": [
    "b662b5a9fd818c3abaa25ebd172781b869806391"
  ],
  "author": {
    "name": "Diego Caballero",
    "email": "diegocaballero@google.com",
    "time": "Mon Jun 19 11:18:11 2023 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Jun 19 11:18:11 2023 -0700"
  },
  "message": "[CPU] Scalarize vector loads used in a scalar fashion (#14150)\n\nThis PR makes sure that we scalarize the vector load that are used in a\r\nscalar fashion (i.e., vector.transfer_read + vector.extract) in matmuls.\r\nThe LLVM backend is sometimes able to scalarize this vector load but not\r\nalways. For cases where it\u0027s not scalarized, register pressure increases\r\nas the liveness of this vector load spans across all the unrolled\r\niterations of the matmul. There are also some shuffles/permutations\r\ngenerated that don\u0027t make too much sense from the performance point of\r\nview.",
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