[spirv] Remove obsolete pass for distributing copy (#8813)
We have a solution for all backends now. This one is not needed.
diff --git a/iree/compiler/Codegen/Dialect/LoweringConfig.td b/iree/compiler/Codegen/Dialect/LoweringConfig.td
index 5225430..b7bafda 100644
--- a/iree/compiler/Codegen/Dialect/LoweringConfig.td
+++ b/iree/compiler/Codegen/Dialect/LoweringConfig.td
@@ -38,15 +38,13 @@
def SPIRV_Distribute
: I32EnumAttrCase<"SPIRVDistribute", 11>;
-def SPIRV_DistributeCopy
- : I32EnumAttrCase<"SPIRVDistributeCopy", 12>;
def SPIRV_Vectorize
- : I32EnumAttrCase<"SPIRVVectorize", 13>;
+ : I32EnumAttrCase<"SPIRVVectorize", 12>;
def SPIRV_VectorizeToCooperativeOps
- : I32EnumAttrCase<"SPIRVVectorizeToCooperativeOps", 14>;
+ : I32EnumAttrCase<"SPIRVVectorizeToCooperativeOps", 13>;
def None
- : I32EnumAttrCase<"None", 15>;
+ : I32EnumAttrCase<"None", 0xff>;
// EnumAttrCase for all known lowerings for ops within dispatch region
// to scalar/native-vector code.
@@ -57,7 +55,7 @@
CPU_ConvTileAndDecomposeExpert, CPU_TileFuseAndVectorize,
CPU_BufferOpsTileAndVectorize, Linalg_TransformInterpCodegen,
LLVMGPU_SimpleDistribute, LLVMGPU_Vectorize, LLVMGPU_MatmulSimt,
- LLVMGPU_MatmulTensorCore, SPIRV_Distribute, SPIRV_DistributeCopy, SPIRV_Vectorize,
+ LLVMGPU_MatmulTensorCore, SPIRV_Distribute, SPIRV_Vectorize,
SPIRV_VectorizeToCooperativeOps, None]> {
let cppNamespace = "::mlir::iree_compiler::IREE::Codegen";
// Don't generate a C++ class! We want to use the AttrDef
diff --git a/iree/compiler/Codegen/Passes.h b/iree/compiler/Codegen/Passes.h
index 9f5ae99..5594cc3 100644
--- a/iree/compiler/Codegen/Passes.h
+++ b/iree/compiler/Codegen/Passes.h
@@ -383,12 +383,6 @@
void addSPIRVTileAndDistributePassPipeline(OpPassManager &pm);
/// Pass pipeline to lower IREE HAL executables with workgroup tiled and
-/// distributed copies (via flow.dispatch.tensor.load/store pairs) to SPIR-V
-/// scalar code. Additionally performs distribution to threads without
-/// vectorization.
-void addSPIRVTileAndDistributeCopyPassPipeline(OpPassManager &pm);
-
-/// Pass pipeline to lower IREE HAL executables with workgroup tiled and
/// distributed Linalg ops to SPIR-V scalar and vector code. Additionally
/// performs distribution to threads with vectorization.
void addSPIRVTileAndVectorizePassPipeline(OpPassManager &pm);
@@ -415,9 +409,6 @@
std::unique_ptr<OperationPass<IREE::HAL::ExecutableVariantOp>>
createSPIRVLowerExecutableTargetPass();
-/// Initializes CodeGen configuration for the given dispatch region.
-std::unique_ptr<OperationPass<ModuleOp>> createSPIRVInitConfigPass();
-
/// Pass to tile and distribute Linalg ops with buffer semantics to invocations.
std::unique_ptr<OperationPass<func::FuncOp>> createSPIRVTileAndDistributePass();
diff --git a/iree/compiler/Codegen/Passes.td b/iree/compiler/Codegen/Passes.td
index 339c709..c93fdb4 100644
--- a/iree/compiler/Codegen/Passes.td
+++ b/iree/compiler/Codegen/Passes.td
@@ -339,12 +339,6 @@
"mlir::iree_compiler::createSPIRVLowerExecutableTargetPass()";
}
-def SPIRVInitConfig :
- Pass<"iree-spirv-init-config-pass", "ModuleOp"> {
- let summary = "Initialize CodeGen configuration for a given dispatch region";
- let constructor = "mlir::iree_compiler::createSPIRVInitConfigPass()";
-}
-
def SPIRVTile : Pass<"iree-spirv-tile", "func::FuncOp"> {
let summary = "Tile Linalg ops with tensor semantics to invocations";
let constructor = "mlir::iree_compiler::createSPIRVTilePass()";
diff --git a/iree/compiler/Codegen/SPIRV/BUILD b/iree/compiler/Codegen/SPIRV/BUILD
index f16128b..12115b0 100644
--- a/iree/compiler/Codegen/SPIRV/BUILD
+++ b/iree/compiler/Codegen/SPIRV/BUILD
@@ -22,7 +22,6 @@
"SPIRVCreateFastSlowPath.cpp",
"SPIRVDistribute.cpp",
"SPIRVFuseTensorPadWithConsumer.cpp",
- "SPIRVInitConfigPass.cpp",
"SPIRVLowerExecutableTargetPass.cpp",
"SPIRVTile.cpp",
"SPIRVTileAndDistribute.cpp",
diff --git a/iree/compiler/Codegen/SPIRV/CMakeLists.txt b/iree/compiler/Codegen/SPIRV/CMakeLists.txt
index e751f02..cea4c3b 100644
--- a/iree/compiler/Codegen/SPIRV/CMakeLists.txt
+++ b/iree/compiler/Codegen/SPIRV/CMakeLists.txt
@@ -27,7 +27,6 @@
"SPIRVCreateFastSlowPath.cpp"
"SPIRVDistribute.cpp"
"SPIRVFuseTensorPadWithConsumer.cpp"
- "SPIRVInitConfigPass.cpp"
"SPIRVLowerExecutableTargetPass.cpp"
"SPIRVTile.cpp"
"SPIRVTileAndDistribute.cpp"
diff --git a/iree/compiler/Codegen/SPIRV/Passes.cpp b/iree/compiler/Codegen/SPIRV/Passes.cpp
index f59b823..d8e5c53 100644
--- a/iree/compiler/Codegen/SPIRV/Passes.cpp
+++ b/iree/compiler/Codegen/SPIRV/Passes.cpp
@@ -220,36 +220,6 @@
addLoopMaterializationPasses(pm);
}
-// An ad-hoc pipeline for tiling and distributing padding/copy ops. This is
-// needed to migrate from a bufferization-first world to a vectorization-first
-// world.
-//
-// In the former path for CodeGen, we perform bufferization first, which will
-// turn padding/copy (via flow.dispatch.tensor.load/store pairs) into
-// linalg.generic ops. Then we deduce CodeGen configuration from the linalg.copy
-// op and use a `lowering_config` attribute on it to drive transformations.
-//
-// In the latter path for CodeGen, we will see linalg.pad_tensor directly.
-// However, properly tiling and distributing it is an ongoing work. So for now
-// still perform bufferization first to expose a linalg.copy op, from which we
-// can deduce the configuration.
-void addSPIRVTileAndDistributeCopyPassPipeline(OpPassManager &pm) {
- addLinalgBufferizePasses(pm, gpuAllocationFunction);
- pm.addPass(createSPIRVInitConfigPass());
-
- pm.addNestedPass<func::FuncOp>(createInsertDistributionInfoPass());
- pm.addNestedPass<func::FuncOp>(createTileAndDistributeToWorkgroupsPass());
- pm.addPass(createCanonicalizerPass());
- pm.addPass(createCSEPass());
-
- // Tile and distribute to GPU invocations.
- pm.addNestedPass<func::FuncOp>(createSPIRVTileAndDistributePass());
- pm.addPass(createCanonicalizerPass());
- pm.addPass(createCSEPass());
-
- addLoopMaterializationPasses(pm);
-}
-
//===----------------------------------------------------------------------===//
// Entry Point
//===----------------------------------------------------------------------===//
diff --git a/iree/compiler/Codegen/SPIRV/SPIRVInitConfigPass.cpp b/iree/compiler/Codegen/SPIRV/SPIRVInitConfigPass.cpp
deleted file mode 100644
index c8b77cc..0000000
--- a/iree/compiler/Codegen/SPIRV/SPIRVInitConfigPass.cpp
+++ /dev/null
@@ -1,44 +0,0 @@
-// Copyright 2021 The IREE Authors
-//
-// Licensed under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-
-#include "iree/compiler/Codegen/Dialect/IREECodegenDialect.h"
-#include "iree/compiler/Codegen/PassDetail.h"
-#include "iree/compiler/Codegen/Passes.h"
-#include "iree/compiler/Codegen/SPIRV/KernelConfig.h"
-#include "iree/compiler/Dialect/HAL/IR/HALOps.h"
-#include "llvm/Support/Debug.h"
-#include "mlir/Pass/Pass.h"
-#include "mlir/Pass/PassManager.h"
-#include "mlir/Pass/PassRegistry.h"
-
-#define DEBUG_TYPE "iree-spirv-init-config-pass"
-
-namespace mlir {
-namespace iree_compiler {
-
-namespace {
-
-/// Initializes CodeGen configuration for a dispatch region.
-class SPIRVInitConfigPass : public SPIRVInitConfigBase<SPIRVInitConfigPass> {
- public:
- void getDependentDialects(DialectRegistry ®istry) const override {
- registry.insert<IREE::Codegen::IREECodegenDialect>();
- }
-
- void runOnOperation() override {
- ModuleOp moduleOp = getOperation();
- if (failed(initSPIRVLaunchConfig(moduleOp))) return signalPassFailure();
- }
-};
-
-} // namespace
-
-std::unique_ptr<OperationPass<ModuleOp>> createSPIRVInitConfigPass() {
- return std::make_unique<SPIRVInitConfigPass>();
-}
-
-} // namespace iree_compiler
-} // namespace mlir
diff --git a/iree/compiler/Codegen/SPIRV/SPIRVLowerExecutableTargetPass.cpp b/iree/compiler/Codegen/SPIRV/SPIRVLowerExecutableTargetPass.cpp
index 31652de..c65e1e3 100644
--- a/iree/compiler/Codegen/SPIRV/SPIRVLowerExecutableTargetPass.cpp
+++ b/iree/compiler/Codegen/SPIRV/SPIRVLowerExecutableTargetPass.cpp
@@ -100,9 +100,6 @@
case IREE::Codegen::DispatchLoweringPassPipeline::SPIRVDistribute:
addSPIRVTileAndDistributePassPipeline(nestedModulePM);
break;
- case IREE::Codegen::DispatchLoweringPassPipeline::SPIRVDistributeCopy:
- addSPIRVTileAndDistributeCopyPassPipeline(nestedModulePM);
- break;
case IREE::Codegen::DispatchLoweringPassPipeline::SPIRVVectorize:
addSPIRVTileAndVectorizePassPipeline(nestedModulePM);
break;
