[spirv] Add conv CodeGen configuration for Adreno GPUs (#7001) Similar to matmul, this enables tiling and vectorizing conv ops for Adreno GPUs. The goal is to eventually promote what's here as the default for all targets, including Mali GPUs, so that we can remove the hardcoded known good configurations. But for now starting with Adreno to make sure they work fine. Along the way, moved the "fourth-level" tiling into the pattern itself. It's really fundamentally different than the others. We don't have four levels of compute hierarchies on GPU to map to. We just used it as a way to materialize the loops around filter height and width. It's required for applicability and correctness for the pattern itself and is always the same, not tunable knobs that change according to the input.
IREE (Intermediate Representation Execution Environment, pronounced as “eerie”) is an MLIR-based end-to-end compiler and runtime that lowers Machine Learning (ML) models to a unified IR that scales up to meet the needs of the datacenter and down to satisfy the constraints and special considerations of mobile and edge deployments.
See our website for project details, user guides, and instructions on building from source.
IREE is still in its early phase. We have settled down on the overarching infrastructure and are actively improving various software components as well as project logistics. It is still quite far from ready for everyday use and is made available without any support at the moment. With that said, we welcome any kind of feedback on any communication channels!
IREE is licensed under the terms of the Apache 2.0 License with LLVM Exceptions. See LICENSE for more information.