)]}'
{
  "commit": "00a3f2c1a46ff9167c567ee3466baaf8c8a0d881",
  "tree": "cd3c0063740b2fbffaf455d5c543995288e225a4",
  "parents": [
    "1407c5e76639c90c68b9df4ca9b9a5d9d53bc17f"
  ],
  "author": {
    "name": "Han-Chung Wang",
    "email": "hanchung@google.com",
    "time": "Thu Mar 10 09:53:07 2022 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Mar 10 09:53:07 2022 -0800"
  },
  "message": "Heuristically pick up tiling sizes to vectorize Linalg operations. (#8517)\n\nConfigurations: taskset 80 + dylib-sync on local Pixel 4\r\n\r\n| Model            | Before  | After   |\r\n| ---------------- | ------- | ------- |\r\n| DeepLabV3        | 711 ms  | 188 ms  |\r\n| MobileBertSquad  | 672 ms  | 673 ms  |\r\n| MobileNetV2      | 103 ms  | 46.4 ms |\r\n| MobileNetV3Small | 24.6 ms | 14.6 ms |\r\n| MobileSSD        | 204 ms  | 166 ms  |\r\n| PoseNet          | 545 ms  | 241 ms  |\r\n\r\nConfigurations: taskset f0 + dylib on local Pixel 4\r\n\r\n| Model            | Before  | After   |\r\n| ---------------- | ------- | ------- |\r\n| DeepLabV3        | 358 ms  | 161 ms  |\r\n| MobileBertSquad  | 376 ms  | 376 ms  |\r\n| MobileNetV2      | 65.6 ms | 29.8 ms |\r\n| MobileNetV3Small | 20.7 ms | 15.7 ms |\r\n| MobileSSD        | 94 ms   | 79.9 ms |\r\n| PoseNet          | 183 ms  | 121 ms  |",
  "tree_diff": [
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      "old_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp",
      "new_id": "7dcf9d3a8c4ff41734a40c3022fe7ed134ad0aab",
      "new_mode": 33188,
      "new_path": "iree/compiler/Codegen/LLVMCPU/KernelDispatch.cpp"
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}