---
title: "User Guides"
---

* Getting Started
  * [Getting started]({{< relref "getting_started.md" >}})
  * [Quickstart]({{< relref "quickstart.md" >}})
  * [Notes on using GitHub and local git]({{< relref "github_notes.md" >}})
  * [Directory Structure]({{< relref "directory_structure.md" >}})
  * [Installing Build Requirements]({{< relref "install_instructions" >}})
  * [Build software]({{< relref "getting_started_sw.md" >}})
  * [Getting started with Verilator]({{< relref "getting_started_verilator.md" >}})
  * [Getting started on FPGAs]({{< relref "getting_started_fpga.md" >}})
    * [Obtaining an FPGA board]({{< relref "fpga_boards.md" >}})
    * [Installing Xilinx Vivado]({{< relref "install_instructions#xilinx-vivado" >}})
  * [Getting started with a design]({{< relref "getting_started_design.md" >}})
  * [Getting started with verification]({{< relref "getting_started_dv.md" >}})
* [Work with hardware code in external repositories]({{< relref "vendor_hw.md" >}})
* [Design Methodology]({{< relref "design.md" >}})
  * Language and Tool Selection
  * Comportability and the Importance of Architectural Conformity
  * Defining Design Complete: stages and tracking
  * Documentation
  * Usage of Register Tool
  * Linting Methodology
  * Assertions Methodology
  * CDC Methodology
  * DFT
  * Generated Code
  * FPGA vs ASIC
* [Design Verification Methodology]({{< relref "doc/ug/dv_methodology" >}})
  * Language and Tool Selection
  * Defining Verification Complete: Stages and Checklists
  * Documentation
  * Automation
  * Code Reuse
  * DV Efforts in OpenTitan
  * Key Test Focus Areas
  * Assertions
  * Regressions
  * Coverage Collection
  * FPV
  * Reviews
  * Filing Issues
  * Pending Work Items