tree 96d827c53b3e21518187a0cf0b44edde2b59d94b
parent 50fe3b9fd45fdfb1fa555da66995dfd94023143f
author Michael Schaffner <msf@opentitan.org> 1622567094 -0700
committer Michael Schaffner <msf@google.com> 1622575564 -0700

[chiplevel/padring] Correct mio_in_raw connection width for FPGA targets

Fix #6774

This did not affect the ASIC target as the MIO array has no stubbed pads
in that case.

Signed-off-by: Michael Schaffner <msf@opentitan.org>