diff --git a/hw/ip/prim_generic/prim_generic_clock_mux2.core b/hw/ip/prim_generic/prim_generic_clock_mux2.core
index 3839290..f84fbfc 100644
--- a/hw/ip/prim_generic/prim_generic_clock_mux2.core
+++ b/hw/ip/prim_generic/prim_generic_clock_mux2.core
@@ -7,6 +7,8 @@
 description: "two-input clock multiplexer primitive"
 filesets:
   files_rtl:
+    depend:
+      - lowrisc:prim:assert
     files:
       - rtl/prim_generic_clock_mux2.sv
     file_type: systemVerilogSource
diff --git a/hw/ip/prim_generic/prim_generic_pad_wrapper.core b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
index 3e23699..aca1790 100644
--- a/hw/ip/prim_generic/prim_generic_pad_wrapper.core
+++ b/hw/ip/prim_generic/prim_generic_pad_wrapper.core
@@ -7,6 +7,8 @@
 description: "Technology-independent pad wrapper implementation (for sim only!)"
 filesets:
   files_rtl:
+    depend:
+      - lowrisc:prim:assert
     files:
       - rtl/prim_generic_pad_wrapper.sv
     file_type: systemVerilogSource
diff --git a/hw/ip/prim_generic/prim_generic_ram_1p.core b/hw/ip/prim_generic/prim_generic_ram_1p.core
index 5863ab7..7e96d4b 100644
--- a/hw/ip/prim_generic/prim_generic_ram_1p.core
+++ b/hw/ip/prim_generic/prim_generic_ram_1p.core
@@ -8,6 +8,7 @@
 filesets:
   files_rtl:
     depend:
+      - lowrisc:prim:assert
       - lowrisc:prim:util_memload
     files:
       - rtl/prim_generic_ram_1p.sv