| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| |
| /* automatically generated by rust-bindgen 0.60.1 */ |
| |
| pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65; |
| pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 22; |
| pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5; |
| pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32; |
| pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16; |
| pub const ALERT_HANDLER_PARAM_N_CLASSES: u32 = 4; |
| pub const ALERT_HANDLER_PARAM_N_ESC_SEV: u32 = 4; |
| pub const ALERT_HANDLER_PARAM_N_PHASES: u32 = 4; |
| pub const ALERT_HANDLER_PARAM_N_LOC_ALERT: u32 = 7; |
| pub const ALERT_HANDLER_PARAM_PING_CNT_DW: u32 = 16; |
| pub const ALERT_HANDLER_PARAM_PHASE_DW: u32 = 2; |
| pub const ALERT_HANDLER_PARAM_CLASS_DW: u32 = 2; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL: u32 = 0; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL: u32 = 1; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL: u32 = 2; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL: u32 = 3; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL: u32 = 4; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR: u32 = 5; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR: u32 = 6; |
| pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST: u32 = 6; |
| pub const ALERT_HANDLER_PARAM_REG_WIDTH: u32 = 32; |
| pub const ALERT_HANDLER_INTR_COMMON_CLASSA_BIT: u32 = 0; |
| pub const ALERT_HANDLER_INTR_COMMON_CLASSB_BIT: u32 = 1; |
| pub const ALERT_HANDLER_INTR_COMMON_CLASSC_BIT: u32 = 2; |
| pub const ALERT_HANDLER_INTR_COMMON_CLASSD_BIT: u32 = 3; |
| pub const ALERT_HANDLER_INTR_STATE_REG_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_INTR_STATE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_INTR_STATE_CLASSA_BIT: u32 = 0; |
| pub const ALERT_HANDLER_INTR_STATE_CLASSB_BIT: u32 = 1; |
| pub const ALERT_HANDLER_INTR_STATE_CLASSC_BIT: u32 = 2; |
| pub const ALERT_HANDLER_INTR_STATE_CLASSD_BIT: u32 = 3; |
| pub const ALERT_HANDLER_INTR_ENABLE_REG_OFFSET: u32 = 4; |
| pub const ALERT_HANDLER_INTR_ENABLE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_INTR_ENABLE_CLASSA_BIT: u32 = 0; |
| pub const ALERT_HANDLER_INTR_ENABLE_CLASSB_BIT: u32 = 1; |
| pub const ALERT_HANDLER_INTR_ENABLE_CLASSC_BIT: u32 = 2; |
| pub const ALERT_HANDLER_INTR_ENABLE_CLASSD_BIT: u32 = 3; |
| pub const ALERT_HANDLER_INTR_TEST_REG_OFFSET: u32 = 8; |
| pub const ALERT_HANDLER_INTR_TEST_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_INTR_TEST_CLASSA_BIT: u32 = 0; |
| pub const ALERT_HANDLER_INTR_TEST_CLASSB_BIT: u32 = 1; |
| pub const ALERT_HANDLER_INTR_TEST_CLASSC_BIT: u32 = 2; |
| pub const ALERT_HANDLER_INTR_TEST_CLASSD_BIT: u32 = 3; |
| pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_OFFSET: u32 = 12; |
| pub const ALERT_HANDLER_PING_TIMER_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_PING_TIMER_REGWEN_PING_TIMER_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 16; |
| pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 256; |
| pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_PING_TIMEOUT_CYC_SHADOWED_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_OFFSET: u32 = 20; |
| pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_PING_TIMER_EN_SHADOWED_PING_TIMER_EN_SHADOWED_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_MULTIREG_COUNT: u32 = 65; |
| pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_OFFSET: u32 = 24; |
| pub const ALERT_HANDLER_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_OFFSET: u32 = 28; |
| pub const ALERT_HANDLER_ALERT_REGWEN_1_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_1_EN_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_OFFSET: u32 = 32; |
| pub const ALERT_HANDLER_ALERT_REGWEN_2_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_2_EN_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_OFFSET: u32 = 36; |
| pub const ALERT_HANDLER_ALERT_REGWEN_3_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_3_EN_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_OFFSET: u32 = 40; |
| pub const ALERT_HANDLER_ALERT_REGWEN_4_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_4_EN_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_OFFSET: u32 = 44; |
| pub const ALERT_HANDLER_ALERT_REGWEN_5_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_5_EN_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_OFFSET: u32 = 48; |
| pub const ALERT_HANDLER_ALERT_REGWEN_6_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_6_EN_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_OFFSET: u32 = 52; |
| pub const ALERT_HANDLER_ALERT_REGWEN_7_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_7_EN_7_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_OFFSET: u32 = 56; |
| pub const ALERT_HANDLER_ALERT_REGWEN_8_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_8_EN_8_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_OFFSET: u32 = 60; |
| pub const ALERT_HANDLER_ALERT_REGWEN_9_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_9_EN_9_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_OFFSET: u32 = 64; |
| pub const ALERT_HANDLER_ALERT_REGWEN_10_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_10_EN_10_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_OFFSET: u32 = 68; |
| pub const ALERT_HANDLER_ALERT_REGWEN_11_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_11_EN_11_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_OFFSET: u32 = 72; |
| pub const ALERT_HANDLER_ALERT_REGWEN_12_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_12_EN_12_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_OFFSET: u32 = 76; |
| pub const ALERT_HANDLER_ALERT_REGWEN_13_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_13_EN_13_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_OFFSET: u32 = 80; |
| pub const ALERT_HANDLER_ALERT_REGWEN_14_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_14_EN_14_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_OFFSET: u32 = 84; |
| pub const ALERT_HANDLER_ALERT_REGWEN_15_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_15_EN_15_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_OFFSET: u32 = 88; |
| pub const ALERT_HANDLER_ALERT_REGWEN_16_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_16_EN_16_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_OFFSET: u32 = 92; |
| pub const ALERT_HANDLER_ALERT_REGWEN_17_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_17_EN_17_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_OFFSET: u32 = 96; |
| pub const ALERT_HANDLER_ALERT_REGWEN_18_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_18_EN_18_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_OFFSET: u32 = 100; |
| pub const ALERT_HANDLER_ALERT_REGWEN_19_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_19_EN_19_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_OFFSET: u32 = 104; |
| pub const ALERT_HANDLER_ALERT_REGWEN_20_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_20_EN_20_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_OFFSET: u32 = 108; |
| pub const ALERT_HANDLER_ALERT_REGWEN_21_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_21_EN_21_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_OFFSET: u32 = 112; |
| pub const ALERT_HANDLER_ALERT_REGWEN_22_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_22_EN_22_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_OFFSET: u32 = 116; |
| pub const ALERT_HANDLER_ALERT_REGWEN_23_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_23_EN_23_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_OFFSET: u32 = 120; |
| pub const ALERT_HANDLER_ALERT_REGWEN_24_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_24_EN_24_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_OFFSET: u32 = 124; |
| pub const ALERT_HANDLER_ALERT_REGWEN_25_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_25_EN_25_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_OFFSET: u32 = 128; |
| pub const ALERT_HANDLER_ALERT_REGWEN_26_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_26_EN_26_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_OFFSET: u32 = 132; |
| pub const ALERT_HANDLER_ALERT_REGWEN_27_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_27_EN_27_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_OFFSET: u32 = 136; |
| pub const ALERT_HANDLER_ALERT_REGWEN_28_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_28_EN_28_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_OFFSET: u32 = 140; |
| pub const ALERT_HANDLER_ALERT_REGWEN_29_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_29_EN_29_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_OFFSET: u32 = 144; |
| pub const ALERT_HANDLER_ALERT_REGWEN_30_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_30_EN_30_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_OFFSET: u32 = 148; |
| pub const ALERT_HANDLER_ALERT_REGWEN_31_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_31_EN_31_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_OFFSET: u32 = 152; |
| pub const ALERT_HANDLER_ALERT_REGWEN_32_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_32_EN_32_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_OFFSET: u32 = 156; |
| pub const ALERT_HANDLER_ALERT_REGWEN_33_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_33_EN_33_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_OFFSET: u32 = 160; |
| pub const ALERT_HANDLER_ALERT_REGWEN_34_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_34_EN_34_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_OFFSET: u32 = 164; |
| pub const ALERT_HANDLER_ALERT_REGWEN_35_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_35_EN_35_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_OFFSET: u32 = 168; |
| pub const ALERT_HANDLER_ALERT_REGWEN_36_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_36_EN_36_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_OFFSET: u32 = 172; |
| pub const ALERT_HANDLER_ALERT_REGWEN_37_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_37_EN_37_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_OFFSET: u32 = 176; |
| pub const ALERT_HANDLER_ALERT_REGWEN_38_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_38_EN_38_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_OFFSET: u32 = 180; |
| pub const ALERT_HANDLER_ALERT_REGWEN_39_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_39_EN_39_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_OFFSET: u32 = 184; |
| pub const ALERT_HANDLER_ALERT_REGWEN_40_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_40_EN_40_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_OFFSET: u32 = 188; |
| pub const ALERT_HANDLER_ALERT_REGWEN_41_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_41_EN_41_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_OFFSET: u32 = 192; |
| pub const ALERT_HANDLER_ALERT_REGWEN_42_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_42_EN_42_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_OFFSET: u32 = 196; |
| pub const ALERT_HANDLER_ALERT_REGWEN_43_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_43_EN_43_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_OFFSET: u32 = 200; |
| pub const ALERT_HANDLER_ALERT_REGWEN_44_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_44_EN_44_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_OFFSET: u32 = 204; |
| pub const ALERT_HANDLER_ALERT_REGWEN_45_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_45_EN_45_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_OFFSET: u32 = 208; |
| pub const ALERT_HANDLER_ALERT_REGWEN_46_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_46_EN_46_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_OFFSET: u32 = 212; |
| pub const ALERT_HANDLER_ALERT_REGWEN_47_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_47_EN_47_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_OFFSET: u32 = 216; |
| pub const ALERT_HANDLER_ALERT_REGWEN_48_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_48_EN_48_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_OFFSET: u32 = 220; |
| pub const ALERT_HANDLER_ALERT_REGWEN_49_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_49_EN_49_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_OFFSET: u32 = 224; |
| pub const ALERT_HANDLER_ALERT_REGWEN_50_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_50_EN_50_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_OFFSET: u32 = 228; |
| pub const ALERT_HANDLER_ALERT_REGWEN_51_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_51_EN_51_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_OFFSET: u32 = 232; |
| pub const ALERT_HANDLER_ALERT_REGWEN_52_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_52_EN_52_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_OFFSET: u32 = 236; |
| pub const ALERT_HANDLER_ALERT_REGWEN_53_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_53_EN_53_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_OFFSET: u32 = 240; |
| pub const ALERT_HANDLER_ALERT_REGWEN_54_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_54_EN_54_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_OFFSET: u32 = 244; |
| pub const ALERT_HANDLER_ALERT_REGWEN_55_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_55_EN_55_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_OFFSET: u32 = 248; |
| pub const ALERT_HANDLER_ALERT_REGWEN_56_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_56_EN_56_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_OFFSET: u32 = 252; |
| pub const ALERT_HANDLER_ALERT_REGWEN_57_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_57_EN_57_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_OFFSET: u32 = 256; |
| pub const ALERT_HANDLER_ALERT_REGWEN_58_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_58_EN_58_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_OFFSET: u32 = 260; |
| pub const ALERT_HANDLER_ALERT_REGWEN_59_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_59_EN_59_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_OFFSET: u32 = 264; |
| pub const ALERT_HANDLER_ALERT_REGWEN_60_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_60_EN_60_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_OFFSET: u32 = 268; |
| pub const ALERT_HANDLER_ALERT_REGWEN_61_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_61_EN_61_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_OFFSET: u32 = 272; |
| pub const ALERT_HANDLER_ALERT_REGWEN_62_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_62_EN_62_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_OFFSET: u32 = 276; |
| pub const ALERT_HANDLER_ALERT_REGWEN_63_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_63_EN_63_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_OFFSET: u32 = 280; |
| pub const ALERT_HANDLER_ALERT_REGWEN_64_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_REGWEN_64_EN_64_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_EN_A_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 65; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 284; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_0_EN_A_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 288; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_1_EN_A_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 292; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_2_EN_A_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 296; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_3_EN_A_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 300; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_4_EN_A_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 304; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_5_EN_A_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 308; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_6_EN_A_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_OFFSET: u32 = 312; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_7_EN_A_7_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_OFFSET: u32 = 316; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_8_EN_A_8_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_OFFSET: u32 = 320; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_9_EN_A_9_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_OFFSET: u32 = 324; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_10_EN_A_10_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_OFFSET: u32 = 328; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_11_EN_A_11_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_OFFSET: u32 = 332; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_12_EN_A_12_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_OFFSET: u32 = 336; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_13_EN_A_13_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_OFFSET: u32 = 340; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_14_EN_A_14_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_OFFSET: u32 = 344; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_15_EN_A_15_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_OFFSET: u32 = 348; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_16_EN_A_16_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_OFFSET: u32 = 352; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_17_EN_A_17_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_OFFSET: u32 = 356; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_18_EN_A_18_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_OFFSET: u32 = 360; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_19_EN_A_19_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_OFFSET: u32 = 364; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_20_EN_A_20_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_OFFSET: u32 = 368; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_21_EN_A_21_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_OFFSET: u32 = 372; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_22_EN_A_22_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_OFFSET: u32 = 376; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_23_EN_A_23_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_OFFSET: u32 = 380; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_24_EN_A_24_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_OFFSET: u32 = 384; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_25_EN_A_25_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_OFFSET: u32 = 388; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_26_EN_A_26_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_OFFSET: u32 = 392; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_27_EN_A_27_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_OFFSET: u32 = 396; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_28_EN_A_28_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_OFFSET: u32 = 400; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_29_EN_A_29_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_OFFSET: u32 = 404; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_30_EN_A_30_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_OFFSET: u32 = 408; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_31_EN_A_31_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_OFFSET: u32 = 412; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_32_EN_A_32_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_OFFSET: u32 = 416; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_33_EN_A_33_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_OFFSET: u32 = 420; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_34_EN_A_34_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_OFFSET: u32 = 424; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_35_EN_A_35_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_OFFSET: u32 = 428; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_36_EN_A_36_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_OFFSET: u32 = 432; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_37_EN_A_37_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_OFFSET: u32 = 436; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_38_EN_A_38_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_OFFSET: u32 = 440; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_39_EN_A_39_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_OFFSET: u32 = 444; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_40_EN_A_40_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_OFFSET: u32 = 448; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_41_EN_A_41_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_OFFSET: u32 = 452; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_42_EN_A_42_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_OFFSET: u32 = 456; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_43_EN_A_43_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_OFFSET: u32 = 460; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_44_EN_A_44_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_OFFSET: u32 = 464; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_45_EN_A_45_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_OFFSET: u32 = 468; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_46_EN_A_46_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_OFFSET: u32 = 472; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_47_EN_A_47_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_OFFSET: u32 = 476; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_48_EN_A_48_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_OFFSET: u32 = 480; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_49_EN_A_49_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_OFFSET: u32 = 484; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_50_EN_A_50_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_OFFSET: u32 = 488; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_51_EN_A_51_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_OFFSET: u32 = 492; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_52_EN_A_52_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_OFFSET: u32 = 496; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_53_EN_A_53_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_OFFSET: u32 = 500; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_54_EN_A_54_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_OFFSET: u32 = 504; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_55_EN_A_55_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_OFFSET: u32 = 508; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_56_EN_A_56_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_OFFSET: u32 = 512; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_57_EN_A_57_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_OFFSET: u32 = 516; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_58_EN_A_58_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_OFFSET: u32 = 520; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_59_EN_A_59_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_OFFSET: u32 = 524; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_60_EN_A_60_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_OFFSET: u32 = 528; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_61_EN_A_61_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_OFFSET: u32 = 532; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_62_EN_A_62_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_OFFSET: u32 = 536; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_63_EN_A_63_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_OFFSET: u32 = 540; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_EN_SHADOWED_64_EN_A_64_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_CLASS_A_FIELD_WIDTH: u32 = 2; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 65; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 544; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSA: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSB: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSC: u32 = 2; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_CLASS_A_0_VALUE_CLASSD: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 548; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_CLASS_A_1_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 552; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_CLASS_A_2_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 556; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_CLASS_A_3_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 560; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_CLASS_A_4_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 564; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_CLASS_A_5_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 568; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_CLASS_A_6_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_OFFSET: u32 = 572; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_CLASS_A_7_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_OFFSET: u32 = 576; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_CLASS_A_8_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_OFFSET: u32 = 580; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_CLASS_A_9_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_OFFSET: u32 = 584; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_CLASS_A_10_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_OFFSET: u32 = 588; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_CLASS_A_11_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_OFFSET: u32 = 592; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_CLASS_A_12_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_OFFSET: u32 = 596; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_CLASS_A_13_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_OFFSET: u32 = 600; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_CLASS_A_14_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_OFFSET: u32 = 604; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_CLASS_A_15_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_OFFSET: u32 = 608; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_CLASS_A_16_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_OFFSET: u32 = 612; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_CLASS_A_17_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_OFFSET: u32 = 616; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_CLASS_A_18_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_OFFSET: u32 = 620; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_CLASS_A_19_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_OFFSET: u32 = 624; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_CLASS_A_20_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_OFFSET: u32 = 628; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_CLASS_A_21_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_OFFSET: u32 = 632; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_CLASS_A_22_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_OFFSET: u32 = 636; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_CLASS_A_23_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_OFFSET: u32 = 640; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_CLASS_A_24_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_OFFSET: u32 = 644; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_CLASS_A_25_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_OFFSET: u32 = 648; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_CLASS_A_26_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_OFFSET: u32 = 652; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_CLASS_A_27_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_OFFSET: u32 = 656; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_CLASS_A_28_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_OFFSET: u32 = 660; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_CLASS_A_29_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_OFFSET: u32 = 664; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_CLASS_A_30_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_OFFSET: u32 = 668; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_CLASS_A_31_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_OFFSET: u32 = 672; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_CLASS_A_32_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_OFFSET: u32 = 676; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_CLASS_A_33_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_OFFSET: u32 = 680; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_CLASS_A_34_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_OFFSET: u32 = 684; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_CLASS_A_35_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_OFFSET: u32 = 688; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_CLASS_A_36_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_OFFSET: u32 = 692; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_CLASS_A_37_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_OFFSET: u32 = 696; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_CLASS_A_38_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_OFFSET: u32 = 700; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_CLASS_A_39_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_OFFSET: u32 = 704; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_CLASS_A_40_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_OFFSET: u32 = 708; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_CLASS_A_41_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_OFFSET: u32 = 712; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_CLASS_A_42_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_OFFSET: u32 = 716; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_CLASS_A_43_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_OFFSET: u32 = 720; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_CLASS_A_44_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_OFFSET: u32 = 724; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_CLASS_A_45_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_OFFSET: u32 = 728; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_CLASS_A_46_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_OFFSET: u32 = 732; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_CLASS_A_47_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_OFFSET: u32 = 736; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_CLASS_A_48_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_OFFSET: u32 = 740; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_CLASS_A_49_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_OFFSET: u32 = 744; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_CLASS_A_50_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_OFFSET: u32 = 748; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_CLASS_A_51_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_OFFSET: u32 = 752; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_CLASS_A_52_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_OFFSET: u32 = 756; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_CLASS_A_53_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_OFFSET: u32 = 760; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_CLASS_A_54_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_OFFSET: u32 = 764; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_CLASS_A_55_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_OFFSET: u32 = 768; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_CLASS_A_56_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_OFFSET: u32 = 772; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_CLASS_A_57_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_OFFSET: u32 = 776; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_CLASS_A_58_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_OFFSET: u32 = 780; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_CLASS_A_59_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_OFFSET: u32 = 784; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_CLASS_A_60_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_OFFSET: u32 = 788; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_CLASS_A_61_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_OFFSET: u32 = 792; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_CLASS_A_62_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_OFFSET: u32 = 796; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_CLASS_A_63_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_OFFSET: u32 = 800; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_MASK: u32 = 3; |
| pub const ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_CLASS_A_64_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_A_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_ALERT_CAUSE_MULTIREG_COUNT: u32 = 65; |
| pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_OFFSET: u32 = 804; |
| pub const ALERT_HANDLER_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_0_A_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_OFFSET: u32 = 808; |
| pub const ALERT_HANDLER_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_1_A_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_OFFSET: u32 = 812; |
| pub const ALERT_HANDLER_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_2_A_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_OFFSET: u32 = 816; |
| pub const ALERT_HANDLER_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_3_A_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_OFFSET: u32 = 820; |
| pub const ALERT_HANDLER_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_4_A_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_OFFSET: u32 = 824; |
| pub const ALERT_HANDLER_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_5_A_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_OFFSET: u32 = 828; |
| pub const ALERT_HANDLER_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_6_A_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_OFFSET: u32 = 832; |
| pub const ALERT_HANDLER_ALERT_CAUSE_7_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_7_A_7_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_OFFSET: u32 = 836; |
| pub const ALERT_HANDLER_ALERT_CAUSE_8_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_8_A_8_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_OFFSET: u32 = 840; |
| pub const ALERT_HANDLER_ALERT_CAUSE_9_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_9_A_9_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_OFFSET: u32 = 844; |
| pub const ALERT_HANDLER_ALERT_CAUSE_10_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_10_A_10_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_OFFSET: u32 = 848; |
| pub const ALERT_HANDLER_ALERT_CAUSE_11_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_11_A_11_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_OFFSET: u32 = 852; |
| pub const ALERT_HANDLER_ALERT_CAUSE_12_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_12_A_12_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_OFFSET: u32 = 856; |
| pub const ALERT_HANDLER_ALERT_CAUSE_13_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_13_A_13_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_OFFSET: u32 = 860; |
| pub const ALERT_HANDLER_ALERT_CAUSE_14_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_14_A_14_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_OFFSET: u32 = 864; |
| pub const ALERT_HANDLER_ALERT_CAUSE_15_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_15_A_15_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_OFFSET: u32 = 868; |
| pub const ALERT_HANDLER_ALERT_CAUSE_16_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_16_A_16_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_OFFSET: u32 = 872; |
| pub const ALERT_HANDLER_ALERT_CAUSE_17_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_17_A_17_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_OFFSET: u32 = 876; |
| pub const ALERT_HANDLER_ALERT_CAUSE_18_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_18_A_18_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_OFFSET: u32 = 880; |
| pub const ALERT_HANDLER_ALERT_CAUSE_19_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_19_A_19_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_OFFSET: u32 = 884; |
| pub const ALERT_HANDLER_ALERT_CAUSE_20_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_20_A_20_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_OFFSET: u32 = 888; |
| pub const ALERT_HANDLER_ALERT_CAUSE_21_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_21_A_21_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_OFFSET: u32 = 892; |
| pub const ALERT_HANDLER_ALERT_CAUSE_22_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_22_A_22_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_OFFSET: u32 = 896; |
| pub const ALERT_HANDLER_ALERT_CAUSE_23_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_23_A_23_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_OFFSET: u32 = 900; |
| pub const ALERT_HANDLER_ALERT_CAUSE_24_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_24_A_24_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_OFFSET: u32 = 904; |
| pub const ALERT_HANDLER_ALERT_CAUSE_25_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_25_A_25_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_OFFSET: u32 = 908; |
| pub const ALERT_HANDLER_ALERT_CAUSE_26_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_26_A_26_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_OFFSET: u32 = 912; |
| pub const ALERT_HANDLER_ALERT_CAUSE_27_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_27_A_27_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_OFFSET: u32 = 916; |
| pub const ALERT_HANDLER_ALERT_CAUSE_28_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_28_A_28_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_OFFSET: u32 = 920; |
| pub const ALERT_HANDLER_ALERT_CAUSE_29_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_29_A_29_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_OFFSET: u32 = 924; |
| pub const ALERT_HANDLER_ALERT_CAUSE_30_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_30_A_30_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_OFFSET: u32 = 928; |
| pub const ALERT_HANDLER_ALERT_CAUSE_31_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_31_A_31_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_OFFSET: u32 = 932; |
| pub const ALERT_HANDLER_ALERT_CAUSE_32_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_32_A_32_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_OFFSET: u32 = 936; |
| pub const ALERT_HANDLER_ALERT_CAUSE_33_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_33_A_33_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_OFFSET: u32 = 940; |
| pub const ALERT_HANDLER_ALERT_CAUSE_34_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_34_A_34_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_OFFSET: u32 = 944; |
| pub const ALERT_HANDLER_ALERT_CAUSE_35_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_35_A_35_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_OFFSET: u32 = 948; |
| pub const ALERT_HANDLER_ALERT_CAUSE_36_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_36_A_36_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_OFFSET: u32 = 952; |
| pub const ALERT_HANDLER_ALERT_CAUSE_37_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_37_A_37_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_OFFSET: u32 = 956; |
| pub const ALERT_HANDLER_ALERT_CAUSE_38_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_38_A_38_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_OFFSET: u32 = 960; |
| pub const ALERT_HANDLER_ALERT_CAUSE_39_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_39_A_39_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_OFFSET: u32 = 964; |
| pub const ALERT_HANDLER_ALERT_CAUSE_40_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_40_A_40_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_OFFSET: u32 = 968; |
| pub const ALERT_HANDLER_ALERT_CAUSE_41_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_41_A_41_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_OFFSET: u32 = 972; |
| pub const ALERT_HANDLER_ALERT_CAUSE_42_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_42_A_42_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_OFFSET: u32 = 976; |
| pub const ALERT_HANDLER_ALERT_CAUSE_43_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_43_A_43_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_OFFSET: u32 = 980; |
| pub const ALERT_HANDLER_ALERT_CAUSE_44_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_44_A_44_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_OFFSET: u32 = 984; |
| pub const ALERT_HANDLER_ALERT_CAUSE_45_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_45_A_45_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_OFFSET: u32 = 988; |
| pub const ALERT_HANDLER_ALERT_CAUSE_46_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_46_A_46_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_OFFSET: u32 = 992; |
| pub const ALERT_HANDLER_ALERT_CAUSE_47_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_47_A_47_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_OFFSET: u32 = 996; |
| pub const ALERT_HANDLER_ALERT_CAUSE_48_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_48_A_48_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_OFFSET: u32 = 1000; |
| pub const ALERT_HANDLER_ALERT_CAUSE_49_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_49_A_49_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_OFFSET: u32 = 1004; |
| pub const ALERT_HANDLER_ALERT_CAUSE_50_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_50_A_50_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_OFFSET: u32 = 1008; |
| pub const ALERT_HANDLER_ALERT_CAUSE_51_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_51_A_51_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_OFFSET: u32 = 1012; |
| pub const ALERT_HANDLER_ALERT_CAUSE_52_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_52_A_52_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_OFFSET: u32 = 1016; |
| pub const ALERT_HANDLER_ALERT_CAUSE_53_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_53_A_53_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_OFFSET: u32 = 1020; |
| pub const ALERT_HANDLER_ALERT_CAUSE_54_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_54_A_54_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_OFFSET: u32 = 1024; |
| pub const ALERT_HANDLER_ALERT_CAUSE_55_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_55_A_55_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_OFFSET: u32 = 1028; |
| pub const ALERT_HANDLER_ALERT_CAUSE_56_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_56_A_56_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_OFFSET: u32 = 1032; |
| pub const ALERT_HANDLER_ALERT_CAUSE_57_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_57_A_57_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_OFFSET: u32 = 1036; |
| pub const ALERT_HANDLER_ALERT_CAUSE_58_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_58_A_58_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_OFFSET: u32 = 1040; |
| pub const ALERT_HANDLER_ALERT_CAUSE_59_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_59_A_59_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_OFFSET: u32 = 1044; |
| pub const ALERT_HANDLER_ALERT_CAUSE_60_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_60_A_60_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_OFFSET: u32 = 1048; |
| pub const ALERT_HANDLER_ALERT_CAUSE_61_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_61_A_61_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_OFFSET: u32 = 1052; |
| pub const ALERT_HANDLER_ALERT_CAUSE_62_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_62_A_62_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_OFFSET: u32 = 1056; |
| pub const ALERT_HANDLER_ALERT_CAUSE_63_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_63_A_63_BIT: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_OFFSET: u32 = 1060; |
| pub const ALERT_HANDLER_ALERT_CAUSE_64_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_ALERT_CAUSE_64_A_64_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_EN_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_MULTIREG_COUNT: u32 = 7; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_OFFSET: u32 = 1064; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_0_EN_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_OFFSET: u32 = 1068; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_1_EN_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_OFFSET: u32 = 1072; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_2_EN_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_OFFSET: u32 = 1076; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_3_EN_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_OFFSET: u32 = 1080; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_4_EN_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_OFFSET: u32 = 1084; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_5_EN_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_OFFSET: u32 = 1088; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_REGWEN_6_EN_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_EN_LA_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_MULTIREG_COUNT: u32 = 7; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_OFFSET: u32 = 1092; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_EN_LA_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_OFFSET: u32 = 1096; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_EN_LA_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_OFFSET: u32 = 1100; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_EN_LA_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_OFFSET: u32 = 1104; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_EN_LA_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_OFFSET: u32 = 1108; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_EN_LA_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_OFFSET: u32 = 1112; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_EN_LA_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_OFFSET: u32 = 1116; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_EN_LA_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_CLASS_LA_FIELD_WIDTH: u32 = 2; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_MULTIREG_COUNT: u32 = 7; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_OFFSET: u32 = 1120; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSA: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSB: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSC: u32 = 2; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_CLASS_LA_0_VALUE_CLASSD: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_OFFSET: u32 = 1124; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_CLASS_LA_1_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_OFFSET: u32 = 1128; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_CLASS_LA_2_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_OFFSET: u32 = 1132; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_CLASS_LA_3_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_OFFSET: u32 = 1136; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_CLASS_LA_4_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_OFFSET: u32 = 1140; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_CLASS_LA_5_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_OFFSET: u32 = 1144; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_MASK: u32 = 3; |
| pub const ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_CLASS_LA_6_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_LA_FIELD_WIDTH: u32 = 1; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_MULTIREG_COUNT: u32 = 7; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_OFFSET: u32 = 1148; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_0_LA_0_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_OFFSET: u32 = 1152; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_1_LA_1_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_OFFSET: u32 = 1156; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_2_LA_2_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_OFFSET: u32 = 1160; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_3_LA_3_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_OFFSET: u32 = 1164; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_4_LA_4_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_OFFSET: u32 = 1168; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_5_LA_5_BIT: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_OFFSET: u32 = 1172; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_LOC_ALERT_CAUSE_6_LA_6_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_REGWEN_REG_OFFSET: u32 = 1176; |
| pub const ALERT_HANDLER_CLASSA_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSA_REGWEN_CLASSA_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_OFFSET: u32 = 1180; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_LOCK_BIT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E0_BIT: u32 = 2; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E1_BIT: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E2_BIT: u32 = 4; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_EN_E3_BIT: u32 = 5; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; |
| pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_OFFSET: u32 = 1184; |
| pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSA_CLR_REGWEN_CLASSA_CLR_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_OFFSET: u32 = 1188; |
| pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CLR_SHADOWED_CLASSA_CLR_SHADOWED_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_OFFSET: u32 = 1192; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_CNT_CLASSA_ACCUM_CNT_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1196; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1200; |
| pub const ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1204; |
| pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_MASK: |
| u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; |
| pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1208; |
| pub const ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1212; |
| pub const ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1216; |
| pub const ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1220; |
| pub const ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_OFFSET: u32 = 1224; |
| pub const ALERT_HANDLER_CLASSA_ESC_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_STATE_REG_OFFSET: u32 = 1228; |
| pub const ALERT_HANDLER_CLASSA_STATE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_MASK: u32 = 7; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_IDLE: u32 = 0; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TIMEOUT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_FSMERROR: u32 = 2; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_TERMINAL: u32 = 3; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE0: u32 = 4; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE1: u32 = 5; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE2: u32 = 6; |
| pub const ALERT_HANDLER_CLASSA_STATE_CLASSA_STATE_VALUE_PHASE3: u32 = 7; |
| pub const ALERT_HANDLER_CLASSB_REGWEN_REG_OFFSET: u32 = 1232; |
| pub const ALERT_HANDLER_CLASSB_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSB_REGWEN_CLASSB_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_OFFSET: u32 = 1236; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_LOCK_BIT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E0_BIT: u32 = 2; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E1_BIT: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E2_BIT: u32 = 4; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_EN_E3_BIT: u32 = 5; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; |
| pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_OFFSET: u32 = 1240; |
| pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSB_CLR_REGWEN_CLASSB_CLR_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_OFFSET: u32 = 1244; |
| pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CLR_SHADOWED_CLASSB_CLR_SHADOWED_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_OFFSET: u32 = 1248; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_CNT_CLASSB_ACCUM_CNT_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1252; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1256; |
| pub const ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1260; |
| pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_MASK: |
| u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; |
| pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1264; |
| pub const ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1268; |
| pub const ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1272; |
| pub const ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1276; |
| pub const ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_OFFSET: u32 = 1280; |
| pub const ALERT_HANDLER_CLASSB_ESC_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_STATE_REG_OFFSET: u32 = 1284; |
| pub const ALERT_HANDLER_CLASSB_STATE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_MASK: u32 = 7; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_IDLE: u32 = 0; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TIMEOUT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_FSMERROR: u32 = 2; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_TERMINAL: u32 = 3; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE0: u32 = 4; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE1: u32 = 5; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE2: u32 = 6; |
| pub const ALERT_HANDLER_CLASSB_STATE_CLASSB_STATE_VALUE_PHASE3: u32 = 7; |
| pub const ALERT_HANDLER_CLASSC_REGWEN_REG_OFFSET: u32 = 1288; |
| pub const ALERT_HANDLER_CLASSC_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSC_REGWEN_CLASSC_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_OFFSET: u32 = 1292; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_LOCK_BIT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E0_BIT: u32 = 2; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E1_BIT: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E2_BIT: u32 = 4; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_EN_E3_BIT: u32 = 5; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; |
| pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_OFFSET: u32 = 1296; |
| pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSC_CLR_REGWEN_CLASSC_CLR_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_OFFSET: u32 = 1300; |
| pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CLR_SHADOWED_CLASSC_CLR_SHADOWED_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_OFFSET: u32 = 1304; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_CNT_CLASSC_ACCUM_CNT_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1308; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1312; |
| pub const ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1316; |
| pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_MASK: |
| u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; |
| pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1320; |
| pub const ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1324; |
| pub const ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1328; |
| pub const ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1332; |
| pub const ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_OFFSET: u32 = 1336; |
| pub const ALERT_HANDLER_CLASSC_ESC_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_STATE_REG_OFFSET: u32 = 1340; |
| pub const ALERT_HANDLER_CLASSC_STATE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_MASK: u32 = 7; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_IDLE: u32 = 0; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TIMEOUT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_FSMERROR: u32 = 2; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_TERMINAL: u32 = 3; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE0: u32 = 4; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE1: u32 = 5; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE2: u32 = 6; |
| pub const ALERT_HANDLER_CLASSC_STATE_CLASSC_STATE_VALUE_PHASE3: u32 = 7; |
| pub const ALERT_HANDLER_CLASSD_REGWEN_REG_OFFSET: u32 = 1344; |
| pub const ALERT_HANDLER_CLASSD_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSD_REGWEN_CLASSD_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_OFFSET: u32 = 1348; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_REG_RESVAL: u32 = 14652; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_LOCK_BIT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E0_BIT: u32 = 2; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E1_BIT: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E2_BIT: u32 = 4; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_EN_E3_BIT: u32 = 5; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E0_OFFSET: u32 = 6; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E1_OFFSET: u32 = 8; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E2_OFFSET: u32 = 10; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_MASK: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CTRL_SHADOWED_MAP_E3_OFFSET: u32 = 12; |
| pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_OFFSET: u32 = 1352; |
| pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_REG_RESVAL: u32 = 1; |
| pub const ALERT_HANDLER_CLASSD_CLR_REGWEN_CLASSD_CLR_REGWEN_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_OFFSET: u32 = 1356; |
| pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CLR_SHADOWED_CLASSD_CLR_SHADOWED_BIT: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_OFFSET: u32 = 1360; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_CNT_CLASSD_ACCUM_CNT_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_OFFSET: u32 = 1364; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_MASK: u32 = 65535; |
| pub const ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_OFFSET: u32 = 1368; |
| pub const ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_OFFSET: u32 = 1372; |
| pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_MASK: |
| u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET : u32 = 0 ; |
| pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_OFFSET: u32 = 1376; |
| pub const ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_OFFSET: u32 = 1380; |
| pub const ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_OFFSET: u32 = 1384; |
| pub const ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_OFFSET: u32 = 1388; |
| pub const ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_OFFSET: u32 = 1392; |
| pub const ALERT_HANDLER_CLASSD_ESC_CNT_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_STATE_REG_OFFSET: u32 = 1396; |
| pub const ALERT_HANDLER_CLASSD_STATE_REG_RESVAL: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_MASK: u32 = 7; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_OFFSET: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_IDLE: u32 = 0; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TIMEOUT: u32 = 1; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_FSMERROR: u32 = 2; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_TERMINAL: u32 = 3; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE0: u32 = 4; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE1: u32 = 5; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE2: u32 = 6; |
| pub const ALERT_HANDLER_CLASSD_STATE_CLASSD_STATE_VALUE_PHASE3: u32 = 7; |
