hw/ip/rv_timer/dv/rv_timer_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: rv_timer

  // Top level dut name (sv module).
  dut: rv_timer

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:rv_timer_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/rv_timer/data/rv_timer_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/rv_timer/data/rv_timer.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["rv_timer_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Default UVM test and seq class name.
  uvm_test: rv_timer_base_test
  uvm_test_seq: rv_timer_base_vseq

  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: rv_timer_random
      uvm_test_seq: rv_timer_random_vseq
      reseed: 200
    }

    {
      name: rv_timer_disabled
      uvm_test_seq: rv_timer_disabled_vseq
    }

    {
      name: rv_timer_cfg_update_on_fly
      uvm_test_seq: rv_timer_cfg_update_on_fly_vseq
      // 10ms
      run_opts: ["+zero_delays=1", "+test_timeout_ns=10000000000"]
    }

    {
      name: rv_timer_random_reset
      uvm_test_seq: rv_timer_random_reset_vseq
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["rv_timer_random"]
    }
  ]
}