| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| // Register Top module auto-generated by `reggen` |
| |
| `include "prim_assert.sv" |
| |
| module rv_dm_mem_reg_top ( |
| input clk_i, |
| input rst_ni, |
| input tlul_pkg::tl_h2d_t tl_i, |
| output tlul_pkg::tl_d2h_t tl_o, |
| |
| // Output port for window |
| output tlul_pkg::tl_h2d_t tl_win_o, |
| input tlul_pkg::tl_d2h_t tl_win_i, |
| |
| // To HW |
| output rv_dm_reg_pkg::rv_dm_mem_reg2hw_t reg2hw, // Write |
| input rv_dm_reg_pkg::rv_dm_mem_hw2reg_t hw2reg, // Read |
| |
| // Integrity check errors |
| output logic intg_err_o, |
| |
| // Config |
| input devmode_i // If 1, explicit error return for unmapped register access |
| ); |
| |
| import rv_dm_reg_pkg::* ; |
| |
| localparam int AW = 12; |
| localparam int DW = 32; |
| localparam int DBW = DW/8; // Byte Width |
| |
| // register signals |
| logic reg_we; |
| logic reg_re; |
| logic [AW-1:0] reg_addr; |
| logic [DW-1:0] reg_wdata; |
| logic [DBW-1:0] reg_be; |
| logic [DW-1:0] reg_rdata; |
| logic reg_error; |
| |
| logic addrmiss, wr_err; |
| |
| logic [DW-1:0] reg_rdata_next; |
| logic reg_busy; |
| |
| tlul_pkg::tl_h2d_t tl_reg_h2d; |
| tlul_pkg::tl_d2h_t tl_reg_d2h; |
| |
| |
| // incoming payload check |
| logic intg_err; |
| tlul_cmd_intg_chk u_chk ( |
| .tl_i(tl_i), |
| .err_o(intg_err) |
| ); |
| |
| // also check for spurious write enables |
| logic reg_we_err; |
| logic [280:0] reg_we_check; |
| prim_reg_we_check #( |
| .OneHotWidth(281) |
| ) u_prim_reg_we_check ( |
| .clk_i(clk_i), |
| .rst_ni(rst_ni), |
| .oh_i (reg_we_check), |
| .en_i (reg_we && !addrmiss), |
| .err_o (reg_we_err) |
| ); |
| |
| logic err_q; |
| always_ff @(posedge clk_i or negedge rst_ni) begin |
| if (!rst_ni) begin |
| err_q <= '0; |
| end else if (intg_err || reg_we_err) begin |
| err_q <= 1'b1; |
| end |
| end |
| |
| // integrity error output is permanent and should be used for alert generation |
| // register errors are transactional |
| assign intg_err_o = err_q | intg_err | reg_we_err; |
| |
| // outgoing integrity generation |
| tlul_pkg::tl_d2h_t tl_o_pre; |
| tlul_rsp_intg_gen #( |
| .EnableRspIntgGen(1), |
| .EnableDataIntgGen(1) |
| ) u_rsp_intg_gen ( |
| .tl_i(tl_o_pre), |
| .tl_o(tl_o) |
| ); |
| |
| tlul_pkg::tl_h2d_t tl_socket_h2d [2]; |
| tlul_pkg::tl_d2h_t tl_socket_d2h [2]; |
| |
| logic [0:0] reg_steer; |
| |
| // socket_1n connection |
| assign tl_reg_h2d = tl_socket_h2d[1]; |
| assign tl_socket_d2h[1] = tl_reg_d2h; |
| |
| assign tl_win_o = tl_socket_h2d[0]; |
| assign tl_socket_d2h[0] = tl_win_i; |
| |
| // Create Socket_1n |
| tlul_socket_1n #( |
| .N (2), |
| .HReqPass (1'b1), |
| .HRspPass (1'b1), |
| .DReqPass ({2{1'b1}}), |
| .DRspPass ({2{1'b1}}), |
| .HReqDepth (4'h0), |
| .HRspDepth (4'h0), |
| .DReqDepth ({2{4'h0}}), |
| .DRspDepth ({2{4'h0}}), |
| .ExplicitErrs (1'b0) |
| ) u_socket ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| .tl_h_i (tl_i), |
| .tl_h_o (tl_o_pre), |
| .tl_d_o (tl_socket_h2d), |
| .tl_d_i (tl_socket_d2h), |
| .dev_select_i (reg_steer) |
| ); |
| |
| // Create steering logic |
| always_comb begin |
| reg_steer = |
| tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 : |
| // Default set to register |
| 1'd1; |
| |
| // Override this in case of an integrity error |
| if (intg_err) begin |
| reg_steer = 1'd1; |
| end |
| end |
| |
| tlul_adapter_reg #( |
| .RegAw(AW), |
| .RegDw(DW), |
| .EnableDataIntgGen(0) |
| ) u_reg_if ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| .tl_i (tl_reg_h2d), |
| .tl_o (tl_reg_d2h), |
| |
| .en_ifetch_i(prim_mubi_pkg::MuBi4False), |
| .intg_error_o(), |
| |
| .we_o (reg_we), |
| .re_o (reg_re), |
| .addr_o (reg_addr), |
| .wdata_o (reg_wdata), |
| .be_o (reg_be), |
| .busy_i (reg_busy), |
| .rdata_i (reg_rdata), |
| .error_i (reg_error) |
| ); |
| |
| // cdc oversampling signals |
| |
| assign reg_rdata = reg_rdata_next ; |
| assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err; |
| |
| // Define SW related signals |
| // Format: <reg>_<field>_{wd|we|qs} |
| // or <reg>_{wd|we|qs} if field == 1 or 0 |
| logic halted_we; |
| logic halted_wd; |
| logic going_we; |
| logic going_wd; |
| logic resuming_we; |
| logic resuming_wd; |
| logic exception_we; |
| logic exception_wd; |
| logic [31:0] whereto_qs; |
| logic [31:0] abstractcmd_0_qs; |
| logic [31:0] abstractcmd_1_qs; |
| logic [31:0] abstractcmd_2_qs; |
| logic [31:0] abstractcmd_3_qs; |
| logic [31:0] abstractcmd_4_qs; |
| logic [31:0] abstractcmd_5_qs; |
| logic [31:0] abstractcmd_6_qs; |
| logic [31:0] abstractcmd_7_qs; |
| logic [31:0] abstractcmd_8_qs; |
| logic [31:0] abstractcmd_9_qs; |
| logic [31:0] program_buffer_0_qs; |
| logic [31:0] program_buffer_1_qs; |
| logic [31:0] program_buffer_2_qs; |
| logic [31:0] program_buffer_3_qs; |
| logic [31:0] program_buffer_4_qs; |
| logic [31:0] program_buffer_5_qs; |
| logic [31:0] program_buffer_6_qs; |
| logic [31:0] program_buffer_7_qs; |
| logic dataaddr_0_we; |
| logic [31:0] dataaddr_0_qs; |
| logic [31:0] dataaddr_0_wd; |
| logic dataaddr_1_we; |
| logic [31:0] dataaddr_1_qs; |
| logic [31:0] dataaddr_1_wd; |
| logic [31:0] flags_0_qs; |
| logic [31:0] flags_1_qs; |
| logic [31:0] flags_2_qs; |
| logic [31:0] flags_3_qs; |
| logic [31:0] flags_4_qs; |
| logic [31:0] flags_5_qs; |
| logic [31:0] flags_6_qs; |
| logic [31:0] flags_7_qs; |
| logic [31:0] flags_8_qs; |
| logic [31:0] flags_9_qs; |
| logic [31:0] flags_10_qs; |
| logic [31:0] flags_11_qs; |
| logic [31:0] flags_12_qs; |
| logic [31:0] flags_13_qs; |
| logic [31:0] flags_14_qs; |
| logic [31:0] flags_15_qs; |
| logic [31:0] flags_16_qs; |
| logic [31:0] flags_17_qs; |
| logic [31:0] flags_18_qs; |
| logic [31:0] flags_19_qs; |
| logic [31:0] flags_20_qs; |
| logic [31:0] flags_21_qs; |
| logic [31:0] flags_22_qs; |
| logic [31:0] flags_23_qs; |
| logic [31:0] flags_24_qs; |
| logic [31:0] flags_25_qs; |
| logic [31:0] flags_26_qs; |
| logic [31:0] flags_27_qs; |
| logic [31:0] flags_28_qs; |
| logic [31:0] flags_29_qs; |
| logic [31:0] flags_30_qs; |
| logic [31:0] flags_31_qs; |
| logic [31:0] flags_32_qs; |
| logic [31:0] flags_33_qs; |
| logic [31:0] flags_34_qs; |
| logic [31:0] flags_35_qs; |
| logic [31:0] flags_36_qs; |
| logic [31:0] flags_37_qs; |
| logic [31:0] flags_38_qs; |
| logic [31:0] flags_39_qs; |
| logic [31:0] flags_40_qs; |
| logic [31:0] flags_41_qs; |
| logic [31:0] flags_42_qs; |
| logic [31:0] flags_43_qs; |
| logic [31:0] flags_44_qs; |
| logic [31:0] flags_45_qs; |
| logic [31:0] flags_46_qs; |
| logic [31:0] flags_47_qs; |
| logic [31:0] flags_48_qs; |
| logic [31:0] flags_49_qs; |
| logic [31:0] flags_50_qs; |
| logic [31:0] flags_51_qs; |
| logic [31:0] flags_52_qs; |
| logic [31:0] flags_53_qs; |
| logic [31:0] flags_54_qs; |
| logic [31:0] flags_55_qs; |
| logic [31:0] flags_56_qs; |
| logic [31:0] flags_57_qs; |
| logic [31:0] flags_58_qs; |
| logic [31:0] flags_59_qs; |
| logic [31:0] flags_60_qs; |
| logic [31:0] flags_61_qs; |
| logic [31:0] flags_62_qs; |
| logic [31:0] flags_63_qs; |
| logic [31:0] flags_64_qs; |
| logic [31:0] flags_65_qs; |
| logic [31:0] flags_66_qs; |
| logic [31:0] flags_67_qs; |
| logic [31:0] flags_68_qs; |
| logic [31:0] flags_69_qs; |
| logic [31:0] flags_70_qs; |
| logic [31:0] flags_71_qs; |
| logic [31:0] flags_72_qs; |
| logic [31:0] flags_73_qs; |
| logic [31:0] flags_74_qs; |
| logic [31:0] flags_75_qs; |
| logic [31:0] flags_76_qs; |
| logic [31:0] flags_77_qs; |
| logic [31:0] flags_78_qs; |
| logic [31:0] flags_79_qs; |
| logic [31:0] flags_80_qs; |
| logic [31:0] flags_81_qs; |
| logic [31:0] flags_82_qs; |
| logic [31:0] flags_83_qs; |
| logic [31:0] flags_84_qs; |
| logic [31:0] flags_85_qs; |
| logic [31:0] flags_86_qs; |
| logic [31:0] flags_87_qs; |
| logic [31:0] flags_88_qs; |
| logic [31:0] flags_89_qs; |
| logic [31:0] flags_90_qs; |
| logic [31:0] flags_91_qs; |
| logic [31:0] flags_92_qs; |
| logic [31:0] flags_93_qs; |
| logic [31:0] flags_94_qs; |
| logic [31:0] flags_95_qs; |
| logic [31:0] flags_96_qs; |
| logic [31:0] flags_97_qs; |
| logic [31:0] flags_98_qs; |
| logic [31:0] flags_99_qs; |
| logic [31:0] flags_100_qs; |
| logic [31:0] flags_101_qs; |
| logic [31:0] flags_102_qs; |
| logic [31:0] flags_103_qs; |
| logic [31:0] flags_104_qs; |
| logic [31:0] flags_105_qs; |
| logic [31:0] flags_106_qs; |
| logic [31:0] flags_107_qs; |
| logic [31:0] flags_108_qs; |
| logic [31:0] flags_109_qs; |
| logic [31:0] flags_110_qs; |
| logic [31:0] flags_111_qs; |
| logic [31:0] flags_112_qs; |
| logic [31:0] flags_113_qs; |
| logic [31:0] flags_114_qs; |
| logic [31:0] flags_115_qs; |
| logic [31:0] flags_116_qs; |
| logic [31:0] flags_117_qs; |
| logic [31:0] flags_118_qs; |
| logic [31:0] flags_119_qs; |
| logic [31:0] flags_120_qs; |
| logic [31:0] flags_121_qs; |
| logic [31:0] flags_122_qs; |
| logic [31:0] flags_123_qs; |
| logic [31:0] flags_124_qs; |
| logic [31:0] flags_125_qs; |
| logic [31:0] flags_126_qs; |
| logic [31:0] flags_127_qs; |
| logic [31:0] flags_128_qs; |
| logic [31:0] flags_129_qs; |
| logic [31:0] flags_130_qs; |
| logic [31:0] flags_131_qs; |
| logic [31:0] flags_132_qs; |
| logic [31:0] flags_133_qs; |
| logic [31:0] flags_134_qs; |
| logic [31:0] flags_135_qs; |
| logic [31:0] flags_136_qs; |
| logic [31:0] flags_137_qs; |
| logic [31:0] flags_138_qs; |
| logic [31:0] flags_139_qs; |
| logic [31:0] flags_140_qs; |
| logic [31:0] flags_141_qs; |
| logic [31:0] flags_142_qs; |
| logic [31:0] flags_143_qs; |
| logic [31:0] flags_144_qs; |
| logic [31:0] flags_145_qs; |
| logic [31:0] flags_146_qs; |
| logic [31:0] flags_147_qs; |
| logic [31:0] flags_148_qs; |
| logic [31:0] flags_149_qs; |
| logic [31:0] flags_150_qs; |
| logic [31:0] flags_151_qs; |
| logic [31:0] flags_152_qs; |
| logic [31:0] flags_153_qs; |
| logic [31:0] flags_154_qs; |
| logic [31:0] flags_155_qs; |
| logic [31:0] flags_156_qs; |
| logic [31:0] flags_157_qs; |
| logic [31:0] flags_158_qs; |
| logic [31:0] flags_159_qs; |
| logic [31:0] flags_160_qs; |
| logic [31:0] flags_161_qs; |
| logic [31:0] flags_162_qs; |
| logic [31:0] flags_163_qs; |
| logic [31:0] flags_164_qs; |
| logic [31:0] flags_165_qs; |
| logic [31:0] flags_166_qs; |
| logic [31:0] flags_167_qs; |
| logic [31:0] flags_168_qs; |
| logic [31:0] flags_169_qs; |
| logic [31:0] flags_170_qs; |
| logic [31:0] flags_171_qs; |
| logic [31:0] flags_172_qs; |
| logic [31:0] flags_173_qs; |
| logic [31:0] flags_174_qs; |
| logic [31:0] flags_175_qs; |
| logic [31:0] flags_176_qs; |
| logic [31:0] flags_177_qs; |
| logic [31:0] flags_178_qs; |
| logic [31:0] flags_179_qs; |
| logic [31:0] flags_180_qs; |
| logic [31:0] flags_181_qs; |
| logic [31:0] flags_182_qs; |
| logic [31:0] flags_183_qs; |
| logic [31:0] flags_184_qs; |
| logic [31:0] flags_185_qs; |
| logic [31:0] flags_186_qs; |
| logic [31:0] flags_187_qs; |
| logic [31:0] flags_188_qs; |
| logic [31:0] flags_189_qs; |
| logic [31:0] flags_190_qs; |
| logic [31:0] flags_191_qs; |
| logic [31:0] flags_192_qs; |
| logic [31:0] flags_193_qs; |
| logic [31:0] flags_194_qs; |
| logic [31:0] flags_195_qs; |
| logic [31:0] flags_196_qs; |
| logic [31:0] flags_197_qs; |
| logic [31:0] flags_198_qs; |
| logic [31:0] flags_199_qs; |
| logic [31:0] flags_200_qs; |
| logic [31:0] flags_201_qs; |
| logic [31:0] flags_202_qs; |
| logic [31:0] flags_203_qs; |
| logic [31:0] flags_204_qs; |
| logic [31:0] flags_205_qs; |
| logic [31:0] flags_206_qs; |
| logic [31:0] flags_207_qs; |
| logic [31:0] flags_208_qs; |
| logic [31:0] flags_209_qs; |
| logic [31:0] flags_210_qs; |
| logic [31:0] flags_211_qs; |
| logic [31:0] flags_212_qs; |
| logic [31:0] flags_213_qs; |
| logic [31:0] flags_214_qs; |
| logic [31:0] flags_215_qs; |
| logic [31:0] flags_216_qs; |
| logic [31:0] flags_217_qs; |
| logic [31:0] flags_218_qs; |
| logic [31:0] flags_219_qs; |
| logic [31:0] flags_220_qs; |
| logic [31:0] flags_221_qs; |
| logic [31:0] flags_222_qs; |
| logic [31:0] flags_223_qs; |
| logic [31:0] flags_224_qs; |
| logic [31:0] flags_225_qs; |
| logic [31:0] flags_226_qs; |
| logic [31:0] flags_227_qs; |
| logic [31:0] flags_228_qs; |
| logic [31:0] flags_229_qs; |
| logic [31:0] flags_230_qs; |
| logic [31:0] flags_231_qs; |
| logic [31:0] flags_232_qs; |
| logic [31:0] flags_233_qs; |
| logic [31:0] flags_234_qs; |
| logic [31:0] flags_235_qs; |
| logic [31:0] flags_236_qs; |
| logic [31:0] flags_237_qs; |
| logic [31:0] flags_238_qs; |
| logic [31:0] flags_239_qs; |
| logic [31:0] flags_240_qs; |
| logic [31:0] flags_241_qs; |
| logic [31:0] flags_242_qs; |
| logic [31:0] flags_243_qs; |
| logic [31:0] flags_244_qs; |
| logic [31:0] flags_245_qs; |
| logic [31:0] flags_246_qs; |
| logic [31:0] flags_247_qs; |
| logic [31:0] flags_248_qs; |
| logic [31:0] flags_249_qs; |
| logic [31:0] flags_250_qs; |
| logic [31:0] flags_251_qs; |
| logic [31:0] flags_252_qs; |
| logic [31:0] flags_253_qs; |
| logic [31:0] flags_254_qs; |
| logic [31:0] flags_255_qs; |
| |
| // Register instances |
| // R[halted]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_halted ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (halted_we), |
| .wd (halted_wd), |
| |
| // from internal hardware |
| .de (hw2reg.halted.de), |
| .d (hw2reg.halted.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.halted.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| |
| |
| // R[going]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_going ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (going_we), |
| .wd (going_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.going.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| |
| |
| // R[resuming]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_resuming ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (resuming_we), |
| .wd (resuming_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.resuming.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| |
| |
| // R[exception]: V(False) |
| prim_subreg #( |
| .DW (1), |
| .SwAccess(prim_subreg_pkg::SwAccessWO), |
| .RESVAL (1'h0) |
| ) u_exception ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (exception_we), |
| .wd (exception_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.exception.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs () |
| ); |
| |
| |
| // R[whereto]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_whereto ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (hw2reg.whereto.de), |
| .d (hw2reg.whereto.d), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.whereto.q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (whereto_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg abstractcmd |
| // R[abstractcmd_0]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg abstractcmd |
| // R[abstractcmd_1]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg abstractcmd |
| // R[abstractcmd_2]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg abstractcmd |
| // R[abstractcmd_3]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg abstractcmd |
| // R[abstractcmd_4]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg abstractcmd |
| // R[abstractcmd_5]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg abstractcmd |
| // R[abstractcmd_6]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg abstractcmd |
| // R[abstractcmd_7]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg abstractcmd |
| // R[abstractcmd_8]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg abstractcmd |
| // R[abstractcmd_9]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_abstractcmd_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.abstractcmd[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (abstractcmd_9_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg program_buffer |
| // R[program_buffer_0]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg program_buffer |
| // R[program_buffer_1]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg program_buffer |
| // R[program_buffer_2]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg program_buffer |
| // R[program_buffer_3]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg program_buffer |
| // R[program_buffer_4]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg program_buffer |
| // R[program_buffer_5]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg program_buffer |
| // R[program_buffer_6]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg program_buffer |
| // R[program_buffer_7]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_program_buffer_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.program_buffer[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (program_buffer_7_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg dataaddr |
| // R[dataaddr_0]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (32'h0) |
| ) u_dataaddr_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dataaddr_0_we), |
| .wd (dataaddr_0_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dataaddr[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dataaddr_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg dataaddr |
| // R[dataaddr_1]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRW), |
| .RESVAL (32'h0) |
| ) u_dataaddr_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (dataaddr_1_we), |
| .wd (dataaddr_1_wd), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.dataaddr[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (dataaddr_1_qs) |
| ); |
| |
| |
| // Subregister 0 of Multireg flags |
| // R[flags_0]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_0 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[0].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_0_qs) |
| ); |
| |
| |
| // Subregister 1 of Multireg flags |
| // R[flags_1]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_1 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[1].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_1_qs) |
| ); |
| |
| |
| // Subregister 2 of Multireg flags |
| // R[flags_2]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_2 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[2].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_2_qs) |
| ); |
| |
| |
| // Subregister 3 of Multireg flags |
| // R[flags_3]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_3 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[3].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_3_qs) |
| ); |
| |
| |
| // Subregister 4 of Multireg flags |
| // R[flags_4]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_4 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[4].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_4_qs) |
| ); |
| |
| |
| // Subregister 5 of Multireg flags |
| // R[flags_5]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_5 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[5].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_5_qs) |
| ); |
| |
| |
| // Subregister 6 of Multireg flags |
| // R[flags_6]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_6 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[6].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_6_qs) |
| ); |
| |
| |
| // Subregister 7 of Multireg flags |
| // R[flags_7]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_7 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[7].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_7_qs) |
| ); |
| |
| |
| // Subregister 8 of Multireg flags |
| // R[flags_8]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_8 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[8].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_8_qs) |
| ); |
| |
| |
| // Subregister 9 of Multireg flags |
| // R[flags_9]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_9 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[9].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_9_qs) |
| ); |
| |
| |
| // Subregister 10 of Multireg flags |
| // R[flags_10]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_10 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[10].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_10_qs) |
| ); |
| |
| |
| // Subregister 11 of Multireg flags |
| // R[flags_11]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_11 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[11].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_11_qs) |
| ); |
| |
| |
| // Subregister 12 of Multireg flags |
| // R[flags_12]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_12 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[12].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_12_qs) |
| ); |
| |
| |
| // Subregister 13 of Multireg flags |
| // R[flags_13]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_13 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[13].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_13_qs) |
| ); |
| |
| |
| // Subregister 14 of Multireg flags |
| // R[flags_14]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_14 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[14].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_14_qs) |
| ); |
| |
| |
| // Subregister 15 of Multireg flags |
| // R[flags_15]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_15 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[15].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_15_qs) |
| ); |
| |
| |
| // Subregister 16 of Multireg flags |
| // R[flags_16]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_16 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[16].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_16_qs) |
| ); |
| |
| |
| // Subregister 17 of Multireg flags |
| // R[flags_17]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_17 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[17].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_17_qs) |
| ); |
| |
| |
| // Subregister 18 of Multireg flags |
| // R[flags_18]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_18 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[18].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_18_qs) |
| ); |
| |
| |
| // Subregister 19 of Multireg flags |
| // R[flags_19]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_19 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[19].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_19_qs) |
| ); |
| |
| |
| // Subregister 20 of Multireg flags |
| // R[flags_20]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_20 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[20].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_20_qs) |
| ); |
| |
| |
| // Subregister 21 of Multireg flags |
| // R[flags_21]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_21 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[21].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_21_qs) |
| ); |
| |
| |
| // Subregister 22 of Multireg flags |
| // R[flags_22]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_22 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[22].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_22_qs) |
| ); |
| |
| |
| // Subregister 23 of Multireg flags |
| // R[flags_23]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_23 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[23].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_23_qs) |
| ); |
| |
| |
| // Subregister 24 of Multireg flags |
| // R[flags_24]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_24 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[24].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_24_qs) |
| ); |
| |
| |
| // Subregister 25 of Multireg flags |
| // R[flags_25]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_25 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[25].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_25_qs) |
| ); |
| |
| |
| // Subregister 26 of Multireg flags |
| // R[flags_26]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_26 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[26].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_26_qs) |
| ); |
| |
| |
| // Subregister 27 of Multireg flags |
| // R[flags_27]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_27 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[27].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_27_qs) |
| ); |
| |
| |
| // Subregister 28 of Multireg flags |
| // R[flags_28]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_28 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[28].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_28_qs) |
| ); |
| |
| |
| // Subregister 29 of Multireg flags |
| // R[flags_29]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_29 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[29].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_29_qs) |
| ); |
| |
| |
| // Subregister 30 of Multireg flags |
| // R[flags_30]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_30 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[30].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_30_qs) |
| ); |
| |
| |
| // Subregister 31 of Multireg flags |
| // R[flags_31]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_31 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[31].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_31_qs) |
| ); |
| |
| |
| // Subregister 32 of Multireg flags |
| // R[flags_32]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_32 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[32].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_32_qs) |
| ); |
| |
| |
| // Subregister 33 of Multireg flags |
| // R[flags_33]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_33 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[33].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_33_qs) |
| ); |
| |
| |
| // Subregister 34 of Multireg flags |
| // R[flags_34]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_34 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[34].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_34_qs) |
| ); |
| |
| |
| // Subregister 35 of Multireg flags |
| // R[flags_35]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_35 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[35].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_35_qs) |
| ); |
| |
| |
| // Subregister 36 of Multireg flags |
| // R[flags_36]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_36 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[36].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_36_qs) |
| ); |
| |
| |
| // Subregister 37 of Multireg flags |
| // R[flags_37]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_37 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[37].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_37_qs) |
| ); |
| |
| |
| // Subregister 38 of Multireg flags |
| // R[flags_38]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_38 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[38].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_38_qs) |
| ); |
| |
| |
| // Subregister 39 of Multireg flags |
| // R[flags_39]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_39 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[39].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_39_qs) |
| ); |
| |
| |
| // Subregister 40 of Multireg flags |
| // R[flags_40]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_40 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[40].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_40_qs) |
| ); |
| |
| |
| // Subregister 41 of Multireg flags |
| // R[flags_41]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_41 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[41].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_41_qs) |
| ); |
| |
| |
| // Subregister 42 of Multireg flags |
| // R[flags_42]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_42 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[42].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_42_qs) |
| ); |
| |
| |
| // Subregister 43 of Multireg flags |
| // R[flags_43]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_43 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[43].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_43_qs) |
| ); |
| |
| |
| // Subregister 44 of Multireg flags |
| // R[flags_44]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_44 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[44].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_44_qs) |
| ); |
| |
| |
| // Subregister 45 of Multireg flags |
| // R[flags_45]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_45 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[45].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_45_qs) |
| ); |
| |
| |
| // Subregister 46 of Multireg flags |
| // R[flags_46]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_46 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[46].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_46_qs) |
| ); |
| |
| |
| // Subregister 47 of Multireg flags |
| // R[flags_47]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_47 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[47].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_47_qs) |
| ); |
| |
| |
| // Subregister 48 of Multireg flags |
| // R[flags_48]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_48 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[48].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_48_qs) |
| ); |
| |
| |
| // Subregister 49 of Multireg flags |
| // R[flags_49]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_49 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[49].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_49_qs) |
| ); |
| |
| |
| // Subregister 50 of Multireg flags |
| // R[flags_50]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_50 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[50].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_50_qs) |
| ); |
| |
| |
| // Subregister 51 of Multireg flags |
| // R[flags_51]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_51 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[51].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_51_qs) |
| ); |
| |
| |
| // Subregister 52 of Multireg flags |
| // R[flags_52]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_52 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[52].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_52_qs) |
| ); |
| |
| |
| // Subregister 53 of Multireg flags |
| // R[flags_53]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_53 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[53].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_53_qs) |
| ); |
| |
| |
| // Subregister 54 of Multireg flags |
| // R[flags_54]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_54 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[54].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_54_qs) |
| ); |
| |
| |
| // Subregister 55 of Multireg flags |
| // R[flags_55]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_55 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[55].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_55_qs) |
| ); |
| |
| |
| // Subregister 56 of Multireg flags |
| // R[flags_56]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_56 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[56].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_56_qs) |
| ); |
| |
| |
| // Subregister 57 of Multireg flags |
| // R[flags_57]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_57 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[57].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_57_qs) |
| ); |
| |
| |
| // Subregister 58 of Multireg flags |
| // R[flags_58]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_58 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[58].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_58_qs) |
| ); |
| |
| |
| // Subregister 59 of Multireg flags |
| // R[flags_59]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_59 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[59].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_59_qs) |
| ); |
| |
| |
| // Subregister 60 of Multireg flags |
| // R[flags_60]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_60 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[60].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_60_qs) |
| ); |
| |
| |
| // Subregister 61 of Multireg flags |
| // R[flags_61]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_61 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[61].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_61_qs) |
| ); |
| |
| |
| // Subregister 62 of Multireg flags |
| // R[flags_62]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_62 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[62].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_62_qs) |
| ); |
| |
| |
| // Subregister 63 of Multireg flags |
| // R[flags_63]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_63 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[63].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_63_qs) |
| ); |
| |
| |
| // Subregister 64 of Multireg flags |
| // R[flags_64]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_64 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[64].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_64_qs) |
| ); |
| |
| |
| // Subregister 65 of Multireg flags |
| // R[flags_65]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_65 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[65].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_65_qs) |
| ); |
| |
| |
| // Subregister 66 of Multireg flags |
| // R[flags_66]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_66 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[66].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_66_qs) |
| ); |
| |
| |
| // Subregister 67 of Multireg flags |
| // R[flags_67]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_67 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[67].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_67_qs) |
| ); |
| |
| |
| // Subregister 68 of Multireg flags |
| // R[flags_68]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_68 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[68].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_68_qs) |
| ); |
| |
| |
| // Subregister 69 of Multireg flags |
| // R[flags_69]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_69 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[69].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_69_qs) |
| ); |
| |
| |
| // Subregister 70 of Multireg flags |
| // R[flags_70]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_70 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[70].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_70_qs) |
| ); |
| |
| |
| // Subregister 71 of Multireg flags |
| // R[flags_71]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_71 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[71].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_71_qs) |
| ); |
| |
| |
| // Subregister 72 of Multireg flags |
| // R[flags_72]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_72 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[72].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_72_qs) |
| ); |
| |
| |
| // Subregister 73 of Multireg flags |
| // R[flags_73]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_73 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[73].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_73_qs) |
| ); |
| |
| |
| // Subregister 74 of Multireg flags |
| // R[flags_74]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_74 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[74].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_74_qs) |
| ); |
| |
| |
| // Subregister 75 of Multireg flags |
| // R[flags_75]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_75 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[75].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_75_qs) |
| ); |
| |
| |
| // Subregister 76 of Multireg flags |
| // R[flags_76]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_76 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[76].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_76_qs) |
| ); |
| |
| |
| // Subregister 77 of Multireg flags |
| // R[flags_77]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_77 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[77].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_77_qs) |
| ); |
| |
| |
| // Subregister 78 of Multireg flags |
| // R[flags_78]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_78 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[78].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_78_qs) |
| ); |
| |
| |
| // Subregister 79 of Multireg flags |
| // R[flags_79]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_79 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[79].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_79_qs) |
| ); |
| |
| |
| // Subregister 80 of Multireg flags |
| // R[flags_80]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_80 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[80].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_80_qs) |
| ); |
| |
| |
| // Subregister 81 of Multireg flags |
| // R[flags_81]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_81 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[81].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_81_qs) |
| ); |
| |
| |
| // Subregister 82 of Multireg flags |
| // R[flags_82]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_82 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[82].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_82_qs) |
| ); |
| |
| |
| // Subregister 83 of Multireg flags |
| // R[flags_83]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_83 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[83].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_83_qs) |
| ); |
| |
| |
| // Subregister 84 of Multireg flags |
| // R[flags_84]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_84 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[84].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_84_qs) |
| ); |
| |
| |
| // Subregister 85 of Multireg flags |
| // R[flags_85]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_85 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[85].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_85_qs) |
| ); |
| |
| |
| // Subregister 86 of Multireg flags |
| // R[flags_86]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_86 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[86].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_86_qs) |
| ); |
| |
| |
| // Subregister 87 of Multireg flags |
| // R[flags_87]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_87 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[87].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_87_qs) |
| ); |
| |
| |
| // Subregister 88 of Multireg flags |
| // R[flags_88]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_88 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[88].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_88_qs) |
| ); |
| |
| |
| // Subregister 89 of Multireg flags |
| // R[flags_89]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_89 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[89].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_89_qs) |
| ); |
| |
| |
| // Subregister 90 of Multireg flags |
| // R[flags_90]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_90 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[90].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_90_qs) |
| ); |
| |
| |
| // Subregister 91 of Multireg flags |
| // R[flags_91]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_91 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[91].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_91_qs) |
| ); |
| |
| |
| // Subregister 92 of Multireg flags |
| // R[flags_92]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_92 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[92].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_92_qs) |
| ); |
| |
| |
| // Subregister 93 of Multireg flags |
| // R[flags_93]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_93 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[93].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_93_qs) |
| ); |
| |
| |
| // Subregister 94 of Multireg flags |
| // R[flags_94]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_94 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[94].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_94_qs) |
| ); |
| |
| |
| // Subregister 95 of Multireg flags |
| // R[flags_95]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_95 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[95].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_95_qs) |
| ); |
| |
| |
| // Subregister 96 of Multireg flags |
| // R[flags_96]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_96 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[96].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_96_qs) |
| ); |
| |
| |
| // Subregister 97 of Multireg flags |
| // R[flags_97]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_97 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[97].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_97_qs) |
| ); |
| |
| |
| // Subregister 98 of Multireg flags |
| // R[flags_98]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_98 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[98].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_98_qs) |
| ); |
| |
| |
| // Subregister 99 of Multireg flags |
| // R[flags_99]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_99 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[99].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_99_qs) |
| ); |
| |
| |
| // Subregister 100 of Multireg flags |
| // R[flags_100]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_100 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[100].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_100_qs) |
| ); |
| |
| |
| // Subregister 101 of Multireg flags |
| // R[flags_101]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_101 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[101].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_101_qs) |
| ); |
| |
| |
| // Subregister 102 of Multireg flags |
| // R[flags_102]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_102 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[102].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_102_qs) |
| ); |
| |
| |
| // Subregister 103 of Multireg flags |
| // R[flags_103]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_103 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[103].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_103_qs) |
| ); |
| |
| |
| // Subregister 104 of Multireg flags |
| // R[flags_104]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_104 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[104].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_104_qs) |
| ); |
| |
| |
| // Subregister 105 of Multireg flags |
| // R[flags_105]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_105 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[105].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_105_qs) |
| ); |
| |
| |
| // Subregister 106 of Multireg flags |
| // R[flags_106]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_106 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[106].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_106_qs) |
| ); |
| |
| |
| // Subregister 107 of Multireg flags |
| // R[flags_107]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_107 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[107].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_107_qs) |
| ); |
| |
| |
| // Subregister 108 of Multireg flags |
| // R[flags_108]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_108 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[108].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_108_qs) |
| ); |
| |
| |
| // Subregister 109 of Multireg flags |
| // R[flags_109]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_109 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[109].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_109_qs) |
| ); |
| |
| |
| // Subregister 110 of Multireg flags |
| // R[flags_110]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_110 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[110].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_110_qs) |
| ); |
| |
| |
| // Subregister 111 of Multireg flags |
| // R[flags_111]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_111 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[111].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_111_qs) |
| ); |
| |
| |
| // Subregister 112 of Multireg flags |
| // R[flags_112]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_112 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[112].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_112_qs) |
| ); |
| |
| |
| // Subregister 113 of Multireg flags |
| // R[flags_113]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_113 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[113].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_113_qs) |
| ); |
| |
| |
| // Subregister 114 of Multireg flags |
| // R[flags_114]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_114 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[114].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_114_qs) |
| ); |
| |
| |
| // Subregister 115 of Multireg flags |
| // R[flags_115]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_115 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[115].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_115_qs) |
| ); |
| |
| |
| // Subregister 116 of Multireg flags |
| // R[flags_116]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_116 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[116].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_116_qs) |
| ); |
| |
| |
| // Subregister 117 of Multireg flags |
| // R[flags_117]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_117 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[117].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_117_qs) |
| ); |
| |
| |
| // Subregister 118 of Multireg flags |
| // R[flags_118]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_118 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[118].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_118_qs) |
| ); |
| |
| |
| // Subregister 119 of Multireg flags |
| // R[flags_119]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_119 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[119].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_119_qs) |
| ); |
| |
| |
| // Subregister 120 of Multireg flags |
| // R[flags_120]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_120 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[120].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_120_qs) |
| ); |
| |
| |
| // Subregister 121 of Multireg flags |
| // R[flags_121]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_121 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[121].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_121_qs) |
| ); |
| |
| |
| // Subregister 122 of Multireg flags |
| // R[flags_122]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_122 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[122].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_122_qs) |
| ); |
| |
| |
| // Subregister 123 of Multireg flags |
| // R[flags_123]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_123 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[123].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_123_qs) |
| ); |
| |
| |
| // Subregister 124 of Multireg flags |
| // R[flags_124]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_124 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[124].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_124_qs) |
| ); |
| |
| |
| // Subregister 125 of Multireg flags |
| // R[flags_125]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_125 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[125].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_125_qs) |
| ); |
| |
| |
| // Subregister 126 of Multireg flags |
| // R[flags_126]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_126 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[126].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_126_qs) |
| ); |
| |
| |
| // Subregister 127 of Multireg flags |
| // R[flags_127]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_127 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[127].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_127_qs) |
| ); |
| |
| |
| // Subregister 128 of Multireg flags |
| // R[flags_128]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_128 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[128].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_128_qs) |
| ); |
| |
| |
| // Subregister 129 of Multireg flags |
| // R[flags_129]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_129 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[129].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_129_qs) |
| ); |
| |
| |
| // Subregister 130 of Multireg flags |
| // R[flags_130]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_130 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[130].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_130_qs) |
| ); |
| |
| |
| // Subregister 131 of Multireg flags |
| // R[flags_131]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_131 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[131].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_131_qs) |
| ); |
| |
| |
| // Subregister 132 of Multireg flags |
| // R[flags_132]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_132 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[132].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_132_qs) |
| ); |
| |
| |
| // Subregister 133 of Multireg flags |
| // R[flags_133]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_133 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[133].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_133_qs) |
| ); |
| |
| |
| // Subregister 134 of Multireg flags |
| // R[flags_134]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_134 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[134].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_134_qs) |
| ); |
| |
| |
| // Subregister 135 of Multireg flags |
| // R[flags_135]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_135 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[135].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_135_qs) |
| ); |
| |
| |
| // Subregister 136 of Multireg flags |
| // R[flags_136]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_136 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[136].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_136_qs) |
| ); |
| |
| |
| // Subregister 137 of Multireg flags |
| // R[flags_137]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_137 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[137].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_137_qs) |
| ); |
| |
| |
| // Subregister 138 of Multireg flags |
| // R[flags_138]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_138 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[138].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_138_qs) |
| ); |
| |
| |
| // Subregister 139 of Multireg flags |
| // R[flags_139]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_139 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[139].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_139_qs) |
| ); |
| |
| |
| // Subregister 140 of Multireg flags |
| // R[flags_140]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_140 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[140].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_140_qs) |
| ); |
| |
| |
| // Subregister 141 of Multireg flags |
| // R[flags_141]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_141 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[141].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_141_qs) |
| ); |
| |
| |
| // Subregister 142 of Multireg flags |
| // R[flags_142]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_142 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[142].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_142_qs) |
| ); |
| |
| |
| // Subregister 143 of Multireg flags |
| // R[flags_143]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_143 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[143].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_143_qs) |
| ); |
| |
| |
| // Subregister 144 of Multireg flags |
| // R[flags_144]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_144 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[144].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_144_qs) |
| ); |
| |
| |
| // Subregister 145 of Multireg flags |
| // R[flags_145]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_145 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[145].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_145_qs) |
| ); |
| |
| |
| // Subregister 146 of Multireg flags |
| // R[flags_146]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_146 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[146].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_146_qs) |
| ); |
| |
| |
| // Subregister 147 of Multireg flags |
| // R[flags_147]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_147 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[147].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_147_qs) |
| ); |
| |
| |
| // Subregister 148 of Multireg flags |
| // R[flags_148]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_148 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[148].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_148_qs) |
| ); |
| |
| |
| // Subregister 149 of Multireg flags |
| // R[flags_149]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_149 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[149].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_149_qs) |
| ); |
| |
| |
| // Subregister 150 of Multireg flags |
| // R[flags_150]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_150 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[150].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_150_qs) |
| ); |
| |
| |
| // Subregister 151 of Multireg flags |
| // R[flags_151]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_151 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[151].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_151_qs) |
| ); |
| |
| |
| // Subregister 152 of Multireg flags |
| // R[flags_152]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_152 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[152].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_152_qs) |
| ); |
| |
| |
| // Subregister 153 of Multireg flags |
| // R[flags_153]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_153 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[153].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_153_qs) |
| ); |
| |
| |
| // Subregister 154 of Multireg flags |
| // R[flags_154]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_154 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[154].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_154_qs) |
| ); |
| |
| |
| // Subregister 155 of Multireg flags |
| // R[flags_155]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_155 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[155].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_155_qs) |
| ); |
| |
| |
| // Subregister 156 of Multireg flags |
| // R[flags_156]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_156 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[156].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_156_qs) |
| ); |
| |
| |
| // Subregister 157 of Multireg flags |
| // R[flags_157]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_157 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[157].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_157_qs) |
| ); |
| |
| |
| // Subregister 158 of Multireg flags |
| // R[flags_158]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_158 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[158].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_158_qs) |
| ); |
| |
| |
| // Subregister 159 of Multireg flags |
| // R[flags_159]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_159 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[159].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_159_qs) |
| ); |
| |
| |
| // Subregister 160 of Multireg flags |
| // R[flags_160]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_160 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[160].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_160_qs) |
| ); |
| |
| |
| // Subregister 161 of Multireg flags |
| // R[flags_161]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_161 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[161].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_161_qs) |
| ); |
| |
| |
| // Subregister 162 of Multireg flags |
| // R[flags_162]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_162 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[162].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_162_qs) |
| ); |
| |
| |
| // Subregister 163 of Multireg flags |
| // R[flags_163]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_163 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[163].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_163_qs) |
| ); |
| |
| |
| // Subregister 164 of Multireg flags |
| // R[flags_164]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_164 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[164].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_164_qs) |
| ); |
| |
| |
| // Subregister 165 of Multireg flags |
| // R[flags_165]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_165 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[165].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_165_qs) |
| ); |
| |
| |
| // Subregister 166 of Multireg flags |
| // R[flags_166]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_166 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[166].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_166_qs) |
| ); |
| |
| |
| // Subregister 167 of Multireg flags |
| // R[flags_167]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_167 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[167].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_167_qs) |
| ); |
| |
| |
| // Subregister 168 of Multireg flags |
| // R[flags_168]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_168 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[168].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_168_qs) |
| ); |
| |
| |
| // Subregister 169 of Multireg flags |
| // R[flags_169]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_169 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[169].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_169_qs) |
| ); |
| |
| |
| // Subregister 170 of Multireg flags |
| // R[flags_170]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_170 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[170].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_170_qs) |
| ); |
| |
| |
| // Subregister 171 of Multireg flags |
| // R[flags_171]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_171 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[171].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_171_qs) |
| ); |
| |
| |
| // Subregister 172 of Multireg flags |
| // R[flags_172]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_172 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[172].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_172_qs) |
| ); |
| |
| |
| // Subregister 173 of Multireg flags |
| // R[flags_173]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_173 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[173].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_173_qs) |
| ); |
| |
| |
| // Subregister 174 of Multireg flags |
| // R[flags_174]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_174 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[174].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_174_qs) |
| ); |
| |
| |
| // Subregister 175 of Multireg flags |
| // R[flags_175]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_175 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[175].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_175_qs) |
| ); |
| |
| |
| // Subregister 176 of Multireg flags |
| // R[flags_176]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_176 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[176].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_176_qs) |
| ); |
| |
| |
| // Subregister 177 of Multireg flags |
| // R[flags_177]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_177 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[177].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_177_qs) |
| ); |
| |
| |
| // Subregister 178 of Multireg flags |
| // R[flags_178]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_178 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[178].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_178_qs) |
| ); |
| |
| |
| // Subregister 179 of Multireg flags |
| // R[flags_179]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_179 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[179].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_179_qs) |
| ); |
| |
| |
| // Subregister 180 of Multireg flags |
| // R[flags_180]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_180 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[180].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_180_qs) |
| ); |
| |
| |
| // Subregister 181 of Multireg flags |
| // R[flags_181]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_181 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[181].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_181_qs) |
| ); |
| |
| |
| // Subregister 182 of Multireg flags |
| // R[flags_182]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_182 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[182].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_182_qs) |
| ); |
| |
| |
| // Subregister 183 of Multireg flags |
| // R[flags_183]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_183 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[183].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_183_qs) |
| ); |
| |
| |
| // Subregister 184 of Multireg flags |
| // R[flags_184]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_184 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[184].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_184_qs) |
| ); |
| |
| |
| // Subregister 185 of Multireg flags |
| // R[flags_185]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_185 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[185].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_185_qs) |
| ); |
| |
| |
| // Subregister 186 of Multireg flags |
| // R[flags_186]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_186 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[186].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_186_qs) |
| ); |
| |
| |
| // Subregister 187 of Multireg flags |
| // R[flags_187]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_187 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[187].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_187_qs) |
| ); |
| |
| |
| // Subregister 188 of Multireg flags |
| // R[flags_188]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_188 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[188].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_188_qs) |
| ); |
| |
| |
| // Subregister 189 of Multireg flags |
| // R[flags_189]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_189 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[189].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_189_qs) |
| ); |
| |
| |
| // Subregister 190 of Multireg flags |
| // R[flags_190]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_190 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[190].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_190_qs) |
| ); |
| |
| |
| // Subregister 191 of Multireg flags |
| // R[flags_191]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_191 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[191].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_191_qs) |
| ); |
| |
| |
| // Subregister 192 of Multireg flags |
| // R[flags_192]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_192 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[192].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_192_qs) |
| ); |
| |
| |
| // Subregister 193 of Multireg flags |
| // R[flags_193]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_193 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[193].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_193_qs) |
| ); |
| |
| |
| // Subregister 194 of Multireg flags |
| // R[flags_194]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_194 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[194].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_194_qs) |
| ); |
| |
| |
| // Subregister 195 of Multireg flags |
| // R[flags_195]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_195 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[195].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_195_qs) |
| ); |
| |
| |
| // Subregister 196 of Multireg flags |
| // R[flags_196]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_196 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[196].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_196_qs) |
| ); |
| |
| |
| // Subregister 197 of Multireg flags |
| // R[flags_197]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_197 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[197].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_197_qs) |
| ); |
| |
| |
| // Subregister 198 of Multireg flags |
| // R[flags_198]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_198 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[198].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_198_qs) |
| ); |
| |
| |
| // Subregister 199 of Multireg flags |
| // R[flags_199]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_199 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[199].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_199_qs) |
| ); |
| |
| |
| // Subregister 200 of Multireg flags |
| // R[flags_200]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_200 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[200].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_200_qs) |
| ); |
| |
| |
| // Subregister 201 of Multireg flags |
| // R[flags_201]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_201 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[201].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_201_qs) |
| ); |
| |
| |
| // Subregister 202 of Multireg flags |
| // R[flags_202]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_202 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[202].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_202_qs) |
| ); |
| |
| |
| // Subregister 203 of Multireg flags |
| // R[flags_203]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_203 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[203].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_203_qs) |
| ); |
| |
| |
| // Subregister 204 of Multireg flags |
| // R[flags_204]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_204 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[204].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_204_qs) |
| ); |
| |
| |
| // Subregister 205 of Multireg flags |
| // R[flags_205]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_205 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[205].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_205_qs) |
| ); |
| |
| |
| // Subregister 206 of Multireg flags |
| // R[flags_206]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_206 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[206].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_206_qs) |
| ); |
| |
| |
| // Subregister 207 of Multireg flags |
| // R[flags_207]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_207 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[207].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_207_qs) |
| ); |
| |
| |
| // Subregister 208 of Multireg flags |
| // R[flags_208]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_208 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[208].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_208_qs) |
| ); |
| |
| |
| // Subregister 209 of Multireg flags |
| // R[flags_209]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_209 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[209].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_209_qs) |
| ); |
| |
| |
| // Subregister 210 of Multireg flags |
| // R[flags_210]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_210 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[210].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_210_qs) |
| ); |
| |
| |
| // Subregister 211 of Multireg flags |
| // R[flags_211]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_211 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[211].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_211_qs) |
| ); |
| |
| |
| // Subregister 212 of Multireg flags |
| // R[flags_212]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_212 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[212].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_212_qs) |
| ); |
| |
| |
| // Subregister 213 of Multireg flags |
| // R[flags_213]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_213 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[213].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_213_qs) |
| ); |
| |
| |
| // Subregister 214 of Multireg flags |
| // R[flags_214]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_214 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[214].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_214_qs) |
| ); |
| |
| |
| // Subregister 215 of Multireg flags |
| // R[flags_215]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_215 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[215].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_215_qs) |
| ); |
| |
| |
| // Subregister 216 of Multireg flags |
| // R[flags_216]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_216 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[216].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_216_qs) |
| ); |
| |
| |
| // Subregister 217 of Multireg flags |
| // R[flags_217]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_217 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[217].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_217_qs) |
| ); |
| |
| |
| // Subregister 218 of Multireg flags |
| // R[flags_218]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_218 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[218].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_218_qs) |
| ); |
| |
| |
| // Subregister 219 of Multireg flags |
| // R[flags_219]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_219 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[219].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_219_qs) |
| ); |
| |
| |
| // Subregister 220 of Multireg flags |
| // R[flags_220]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_220 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[220].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_220_qs) |
| ); |
| |
| |
| // Subregister 221 of Multireg flags |
| // R[flags_221]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_221 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[221].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_221_qs) |
| ); |
| |
| |
| // Subregister 222 of Multireg flags |
| // R[flags_222]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_222 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[222].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_222_qs) |
| ); |
| |
| |
| // Subregister 223 of Multireg flags |
| // R[flags_223]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_223 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[223].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_223_qs) |
| ); |
| |
| |
| // Subregister 224 of Multireg flags |
| // R[flags_224]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_224 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[224].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_224_qs) |
| ); |
| |
| |
| // Subregister 225 of Multireg flags |
| // R[flags_225]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_225 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[225].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_225_qs) |
| ); |
| |
| |
| // Subregister 226 of Multireg flags |
| // R[flags_226]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_226 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[226].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_226_qs) |
| ); |
| |
| |
| // Subregister 227 of Multireg flags |
| // R[flags_227]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_227 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[227].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_227_qs) |
| ); |
| |
| |
| // Subregister 228 of Multireg flags |
| // R[flags_228]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_228 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[228].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_228_qs) |
| ); |
| |
| |
| // Subregister 229 of Multireg flags |
| // R[flags_229]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_229 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[229].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_229_qs) |
| ); |
| |
| |
| // Subregister 230 of Multireg flags |
| // R[flags_230]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_230 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[230].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_230_qs) |
| ); |
| |
| |
| // Subregister 231 of Multireg flags |
| // R[flags_231]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_231 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[231].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_231_qs) |
| ); |
| |
| |
| // Subregister 232 of Multireg flags |
| // R[flags_232]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_232 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[232].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_232_qs) |
| ); |
| |
| |
| // Subregister 233 of Multireg flags |
| // R[flags_233]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_233 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[233].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_233_qs) |
| ); |
| |
| |
| // Subregister 234 of Multireg flags |
| // R[flags_234]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_234 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[234].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_234_qs) |
| ); |
| |
| |
| // Subregister 235 of Multireg flags |
| // R[flags_235]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_235 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[235].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_235_qs) |
| ); |
| |
| |
| // Subregister 236 of Multireg flags |
| // R[flags_236]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_236 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[236].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_236_qs) |
| ); |
| |
| |
| // Subregister 237 of Multireg flags |
| // R[flags_237]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_237 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[237].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_237_qs) |
| ); |
| |
| |
| // Subregister 238 of Multireg flags |
| // R[flags_238]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_238 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[238].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_238_qs) |
| ); |
| |
| |
| // Subregister 239 of Multireg flags |
| // R[flags_239]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_239 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[239].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_239_qs) |
| ); |
| |
| |
| // Subregister 240 of Multireg flags |
| // R[flags_240]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_240 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[240].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_240_qs) |
| ); |
| |
| |
| // Subregister 241 of Multireg flags |
| // R[flags_241]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_241 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[241].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_241_qs) |
| ); |
| |
| |
| // Subregister 242 of Multireg flags |
| // R[flags_242]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_242 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[242].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_242_qs) |
| ); |
| |
| |
| // Subregister 243 of Multireg flags |
| // R[flags_243]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_243 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[243].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_243_qs) |
| ); |
| |
| |
| // Subregister 244 of Multireg flags |
| // R[flags_244]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_244 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[244].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_244_qs) |
| ); |
| |
| |
| // Subregister 245 of Multireg flags |
| // R[flags_245]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_245 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[245].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_245_qs) |
| ); |
| |
| |
| // Subregister 246 of Multireg flags |
| // R[flags_246]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_246 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[246].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_246_qs) |
| ); |
| |
| |
| // Subregister 247 of Multireg flags |
| // R[flags_247]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_247 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[247].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_247_qs) |
| ); |
| |
| |
| // Subregister 248 of Multireg flags |
| // R[flags_248]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_248 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[248].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_248_qs) |
| ); |
| |
| |
| // Subregister 249 of Multireg flags |
| // R[flags_249]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_249 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[249].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_249_qs) |
| ); |
| |
| |
| // Subregister 250 of Multireg flags |
| // R[flags_250]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_250 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[250].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_250_qs) |
| ); |
| |
| |
| // Subregister 251 of Multireg flags |
| // R[flags_251]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_251 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[251].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_251_qs) |
| ); |
| |
| |
| // Subregister 252 of Multireg flags |
| // R[flags_252]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_252 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[252].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_252_qs) |
| ); |
| |
| |
| // Subregister 253 of Multireg flags |
| // R[flags_253]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_253 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[253].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_253_qs) |
| ); |
| |
| |
| // Subregister 254 of Multireg flags |
| // R[flags_254]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_254 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[254].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_254_qs) |
| ); |
| |
| |
| // Subregister 255 of Multireg flags |
| // R[flags_255]: V(False) |
| prim_subreg #( |
| .DW (32), |
| .SwAccess(prim_subreg_pkg::SwAccessRO), |
| .RESVAL (32'h0) |
| ) u_flags_255 ( |
| .clk_i (clk_i), |
| .rst_ni (rst_ni), |
| |
| // from register interface |
| .we (1'b0), |
| .wd ('0), |
| |
| // from internal hardware |
| .de (1'b0), |
| .d ('0), |
| |
| // to internal hardware |
| .qe (), |
| .q (reg2hw.flags[255].q), |
| .ds (), |
| |
| // to register interface (read) |
| .qs (flags_255_qs) |
| ); |
| |
| |
| |
| logic [280:0] addr_hit; |
| always_comb begin |
| addr_hit = '0; |
| addr_hit[ 0] = (reg_addr == RV_DM_HALTED_OFFSET); |
| addr_hit[ 1] = (reg_addr == RV_DM_GOING_OFFSET); |
| addr_hit[ 2] = (reg_addr == RV_DM_RESUMING_OFFSET); |
| addr_hit[ 3] = (reg_addr == RV_DM_EXCEPTION_OFFSET); |
| addr_hit[ 4] = (reg_addr == RV_DM_WHERETO_OFFSET); |
| addr_hit[ 5] = (reg_addr == RV_DM_ABSTRACTCMD_0_OFFSET); |
| addr_hit[ 6] = (reg_addr == RV_DM_ABSTRACTCMD_1_OFFSET); |
| addr_hit[ 7] = (reg_addr == RV_DM_ABSTRACTCMD_2_OFFSET); |
| addr_hit[ 8] = (reg_addr == RV_DM_ABSTRACTCMD_3_OFFSET); |
| addr_hit[ 9] = (reg_addr == RV_DM_ABSTRACTCMD_4_OFFSET); |
| addr_hit[ 10] = (reg_addr == RV_DM_ABSTRACTCMD_5_OFFSET); |
| addr_hit[ 11] = (reg_addr == RV_DM_ABSTRACTCMD_6_OFFSET); |
| addr_hit[ 12] = (reg_addr == RV_DM_ABSTRACTCMD_7_OFFSET); |
| addr_hit[ 13] = (reg_addr == RV_DM_ABSTRACTCMD_8_OFFSET); |
| addr_hit[ 14] = (reg_addr == RV_DM_ABSTRACTCMD_9_OFFSET); |
| addr_hit[ 15] = (reg_addr == RV_DM_PROGRAM_BUFFER_0_OFFSET); |
| addr_hit[ 16] = (reg_addr == RV_DM_PROGRAM_BUFFER_1_OFFSET); |
| addr_hit[ 17] = (reg_addr == RV_DM_PROGRAM_BUFFER_2_OFFSET); |
| addr_hit[ 18] = (reg_addr == RV_DM_PROGRAM_BUFFER_3_OFFSET); |
| addr_hit[ 19] = (reg_addr == RV_DM_PROGRAM_BUFFER_4_OFFSET); |
| addr_hit[ 20] = (reg_addr == RV_DM_PROGRAM_BUFFER_5_OFFSET); |
| addr_hit[ 21] = (reg_addr == RV_DM_PROGRAM_BUFFER_6_OFFSET); |
| addr_hit[ 22] = (reg_addr == RV_DM_PROGRAM_BUFFER_7_OFFSET); |
| addr_hit[ 23] = (reg_addr == RV_DM_DATAADDR_0_OFFSET); |
| addr_hit[ 24] = (reg_addr == RV_DM_DATAADDR_1_OFFSET); |
| addr_hit[ 25] = (reg_addr == RV_DM_FLAGS_0_OFFSET); |
| addr_hit[ 26] = (reg_addr == RV_DM_FLAGS_1_OFFSET); |
| addr_hit[ 27] = (reg_addr == RV_DM_FLAGS_2_OFFSET); |
| addr_hit[ 28] = (reg_addr == RV_DM_FLAGS_3_OFFSET); |
| addr_hit[ 29] = (reg_addr == RV_DM_FLAGS_4_OFFSET); |
| addr_hit[ 30] = (reg_addr == RV_DM_FLAGS_5_OFFSET); |
| addr_hit[ 31] = (reg_addr == RV_DM_FLAGS_6_OFFSET); |
| addr_hit[ 32] = (reg_addr == RV_DM_FLAGS_7_OFFSET); |
| addr_hit[ 33] = (reg_addr == RV_DM_FLAGS_8_OFFSET); |
| addr_hit[ 34] = (reg_addr == RV_DM_FLAGS_9_OFFSET); |
| addr_hit[ 35] = (reg_addr == RV_DM_FLAGS_10_OFFSET); |
| addr_hit[ 36] = (reg_addr == RV_DM_FLAGS_11_OFFSET); |
| addr_hit[ 37] = (reg_addr == RV_DM_FLAGS_12_OFFSET); |
| addr_hit[ 38] = (reg_addr == RV_DM_FLAGS_13_OFFSET); |
| addr_hit[ 39] = (reg_addr == RV_DM_FLAGS_14_OFFSET); |
| addr_hit[ 40] = (reg_addr == RV_DM_FLAGS_15_OFFSET); |
| addr_hit[ 41] = (reg_addr == RV_DM_FLAGS_16_OFFSET); |
| addr_hit[ 42] = (reg_addr == RV_DM_FLAGS_17_OFFSET); |
| addr_hit[ 43] = (reg_addr == RV_DM_FLAGS_18_OFFSET); |
| addr_hit[ 44] = (reg_addr == RV_DM_FLAGS_19_OFFSET); |
| addr_hit[ 45] = (reg_addr == RV_DM_FLAGS_20_OFFSET); |
| addr_hit[ 46] = (reg_addr == RV_DM_FLAGS_21_OFFSET); |
| addr_hit[ 47] = (reg_addr == RV_DM_FLAGS_22_OFFSET); |
| addr_hit[ 48] = (reg_addr == RV_DM_FLAGS_23_OFFSET); |
| addr_hit[ 49] = (reg_addr == RV_DM_FLAGS_24_OFFSET); |
| addr_hit[ 50] = (reg_addr == RV_DM_FLAGS_25_OFFSET); |
| addr_hit[ 51] = (reg_addr == RV_DM_FLAGS_26_OFFSET); |
| addr_hit[ 52] = (reg_addr == RV_DM_FLAGS_27_OFFSET); |
| addr_hit[ 53] = (reg_addr == RV_DM_FLAGS_28_OFFSET); |
| addr_hit[ 54] = (reg_addr == RV_DM_FLAGS_29_OFFSET); |
| addr_hit[ 55] = (reg_addr == RV_DM_FLAGS_30_OFFSET); |
| addr_hit[ 56] = (reg_addr == RV_DM_FLAGS_31_OFFSET); |
| addr_hit[ 57] = (reg_addr == RV_DM_FLAGS_32_OFFSET); |
| addr_hit[ 58] = (reg_addr == RV_DM_FLAGS_33_OFFSET); |
| addr_hit[ 59] = (reg_addr == RV_DM_FLAGS_34_OFFSET); |
| addr_hit[ 60] = (reg_addr == RV_DM_FLAGS_35_OFFSET); |
| addr_hit[ 61] = (reg_addr == RV_DM_FLAGS_36_OFFSET); |
| addr_hit[ 62] = (reg_addr == RV_DM_FLAGS_37_OFFSET); |
| addr_hit[ 63] = (reg_addr == RV_DM_FLAGS_38_OFFSET); |
| addr_hit[ 64] = (reg_addr == RV_DM_FLAGS_39_OFFSET); |
| addr_hit[ 65] = (reg_addr == RV_DM_FLAGS_40_OFFSET); |
| addr_hit[ 66] = (reg_addr == RV_DM_FLAGS_41_OFFSET); |
| addr_hit[ 67] = (reg_addr == RV_DM_FLAGS_42_OFFSET); |
| addr_hit[ 68] = (reg_addr == RV_DM_FLAGS_43_OFFSET); |
| addr_hit[ 69] = (reg_addr == RV_DM_FLAGS_44_OFFSET); |
| addr_hit[ 70] = (reg_addr == RV_DM_FLAGS_45_OFFSET); |
| addr_hit[ 71] = (reg_addr == RV_DM_FLAGS_46_OFFSET); |
| addr_hit[ 72] = (reg_addr == RV_DM_FLAGS_47_OFFSET); |
| addr_hit[ 73] = (reg_addr == RV_DM_FLAGS_48_OFFSET); |
| addr_hit[ 74] = (reg_addr == RV_DM_FLAGS_49_OFFSET); |
| addr_hit[ 75] = (reg_addr == RV_DM_FLAGS_50_OFFSET); |
| addr_hit[ 76] = (reg_addr == RV_DM_FLAGS_51_OFFSET); |
| addr_hit[ 77] = (reg_addr == RV_DM_FLAGS_52_OFFSET); |
| addr_hit[ 78] = (reg_addr == RV_DM_FLAGS_53_OFFSET); |
| addr_hit[ 79] = (reg_addr == RV_DM_FLAGS_54_OFFSET); |
| addr_hit[ 80] = (reg_addr == RV_DM_FLAGS_55_OFFSET); |
| addr_hit[ 81] = (reg_addr == RV_DM_FLAGS_56_OFFSET); |
| addr_hit[ 82] = (reg_addr == RV_DM_FLAGS_57_OFFSET); |
| addr_hit[ 83] = (reg_addr == RV_DM_FLAGS_58_OFFSET); |
| addr_hit[ 84] = (reg_addr == RV_DM_FLAGS_59_OFFSET); |
| addr_hit[ 85] = (reg_addr == RV_DM_FLAGS_60_OFFSET); |
| addr_hit[ 86] = (reg_addr == RV_DM_FLAGS_61_OFFSET); |
| addr_hit[ 87] = (reg_addr == RV_DM_FLAGS_62_OFFSET); |
| addr_hit[ 88] = (reg_addr == RV_DM_FLAGS_63_OFFSET); |
| addr_hit[ 89] = (reg_addr == RV_DM_FLAGS_64_OFFSET); |
| addr_hit[ 90] = (reg_addr == RV_DM_FLAGS_65_OFFSET); |
| addr_hit[ 91] = (reg_addr == RV_DM_FLAGS_66_OFFSET); |
| addr_hit[ 92] = (reg_addr == RV_DM_FLAGS_67_OFFSET); |
| addr_hit[ 93] = (reg_addr == RV_DM_FLAGS_68_OFFSET); |
| addr_hit[ 94] = (reg_addr == RV_DM_FLAGS_69_OFFSET); |
| addr_hit[ 95] = (reg_addr == RV_DM_FLAGS_70_OFFSET); |
| addr_hit[ 96] = (reg_addr == RV_DM_FLAGS_71_OFFSET); |
| addr_hit[ 97] = (reg_addr == RV_DM_FLAGS_72_OFFSET); |
| addr_hit[ 98] = (reg_addr == RV_DM_FLAGS_73_OFFSET); |
| addr_hit[ 99] = (reg_addr == RV_DM_FLAGS_74_OFFSET); |
| addr_hit[100] = (reg_addr == RV_DM_FLAGS_75_OFFSET); |
| addr_hit[101] = (reg_addr == RV_DM_FLAGS_76_OFFSET); |
| addr_hit[102] = (reg_addr == RV_DM_FLAGS_77_OFFSET); |
| addr_hit[103] = (reg_addr == RV_DM_FLAGS_78_OFFSET); |
| addr_hit[104] = (reg_addr == RV_DM_FLAGS_79_OFFSET); |
| addr_hit[105] = (reg_addr == RV_DM_FLAGS_80_OFFSET); |
| addr_hit[106] = (reg_addr == RV_DM_FLAGS_81_OFFSET); |
| addr_hit[107] = (reg_addr == RV_DM_FLAGS_82_OFFSET); |
| addr_hit[108] = (reg_addr == RV_DM_FLAGS_83_OFFSET); |
| addr_hit[109] = (reg_addr == RV_DM_FLAGS_84_OFFSET); |
| addr_hit[110] = (reg_addr == RV_DM_FLAGS_85_OFFSET); |
| addr_hit[111] = (reg_addr == RV_DM_FLAGS_86_OFFSET); |
| addr_hit[112] = (reg_addr == RV_DM_FLAGS_87_OFFSET); |
| addr_hit[113] = (reg_addr == RV_DM_FLAGS_88_OFFSET); |
| addr_hit[114] = (reg_addr == RV_DM_FLAGS_89_OFFSET); |
| addr_hit[115] = (reg_addr == RV_DM_FLAGS_90_OFFSET); |
| addr_hit[116] = (reg_addr == RV_DM_FLAGS_91_OFFSET); |
| addr_hit[117] = (reg_addr == RV_DM_FLAGS_92_OFFSET); |
| addr_hit[118] = (reg_addr == RV_DM_FLAGS_93_OFFSET); |
| addr_hit[119] = (reg_addr == RV_DM_FLAGS_94_OFFSET); |
| addr_hit[120] = (reg_addr == RV_DM_FLAGS_95_OFFSET); |
| addr_hit[121] = (reg_addr == RV_DM_FLAGS_96_OFFSET); |
| addr_hit[122] = (reg_addr == RV_DM_FLAGS_97_OFFSET); |
| addr_hit[123] = (reg_addr == RV_DM_FLAGS_98_OFFSET); |
| addr_hit[124] = (reg_addr == RV_DM_FLAGS_99_OFFSET); |
| addr_hit[125] = (reg_addr == RV_DM_FLAGS_100_OFFSET); |
| addr_hit[126] = (reg_addr == RV_DM_FLAGS_101_OFFSET); |
| addr_hit[127] = (reg_addr == RV_DM_FLAGS_102_OFFSET); |
| addr_hit[128] = (reg_addr == RV_DM_FLAGS_103_OFFSET); |
| addr_hit[129] = (reg_addr == RV_DM_FLAGS_104_OFFSET); |
| addr_hit[130] = (reg_addr == RV_DM_FLAGS_105_OFFSET); |
| addr_hit[131] = (reg_addr == RV_DM_FLAGS_106_OFFSET); |
| addr_hit[132] = (reg_addr == RV_DM_FLAGS_107_OFFSET); |
| addr_hit[133] = (reg_addr == RV_DM_FLAGS_108_OFFSET); |
| addr_hit[134] = (reg_addr == RV_DM_FLAGS_109_OFFSET); |
| addr_hit[135] = (reg_addr == RV_DM_FLAGS_110_OFFSET); |
| addr_hit[136] = (reg_addr == RV_DM_FLAGS_111_OFFSET); |
| addr_hit[137] = (reg_addr == RV_DM_FLAGS_112_OFFSET); |
| addr_hit[138] = (reg_addr == RV_DM_FLAGS_113_OFFSET); |
| addr_hit[139] = (reg_addr == RV_DM_FLAGS_114_OFFSET); |
| addr_hit[140] = (reg_addr == RV_DM_FLAGS_115_OFFSET); |
| addr_hit[141] = (reg_addr == RV_DM_FLAGS_116_OFFSET); |
| addr_hit[142] = (reg_addr == RV_DM_FLAGS_117_OFFSET); |
| addr_hit[143] = (reg_addr == RV_DM_FLAGS_118_OFFSET); |
| addr_hit[144] = (reg_addr == RV_DM_FLAGS_119_OFFSET); |
| addr_hit[145] = (reg_addr == RV_DM_FLAGS_120_OFFSET); |
| addr_hit[146] = (reg_addr == RV_DM_FLAGS_121_OFFSET); |
| addr_hit[147] = (reg_addr == RV_DM_FLAGS_122_OFFSET); |
| addr_hit[148] = (reg_addr == RV_DM_FLAGS_123_OFFSET); |
| addr_hit[149] = (reg_addr == RV_DM_FLAGS_124_OFFSET); |
| addr_hit[150] = (reg_addr == RV_DM_FLAGS_125_OFFSET); |
| addr_hit[151] = (reg_addr == RV_DM_FLAGS_126_OFFSET); |
| addr_hit[152] = (reg_addr == RV_DM_FLAGS_127_OFFSET); |
| addr_hit[153] = (reg_addr == RV_DM_FLAGS_128_OFFSET); |
| addr_hit[154] = (reg_addr == RV_DM_FLAGS_129_OFFSET); |
| addr_hit[155] = (reg_addr == RV_DM_FLAGS_130_OFFSET); |
| addr_hit[156] = (reg_addr == RV_DM_FLAGS_131_OFFSET); |
| addr_hit[157] = (reg_addr == RV_DM_FLAGS_132_OFFSET); |
| addr_hit[158] = (reg_addr == RV_DM_FLAGS_133_OFFSET); |
| addr_hit[159] = (reg_addr == RV_DM_FLAGS_134_OFFSET); |
| addr_hit[160] = (reg_addr == RV_DM_FLAGS_135_OFFSET); |
| addr_hit[161] = (reg_addr == RV_DM_FLAGS_136_OFFSET); |
| addr_hit[162] = (reg_addr == RV_DM_FLAGS_137_OFFSET); |
| addr_hit[163] = (reg_addr == RV_DM_FLAGS_138_OFFSET); |
| addr_hit[164] = (reg_addr == RV_DM_FLAGS_139_OFFSET); |
| addr_hit[165] = (reg_addr == RV_DM_FLAGS_140_OFFSET); |
| addr_hit[166] = (reg_addr == RV_DM_FLAGS_141_OFFSET); |
| addr_hit[167] = (reg_addr == RV_DM_FLAGS_142_OFFSET); |
| addr_hit[168] = (reg_addr == RV_DM_FLAGS_143_OFFSET); |
| addr_hit[169] = (reg_addr == RV_DM_FLAGS_144_OFFSET); |
| addr_hit[170] = (reg_addr == RV_DM_FLAGS_145_OFFSET); |
| addr_hit[171] = (reg_addr == RV_DM_FLAGS_146_OFFSET); |
| addr_hit[172] = (reg_addr == RV_DM_FLAGS_147_OFFSET); |
| addr_hit[173] = (reg_addr == RV_DM_FLAGS_148_OFFSET); |
| addr_hit[174] = (reg_addr == RV_DM_FLAGS_149_OFFSET); |
| addr_hit[175] = (reg_addr == RV_DM_FLAGS_150_OFFSET); |
| addr_hit[176] = (reg_addr == RV_DM_FLAGS_151_OFFSET); |
| addr_hit[177] = (reg_addr == RV_DM_FLAGS_152_OFFSET); |
| addr_hit[178] = (reg_addr == RV_DM_FLAGS_153_OFFSET); |
| addr_hit[179] = (reg_addr == RV_DM_FLAGS_154_OFFSET); |
| addr_hit[180] = (reg_addr == RV_DM_FLAGS_155_OFFSET); |
| addr_hit[181] = (reg_addr == RV_DM_FLAGS_156_OFFSET); |
| addr_hit[182] = (reg_addr == RV_DM_FLAGS_157_OFFSET); |
| addr_hit[183] = (reg_addr == RV_DM_FLAGS_158_OFFSET); |
| addr_hit[184] = (reg_addr == RV_DM_FLAGS_159_OFFSET); |
| addr_hit[185] = (reg_addr == RV_DM_FLAGS_160_OFFSET); |
| addr_hit[186] = (reg_addr == RV_DM_FLAGS_161_OFFSET); |
| addr_hit[187] = (reg_addr == RV_DM_FLAGS_162_OFFSET); |
| addr_hit[188] = (reg_addr == RV_DM_FLAGS_163_OFFSET); |
| addr_hit[189] = (reg_addr == RV_DM_FLAGS_164_OFFSET); |
| addr_hit[190] = (reg_addr == RV_DM_FLAGS_165_OFFSET); |
| addr_hit[191] = (reg_addr == RV_DM_FLAGS_166_OFFSET); |
| addr_hit[192] = (reg_addr == RV_DM_FLAGS_167_OFFSET); |
| addr_hit[193] = (reg_addr == RV_DM_FLAGS_168_OFFSET); |
| addr_hit[194] = (reg_addr == RV_DM_FLAGS_169_OFFSET); |
| addr_hit[195] = (reg_addr == RV_DM_FLAGS_170_OFFSET); |
| addr_hit[196] = (reg_addr == RV_DM_FLAGS_171_OFFSET); |
| addr_hit[197] = (reg_addr == RV_DM_FLAGS_172_OFFSET); |
| addr_hit[198] = (reg_addr == RV_DM_FLAGS_173_OFFSET); |
| addr_hit[199] = (reg_addr == RV_DM_FLAGS_174_OFFSET); |
| addr_hit[200] = (reg_addr == RV_DM_FLAGS_175_OFFSET); |
| addr_hit[201] = (reg_addr == RV_DM_FLAGS_176_OFFSET); |
| addr_hit[202] = (reg_addr == RV_DM_FLAGS_177_OFFSET); |
| addr_hit[203] = (reg_addr == RV_DM_FLAGS_178_OFFSET); |
| addr_hit[204] = (reg_addr == RV_DM_FLAGS_179_OFFSET); |
| addr_hit[205] = (reg_addr == RV_DM_FLAGS_180_OFFSET); |
| addr_hit[206] = (reg_addr == RV_DM_FLAGS_181_OFFSET); |
| addr_hit[207] = (reg_addr == RV_DM_FLAGS_182_OFFSET); |
| addr_hit[208] = (reg_addr == RV_DM_FLAGS_183_OFFSET); |
| addr_hit[209] = (reg_addr == RV_DM_FLAGS_184_OFFSET); |
| addr_hit[210] = (reg_addr == RV_DM_FLAGS_185_OFFSET); |
| addr_hit[211] = (reg_addr == RV_DM_FLAGS_186_OFFSET); |
| addr_hit[212] = (reg_addr == RV_DM_FLAGS_187_OFFSET); |
| addr_hit[213] = (reg_addr == RV_DM_FLAGS_188_OFFSET); |
| addr_hit[214] = (reg_addr == RV_DM_FLAGS_189_OFFSET); |
| addr_hit[215] = (reg_addr == RV_DM_FLAGS_190_OFFSET); |
| addr_hit[216] = (reg_addr == RV_DM_FLAGS_191_OFFSET); |
| addr_hit[217] = (reg_addr == RV_DM_FLAGS_192_OFFSET); |
| addr_hit[218] = (reg_addr == RV_DM_FLAGS_193_OFFSET); |
| addr_hit[219] = (reg_addr == RV_DM_FLAGS_194_OFFSET); |
| addr_hit[220] = (reg_addr == RV_DM_FLAGS_195_OFFSET); |
| addr_hit[221] = (reg_addr == RV_DM_FLAGS_196_OFFSET); |
| addr_hit[222] = (reg_addr == RV_DM_FLAGS_197_OFFSET); |
| addr_hit[223] = (reg_addr == RV_DM_FLAGS_198_OFFSET); |
| addr_hit[224] = (reg_addr == RV_DM_FLAGS_199_OFFSET); |
| addr_hit[225] = (reg_addr == RV_DM_FLAGS_200_OFFSET); |
| addr_hit[226] = (reg_addr == RV_DM_FLAGS_201_OFFSET); |
| addr_hit[227] = (reg_addr == RV_DM_FLAGS_202_OFFSET); |
| addr_hit[228] = (reg_addr == RV_DM_FLAGS_203_OFFSET); |
| addr_hit[229] = (reg_addr == RV_DM_FLAGS_204_OFFSET); |
| addr_hit[230] = (reg_addr == RV_DM_FLAGS_205_OFFSET); |
| addr_hit[231] = (reg_addr == RV_DM_FLAGS_206_OFFSET); |
| addr_hit[232] = (reg_addr == RV_DM_FLAGS_207_OFFSET); |
| addr_hit[233] = (reg_addr == RV_DM_FLAGS_208_OFFSET); |
| addr_hit[234] = (reg_addr == RV_DM_FLAGS_209_OFFSET); |
| addr_hit[235] = (reg_addr == RV_DM_FLAGS_210_OFFSET); |
| addr_hit[236] = (reg_addr == RV_DM_FLAGS_211_OFFSET); |
| addr_hit[237] = (reg_addr == RV_DM_FLAGS_212_OFFSET); |
| addr_hit[238] = (reg_addr == RV_DM_FLAGS_213_OFFSET); |
| addr_hit[239] = (reg_addr == RV_DM_FLAGS_214_OFFSET); |
| addr_hit[240] = (reg_addr == RV_DM_FLAGS_215_OFFSET); |
| addr_hit[241] = (reg_addr == RV_DM_FLAGS_216_OFFSET); |
| addr_hit[242] = (reg_addr == RV_DM_FLAGS_217_OFFSET); |
| addr_hit[243] = (reg_addr == RV_DM_FLAGS_218_OFFSET); |
| addr_hit[244] = (reg_addr == RV_DM_FLAGS_219_OFFSET); |
| addr_hit[245] = (reg_addr == RV_DM_FLAGS_220_OFFSET); |
| addr_hit[246] = (reg_addr == RV_DM_FLAGS_221_OFFSET); |
| addr_hit[247] = (reg_addr == RV_DM_FLAGS_222_OFFSET); |
| addr_hit[248] = (reg_addr == RV_DM_FLAGS_223_OFFSET); |
| addr_hit[249] = (reg_addr == RV_DM_FLAGS_224_OFFSET); |
| addr_hit[250] = (reg_addr == RV_DM_FLAGS_225_OFFSET); |
| addr_hit[251] = (reg_addr == RV_DM_FLAGS_226_OFFSET); |
| addr_hit[252] = (reg_addr == RV_DM_FLAGS_227_OFFSET); |
| addr_hit[253] = (reg_addr == RV_DM_FLAGS_228_OFFSET); |
| addr_hit[254] = (reg_addr == RV_DM_FLAGS_229_OFFSET); |
| addr_hit[255] = (reg_addr == RV_DM_FLAGS_230_OFFSET); |
| addr_hit[256] = (reg_addr == RV_DM_FLAGS_231_OFFSET); |
| addr_hit[257] = (reg_addr == RV_DM_FLAGS_232_OFFSET); |
| addr_hit[258] = (reg_addr == RV_DM_FLAGS_233_OFFSET); |
| addr_hit[259] = (reg_addr == RV_DM_FLAGS_234_OFFSET); |
| addr_hit[260] = (reg_addr == RV_DM_FLAGS_235_OFFSET); |
| addr_hit[261] = (reg_addr == RV_DM_FLAGS_236_OFFSET); |
| addr_hit[262] = (reg_addr == RV_DM_FLAGS_237_OFFSET); |
| addr_hit[263] = (reg_addr == RV_DM_FLAGS_238_OFFSET); |
| addr_hit[264] = (reg_addr == RV_DM_FLAGS_239_OFFSET); |
| addr_hit[265] = (reg_addr == RV_DM_FLAGS_240_OFFSET); |
| addr_hit[266] = (reg_addr == RV_DM_FLAGS_241_OFFSET); |
| addr_hit[267] = (reg_addr == RV_DM_FLAGS_242_OFFSET); |
| addr_hit[268] = (reg_addr == RV_DM_FLAGS_243_OFFSET); |
| addr_hit[269] = (reg_addr == RV_DM_FLAGS_244_OFFSET); |
| addr_hit[270] = (reg_addr == RV_DM_FLAGS_245_OFFSET); |
| addr_hit[271] = (reg_addr == RV_DM_FLAGS_246_OFFSET); |
| addr_hit[272] = (reg_addr == RV_DM_FLAGS_247_OFFSET); |
| addr_hit[273] = (reg_addr == RV_DM_FLAGS_248_OFFSET); |
| addr_hit[274] = (reg_addr == RV_DM_FLAGS_249_OFFSET); |
| addr_hit[275] = (reg_addr == RV_DM_FLAGS_250_OFFSET); |
| addr_hit[276] = (reg_addr == RV_DM_FLAGS_251_OFFSET); |
| addr_hit[277] = (reg_addr == RV_DM_FLAGS_252_OFFSET); |
| addr_hit[278] = (reg_addr == RV_DM_FLAGS_253_OFFSET); |
| addr_hit[279] = (reg_addr == RV_DM_FLAGS_254_OFFSET); |
| addr_hit[280] = (reg_addr == RV_DM_FLAGS_255_OFFSET); |
| end |
| |
| assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; |
| |
| // Check sub-word write is permitted |
| always_comb begin |
| wr_err = (reg_we & |
| ((addr_hit[ 0] & (|(RV_DM_MEM_PERMIT[ 0] & ~reg_be))) | |
| (addr_hit[ 1] & (|(RV_DM_MEM_PERMIT[ 1] & ~reg_be))) | |
| (addr_hit[ 2] & (|(RV_DM_MEM_PERMIT[ 2] & ~reg_be))) | |
| (addr_hit[ 3] & (|(RV_DM_MEM_PERMIT[ 3] & ~reg_be))) | |
| (addr_hit[ 4] & (|(RV_DM_MEM_PERMIT[ 4] & ~reg_be))) | |
| (addr_hit[ 5] & (|(RV_DM_MEM_PERMIT[ 5] & ~reg_be))) | |
| (addr_hit[ 6] & (|(RV_DM_MEM_PERMIT[ 6] & ~reg_be))) | |
| (addr_hit[ 7] & (|(RV_DM_MEM_PERMIT[ 7] & ~reg_be))) | |
| (addr_hit[ 8] & (|(RV_DM_MEM_PERMIT[ 8] & ~reg_be))) | |
| (addr_hit[ 9] & (|(RV_DM_MEM_PERMIT[ 9] & ~reg_be))) | |
| (addr_hit[ 10] & (|(RV_DM_MEM_PERMIT[ 10] & ~reg_be))) | |
| (addr_hit[ 11] & (|(RV_DM_MEM_PERMIT[ 11] & ~reg_be))) | |
| (addr_hit[ 12] & (|(RV_DM_MEM_PERMIT[ 12] & ~reg_be))) | |
| (addr_hit[ 13] & (|(RV_DM_MEM_PERMIT[ 13] & ~reg_be))) | |
| (addr_hit[ 14] & (|(RV_DM_MEM_PERMIT[ 14] & ~reg_be))) | |
| (addr_hit[ 15] & (|(RV_DM_MEM_PERMIT[ 15] & ~reg_be))) | |
| (addr_hit[ 16] & (|(RV_DM_MEM_PERMIT[ 16] & ~reg_be))) | |
| (addr_hit[ 17] & (|(RV_DM_MEM_PERMIT[ 17] & ~reg_be))) | |
| (addr_hit[ 18] & (|(RV_DM_MEM_PERMIT[ 18] & ~reg_be))) | |
| (addr_hit[ 19] & (|(RV_DM_MEM_PERMIT[ 19] & ~reg_be))) | |
| (addr_hit[ 20] & (|(RV_DM_MEM_PERMIT[ 20] & ~reg_be))) | |
| (addr_hit[ 21] & (|(RV_DM_MEM_PERMIT[ 21] & ~reg_be))) | |
| (addr_hit[ 22] & (|(RV_DM_MEM_PERMIT[ 22] & ~reg_be))) | |
| (addr_hit[ 23] & (|(RV_DM_MEM_PERMIT[ 23] & ~reg_be))) | |
| (addr_hit[ 24] & (|(RV_DM_MEM_PERMIT[ 24] & ~reg_be))) | |
| (addr_hit[ 25] & (|(RV_DM_MEM_PERMIT[ 25] & ~reg_be))) | |
| (addr_hit[ 26] & (|(RV_DM_MEM_PERMIT[ 26] & ~reg_be))) | |
| (addr_hit[ 27] & (|(RV_DM_MEM_PERMIT[ 27] & ~reg_be))) | |
| (addr_hit[ 28] & (|(RV_DM_MEM_PERMIT[ 28] & ~reg_be))) | |
| (addr_hit[ 29] & (|(RV_DM_MEM_PERMIT[ 29] & ~reg_be))) | |
| (addr_hit[ 30] & (|(RV_DM_MEM_PERMIT[ 30] & ~reg_be))) | |
| (addr_hit[ 31] & (|(RV_DM_MEM_PERMIT[ 31] & ~reg_be))) | |
| (addr_hit[ 32] & (|(RV_DM_MEM_PERMIT[ 32] & ~reg_be))) | |
| (addr_hit[ 33] & (|(RV_DM_MEM_PERMIT[ 33] & ~reg_be))) | |
| (addr_hit[ 34] & (|(RV_DM_MEM_PERMIT[ 34] & ~reg_be))) | |
| (addr_hit[ 35] & (|(RV_DM_MEM_PERMIT[ 35] & ~reg_be))) | |
| (addr_hit[ 36] & (|(RV_DM_MEM_PERMIT[ 36] & ~reg_be))) | |
| (addr_hit[ 37] & (|(RV_DM_MEM_PERMIT[ 37] & ~reg_be))) | |
| (addr_hit[ 38] & (|(RV_DM_MEM_PERMIT[ 38] & ~reg_be))) | |
| (addr_hit[ 39] & (|(RV_DM_MEM_PERMIT[ 39] & ~reg_be))) | |
| (addr_hit[ 40] & (|(RV_DM_MEM_PERMIT[ 40] & ~reg_be))) | |
| (addr_hit[ 41] & (|(RV_DM_MEM_PERMIT[ 41] & ~reg_be))) | |
| (addr_hit[ 42] & (|(RV_DM_MEM_PERMIT[ 42] & ~reg_be))) | |
| (addr_hit[ 43] & (|(RV_DM_MEM_PERMIT[ 43] & ~reg_be))) | |
| (addr_hit[ 44] & (|(RV_DM_MEM_PERMIT[ 44] & ~reg_be))) | |
| (addr_hit[ 45] & (|(RV_DM_MEM_PERMIT[ 45] & ~reg_be))) | |
| (addr_hit[ 46] & (|(RV_DM_MEM_PERMIT[ 46] & ~reg_be))) | |
| (addr_hit[ 47] & (|(RV_DM_MEM_PERMIT[ 47] & ~reg_be))) | |
| (addr_hit[ 48] & (|(RV_DM_MEM_PERMIT[ 48] & ~reg_be))) | |
| (addr_hit[ 49] & (|(RV_DM_MEM_PERMIT[ 49] & ~reg_be))) | |
| (addr_hit[ 50] & (|(RV_DM_MEM_PERMIT[ 50] & ~reg_be))) | |
| (addr_hit[ 51] & (|(RV_DM_MEM_PERMIT[ 51] & ~reg_be))) | |
| (addr_hit[ 52] & (|(RV_DM_MEM_PERMIT[ 52] & ~reg_be))) | |
| (addr_hit[ 53] & (|(RV_DM_MEM_PERMIT[ 53] & ~reg_be))) | |
| (addr_hit[ 54] & (|(RV_DM_MEM_PERMIT[ 54] & ~reg_be))) | |
| (addr_hit[ 55] & (|(RV_DM_MEM_PERMIT[ 55] & ~reg_be))) | |
| (addr_hit[ 56] & (|(RV_DM_MEM_PERMIT[ 56] & ~reg_be))) | |
| (addr_hit[ 57] & (|(RV_DM_MEM_PERMIT[ 57] & ~reg_be))) | |
| (addr_hit[ 58] & (|(RV_DM_MEM_PERMIT[ 58] & ~reg_be))) | |
| (addr_hit[ 59] & (|(RV_DM_MEM_PERMIT[ 59] & ~reg_be))) | |
| (addr_hit[ 60] & (|(RV_DM_MEM_PERMIT[ 60] & ~reg_be))) | |
| (addr_hit[ 61] & (|(RV_DM_MEM_PERMIT[ 61] & ~reg_be))) | |
| (addr_hit[ 62] & (|(RV_DM_MEM_PERMIT[ 62] & ~reg_be))) | |
| (addr_hit[ 63] & (|(RV_DM_MEM_PERMIT[ 63] & ~reg_be))) | |
| (addr_hit[ 64] & (|(RV_DM_MEM_PERMIT[ 64] & ~reg_be))) | |
| (addr_hit[ 65] & (|(RV_DM_MEM_PERMIT[ 65] & ~reg_be))) | |
| (addr_hit[ 66] & (|(RV_DM_MEM_PERMIT[ 66] & ~reg_be))) | |
| (addr_hit[ 67] & (|(RV_DM_MEM_PERMIT[ 67] & ~reg_be))) | |
| (addr_hit[ 68] & (|(RV_DM_MEM_PERMIT[ 68] & ~reg_be))) | |
| (addr_hit[ 69] & (|(RV_DM_MEM_PERMIT[ 69] & ~reg_be))) | |
| (addr_hit[ 70] & (|(RV_DM_MEM_PERMIT[ 70] & ~reg_be))) | |
| (addr_hit[ 71] & (|(RV_DM_MEM_PERMIT[ 71] & ~reg_be))) | |
| (addr_hit[ 72] & (|(RV_DM_MEM_PERMIT[ 72] & ~reg_be))) | |
| (addr_hit[ 73] & (|(RV_DM_MEM_PERMIT[ 73] & ~reg_be))) | |
| (addr_hit[ 74] & (|(RV_DM_MEM_PERMIT[ 74] & ~reg_be))) | |
| (addr_hit[ 75] & (|(RV_DM_MEM_PERMIT[ 75] & ~reg_be))) | |
| (addr_hit[ 76] & (|(RV_DM_MEM_PERMIT[ 76] & ~reg_be))) | |
| (addr_hit[ 77] & (|(RV_DM_MEM_PERMIT[ 77] & ~reg_be))) | |
| (addr_hit[ 78] & (|(RV_DM_MEM_PERMIT[ 78] & ~reg_be))) | |
| (addr_hit[ 79] & (|(RV_DM_MEM_PERMIT[ 79] & ~reg_be))) | |
| (addr_hit[ 80] & (|(RV_DM_MEM_PERMIT[ 80] & ~reg_be))) | |
| (addr_hit[ 81] & (|(RV_DM_MEM_PERMIT[ 81] & ~reg_be))) | |
| (addr_hit[ 82] & (|(RV_DM_MEM_PERMIT[ 82] & ~reg_be))) | |
| (addr_hit[ 83] & (|(RV_DM_MEM_PERMIT[ 83] & ~reg_be))) | |
| (addr_hit[ 84] & (|(RV_DM_MEM_PERMIT[ 84] & ~reg_be))) | |
| (addr_hit[ 85] & (|(RV_DM_MEM_PERMIT[ 85] & ~reg_be))) | |
| (addr_hit[ 86] & (|(RV_DM_MEM_PERMIT[ 86] & ~reg_be))) | |
| (addr_hit[ 87] & (|(RV_DM_MEM_PERMIT[ 87] & ~reg_be))) | |
| (addr_hit[ 88] & (|(RV_DM_MEM_PERMIT[ 88] & ~reg_be))) | |
| (addr_hit[ 89] & (|(RV_DM_MEM_PERMIT[ 89] & ~reg_be))) | |
| (addr_hit[ 90] & (|(RV_DM_MEM_PERMIT[ 90] & ~reg_be))) | |
| (addr_hit[ 91] & (|(RV_DM_MEM_PERMIT[ 91] & ~reg_be))) | |
| (addr_hit[ 92] & (|(RV_DM_MEM_PERMIT[ 92] & ~reg_be))) | |
| (addr_hit[ 93] & (|(RV_DM_MEM_PERMIT[ 93] & ~reg_be))) | |
| (addr_hit[ 94] & (|(RV_DM_MEM_PERMIT[ 94] & ~reg_be))) | |
| (addr_hit[ 95] & (|(RV_DM_MEM_PERMIT[ 95] & ~reg_be))) | |
| (addr_hit[ 96] & (|(RV_DM_MEM_PERMIT[ 96] & ~reg_be))) | |
| (addr_hit[ 97] & (|(RV_DM_MEM_PERMIT[ 97] & ~reg_be))) | |
| (addr_hit[ 98] & (|(RV_DM_MEM_PERMIT[ 98] & ~reg_be))) | |
| (addr_hit[ 99] & (|(RV_DM_MEM_PERMIT[ 99] & ~reg_be))) | |
| (addr_hit[100] & (|(RV_DM_MEM_PERMIT[100] & ~reg_be))) | |
| (addr_hit[101] & (|(RV_DM_MEM_PERMIT[101] & ~reg_be))) | |
| (addr_hit[102] & (|(RV_DM_MEM_PERMIT[102] & ~reg_be))) | |
| (addr_hit[103] & (|(RV_DM_MEM_PERMIT[103] & ~reg_be))) | |
| (addr_hit[104] & (|(RV_DM_MEM_PERMIT[104] & ~reg_be))) | |
| (addr_hit[105] & (|(RV_DM_MEM_PERMIT[105] & ~reg_be))) | |
| (addr_hit[106] & (|(RV_DM_MEM_PERMIT[106] & ~reg_be))) | |
| (addr_hit[107] & (|(RV_DM_MEM_PERMIT[107] & ~reg_be))) | |
| (addr_hit[108] & (|(RV_DM_MEM_PERMIT[108] & ~reg_be))) | |
| (addr_hit[109] & (|(RV_DM_MEM_PERMIT[109] & ~reg_be))) | |
| (addr_hit[110] & (|(RV_DM_MEM_PERMIT[110] & ~reg_be))) | |
| (addr_hit[111] & (|(RV_DM_MEM_PERMIT[111] & ~reg_be))) | |
| (addr_hit[112] & (|(RV_DM_MEM_PERMIT[112] & ~reg_be))) | |
| (addr_hit[113] & (|(RV_DM_MEM_PERMIT[113] & ~reg_be))) | |
| (addr_hit[114] & (|(RV_DM_MEM_PERMIT[114] & ~reg_be))) | |
| (addr_hit[115] & (|(RV_DM_MEM_PERMIT[115] & ~reg_be))) | |
| (addr_hit[116] & (|(RV_DM_MEM_PERMIT[116] & ~reg_be))) | |
| (addr_hit[117] & (|(RV_DM_MEM_PERMIT[117] & ~reg_be))) | |
| (addr_hit[118] & (|(RV_DM_MEM_PERMIT[118] & ~reg_be))) | |
| (addr_hit[119] & (|(RV_DM_MEM_PERMIT[119] & ~reg_be))) | |
| (addr_hit[120] & (|(RV_DM_MEM_PERMIT[120] & ~reg_be))) | |
| (addr_hit[121] & (|(RV_DM_MEM_PERMIT[121] & ~reg_be))) | |
| (addr_hit[122] & (|(RV_DM_MEM_PERMIT[122] & ~reg_be))) | |
| (addr_hit[123] & (|(RV_DM_MEM_PERMIT[123] & ~reg_be))) | |
| (addr_hit[124] & (|(RV_DM_MEM_PERMIT[124] & ~reg_be))) | |
| (addr_hit[125] & (|(RV_DM_MEM_PERMIT[125] & ~reg_be))) | |
| (addr_hit[126] & (|(RV_DM_MEM_PERMIT[126] & ~reg_be))) | |
| (addr_hit[127] & (|(RV_DM_MEM_PERMIT[127] & ~reg_be))) | |
| (addr_hit[128] & (|(RV_DM_MEM_PERMIT[128] & ~reg_be))) | |
| (addr_hit[129] & (|(RV_DM_MEM_PERMIT[129] & ~reg_be))) | |
| (addr_hit[130] & (|(RV_DM_MEM_PERMIT[130] & ~reg_be))) | |
| (addr_hit[131] & (|(RV_DM_MEM_PERMIT[131] & ~reg_be))) | |
| (addr_hit[132] & (|(RV_DM_MEM_PERMIT[132] & ~reg_be))) | |
| (addr_hit[133] & (|(RV_DM_MEM_PERMIT[133] & ~reg_be))) | |
| (addr_hit[134] & (|(RV_DM_MEM_PERMIT[134] & ~reg_be))) | |
| (addr_hit[135] & (|(RV_DM_MEM_PERMIT[135] & ~reg_be))) | |
| (addr_hit[136] & (|(RV_DM_MEM_PERMIT[136] & ~reg_be))) | |
| (addr_hit[137] & (|(RV_DM_MEM_PERMIT[137] & ~reg_be))) | |
| (addr_hit[138] & (|(RV_DM_MEM_PERMIT[138] & ~reg_be))) | |
| (addr_hit[139] & (|(RV_DM_MEM_PERMIT[139] & ~reg_be))) | |
| (addr_hit[140] & (|(RV_DM_MEM_PERMIT[140] & ~reg_be))) | |
| (addr_hit[141] & (|(RV_DM_MEM_PERMIT[141] & ~reg_be))) | |
| (addr_hit[142] & (|(RV_DM_MEM_PERMIT[142] & ~reg_be))) | |
| (addr_hit[143] & (|(RV_DM_MEM_PERMIT[143] & ~reg_be))) | |
| (addr_hit[144] & (|(RV_DM_MEM_PERMIT[144] & ~reg_be))) | |
| (addr_hit[145] & (|(RV_DM_MEM_PERMIT[145] & ~reg_be))) | |
| (addr_hit[146] & (|(RV_DM_MEM_PERMIT[146] & ~reg_be))) | |
| (addr_hit[147] & (|(RV_DM_MEM_PERMIT[147] & ~reg_be))) | |
| (addr_hit[148] & (|(RV_DM_MEM_PERMIT[148] & ~reg_be))) | |
| (addr_hit[149] & (|(RV_DM_MEM_PERMIT[149] & ~reg_be))) | |
| (addr_hit[150] & (|(RV_DM_MEM_PERMIT[150] & ~reg_be))) | |
| (addr_hit[151] & (|(RV_DM_MEM_PERMIT[151] & ~reg_be))) | |
| (addr_hit[152] & (|(RV_DM_MEM_PERMIT[152] & ~reg_be))) | |
| (addr_hit[153] & (|(RV_DM_MEM_PERMIT[153] & ~reg_be))) | |
| (addr_hit[154] & (|(RV_DM_MEM_PERMIT[154] & ~reg_be))) | |
| (addr_hit[155] & (|(RV_DM_MEM_PERMIT[155] & ~reg_be))) | |
| (addr_hit[156] & (|(RV_DM_MEM_PERMIT[156] & ~reg_be))) | |
| (addr_hit[157] & (|(RV_DM_MEM_PERMIT[157] & ~reg_be))) | |
| (addr_hit[158] & (|(RV_DM_MEM_PERMIT[158] & ~reg_be))) | |
| (addr_hit[159] & (|(RV_DM_MEM_PERMIT[159] & ~reg_be))) | |
| (addr_hit[160] & (|(RV_DM_MEM_PERMIT[160] & ~reg_be))) | |
| (addr_hit[161] & (|(RV_DM_MEM_PERMIT[161] & ~reg_be))) | |
| (addr_hit[162] & (|(RV_DM_MEM_PERMIT[162] & ~reg_be))) | |
| (addr_hit[163] & (|(RV_DM_MEM_PERMIT[163] & ~reg_be))) | |
| (addr_hit[164] & (|(RV_DM_MEM_PERMIT[164] & ~reg_be))) | |
| (addr_hit[165] & (|(RV_DM_MEM_PERMIT[165] & ~reg_be))) | |
| (addr_hit[166] & (|(RV_DM_MEM_PERMIT[166] & ~reg_be))) | |
| (addr_hit[167] & (|(RV_DM_MEM_PERMIT[167] & ~reg_be))) | |
| (addr_hit[168] & (|(RV_DM_MEM_PERMIT[168] & ~reg_be))) | |
| (addr_hit[169] & (|(RV_DM_MEM_PERMIT[169] & ~reg_be))) | |
| (addr_hit[170] & (|(RV_DM_MEM_PERMIT[170] & ~reg_be))) | |
| (addr_hit[171] & (|(RV_DM_MEM_PERMIT[171] & ~reg_be))) | |
| (addr_hit[172] & (|(RV_DM_MEM_PERMIT[172] & ~reg_be))) | |
| (addr_hit[173] & (|(RV_DM_MEM_PERMIT[173] & ~reg_be))) | |
| (addr_hit[174] & (|(RV_DM_MEM_PERMIT[174] & ~reg_be))) | |
| (addr_hit[175] & (|(RV_DM_MEM_PERMIT[175] & ~reg_be))) | |
| (addr_hit[176] & (|(RV_DM_MEM_PERMIT[176] & ~reg_be))) | |
| (addr_hit[177] & (|(RV_DM_MEM_PERMIT[177] & ~reg_be))) | |
| (addr_hit[178] & (|(RV_DM_MEM_PERMIT[178] & ~reg_be))) | |
| (addr_hit[179] & (|(RV_DM_MEM_PERMIT[179] & ~reg_be))) | |
| (addr_hit[180] & (|(RV_DM_MEM_PERMIT[180] & ~reg_be))) | |
| (addr_hit[181] & (|(RV_DM_MEM_PERMIT[181] & ~reg_be))) | |
| (addr_hit[182] & (|(RV_DM_MEM_PERMIT[182] & ~reg_be))) | |
| (addr_hit[183] & (|(RV_DM_MEM_PERMIT[183] & ~reg_be))) | |
| (addr_hit[184] & (|(RV_DM_MEM_PERMIT[184] & ~reg_be))) | |
| (addr_hit[185] & (|(RV_DM_MEM_PERMIT[185] & ~reg_be))) | |
| (addr_hit[186] & (|(RV_DM_MEM_PERMIT[186] & ~reg_be))) | |
| (addr_hit[187] & (|(RV_DM_MEM_PERMIT[187] & ~reg_be))) | |
| (addr_hit[188] & (|(RV_DM_MEM_PERMIT[188] & ~reg_be))) | |
| (addr_hit[189] & (|(RV_DM_MEM_PERMIT[189] & ~reg_be))) | |
| (addr_hit[190] & (|(RV_DM_MEM_PERMIT[190] & ~reg_be))) | |
| (addr_hit[191] & (|(RV_DM_MEM_PERMIT[191] & ~reg_be))) | |
| (addr_hit[192] & (|(RV_DM_MEM_PERMIT[192] & ~reg_be))) | |
| (addr_hit[193] & (|(RV_DM_MEM_PERMIT[193] & ~reg_be))) | |
| (addr_hit[194] & (|(RV_DM_MEM_PERMIT[194] & ~reg_be))) | |
| (addr_hit[195] & (|(RV_DM_MEM_PERMIT[195] & ~reg_be))) | |
| (addr_hit[196] & (|(RV_DM_MEM_PERMIT[196] & ~reg_be))) | |
| (addr_hit[197] & (|(RV_DM_MEM_PERMIT[197] & ~reg_be))) | |
| (addr_hit[198] & (|(RV_DM_MEM_PERMIT[198] & ~reg_be))) | |
| (addr_hit[199] & (|(RV_DM_MEM_PERMIT[199] & ~reg_be))) | |
| (addr_hit[200] & (|(RV_DM_MEM_PERMIT[200] & ~reg_be))) | |
| (addr_hit[201] & (|(RV_DM_MEM_PERMIT[201] & ~reg_be))) | |
| (addr_hit[202] & (|(RV_DM_MEM_PERMIT[202] & ~reg_be))) | |
| (addr_hit[203] & (|(RV_DM_MEM_PERMIT[203] & ~reg_be))) | |
| (addr_hit[204] & (|(RV_DM_MEM_PERMIT[204] & ~reg_be))) | |
| (addr_hit[205] & (|(RV_DM_MEM_PERMIT[205] & ~reg_be))) | |
| (addr_hit[206] & (|(RV_DM_MEM_PERMIT[206] & ~reg_be))) | |
| (addr_hit[207] & (|(RV_DM_MEM_PERMIT[207] & ~reg_be))) | |
| (addr_hit[208] & (|(RV_DM_MEM_PERMIT[208] & ~reg_be))) | |
| (addr_hit[209] & (|(RV_DM_MEM_PERMIT[209] & ~reg_be))) | |
| (addr_hit[210] & (|(RV_DM_MEM_PERMIT[210] & ~reg_be))) | |
| (addr_hit[211] & (|(RV_DM_MEM_PERMIT[211] & ~reg_be))) | |
| (addr_hit[212] & (|(RV_DM_MEM_PERMIT[212] & ~reg_be))) | |
| (addr_hit[213] & (|(RV_DM_MEM_PERMIT[213] & ~reg_be))) | |
| (addr_hit[214] & (|(RV_DM_MEM_PERMIT[214] & ~reg_be))) | |
| (addr_hit[215] & (|(RV_DM_MEM_PERMIT[215] & ~reg_be))) | |
| (addr_hit[216] & (|(RV_DM_MEM_PERMIT[216] & ~reg_be))) | |
| (addr_hit[217] & (|(RV_DM_MEM_PERMIT[217] & ~reg_be))) | |
| (addr_hit[218] & (|(RV_DM_MEM_PERMIT[218] & ~reg_be))) | |
| (addr_hit[219] & (|(RV_DM_MEM_PERMIT[219] & ~reg_be))) | |
| (addr_hit[220] & (|(RV_DM_MEM_PERMIT[220] & ~reg_be))) | |
| (addr_hit[221] & (|(RV_DM_MEM_PERMIT[221] & ~reg_be))) | |
| (addr_hit[222] & (|(RV_DM_MEM_PERMIT[222] & ~reg_be))) | |
| (addr_hit[223] & (|(RV_DM_MEM_PERMIT[223] & ~reg_be))) | |
| (addr_hit[224] & (|(RV_DM_MEM_PERMIT[224] & ~reg_be))) | |
| (addr_hit[225] & (|(RV_DM_MEM_PERMIT[225] & ~reg_be))) | |
| (addr_hit[226] & (|(RV_DM_MEM_PERMIT[226] & ~reg_be))) | |
| (addr_hit[227] & (|(RV_DM_MEM_PERMIT[227] & ~reg_be))) | |
| (addr_hit[228] & (|(RV_DM_MEM_PERMIT[228] & ~reg_be))) | |
| (addr_hit[229] & (|(RV_DM_MEM_PERMIT[229] & ~reg_be))) | |
| (addr_hit[230] & (|(RV_DM_MEM_PERMIT[230] & ~reg_be))) | |
| (addr_hit[231] & (|(RV_DM_MEM_PERMIT[231] & ~reg_be))) | |
| (addr_hit[232] & (|(RV_DM_MEM_PERMIT[232] & ~reg_be))) | |
| (addr_hit[233] & (|(RV_DM_MEM_PERMIT[233] & ~reg_be))) | |
| (addr_hit[234] & (|(RV_DM_MEM_PERMIT[234] & ~reg_be))) | |
| (addr_hit[235] & (|(RV_DM_MEM_PERMIT[235] & ~reg_be))) | |
| (addr_hit[236] & (|(RV_DM_MEM_PERMIT[236] & ~reg_be))) | |
| (addr_hit[237] & (|(RV_DM_MEM_PERMIT[237] & ~reg_be))) | |
| (addr_hit[238] & (|(RV_DM_MEM_PERMIT[238] & ~reg_be))) | |
| (addr_hit[239] & (|(RV_DM_MEM_PERMIT[239] & ~reg_be))) | |
| (addr_hit[240] & (|(RV_DM_MEM_PERMIT[240] & ~reg_be))) | |
| (addr_hit[241] & (|(RV_DM_MEM_PERMIT[241] & ~reg_be))) | |
| (addr_hit[242] & (|(RV_DM_MEM_PERMIT[242] & ~reg_be))) | |
| (addr_hit[243] & (|(RV_DM_MEM_PERMIT[243] & ~reg_be))) | |
| (addr_hit[244] & (|(RV_DM_MEM_PERMIT[244] & ~reg_be))) | |
| (addr_hit[245] & (|(RV_DM_MEM_PERMIT[245] & ~reg_be))) | |
| (addr_hit[246] & (|(RV_DM_MEM_PERMIT[246] & ~reg_be))) | |
| (addr_hit[247] & (|(RV_DM_MEM_PERMIT[247] & ~reg_be))) | |
| (addr_hit[248] & (|(RV_DM_MEM_PERMIT[248] & ~reg_be))) | |
| (addr_hit[249] & (|(RV_DM_MEM_PERMIT[249] & ~reg_be))) | |
| (addr_hit[250] & (|(RV_DM_MEM_PERMIT[250] & ~reg_be))) | |
| (addr_hit[251] & (|(RV_DM_MEM_PERMIT[251] & ~reg_be))) | |
| (addr_hit[252] & (|(RV_DM_MEM_PERMIT[252] & ~reg_be))) | |
| (addr_hit[253] & (|(RV_DM_MEM_PERMIT[253] & ~reg_be))) | |
| (addr_hit[254] & (|(RV_DM_MEM_PERMIT[254] & ~reg_be))) | |
| (addr_hit[255] & (|(RV_DM_MEM_PERMIT[255] & ~reg_be))) | |
| (addr_hit[256] & (|(RV_DM_MEM_PERMIT[256] & ~reg_be))) | |
| (addr_hit[257] & (|(RV_DM_MEM_PERMIT[257] & ~reg_be))) | |
| (addr_hit[258] & (|(RV_DM_MEM_PERMIT[258] & ~reg_be))) | |
| (addr_hit[259] & (|(RV_DM_MEM_PERMIT[259] & ~reg_be))) | |
| (addr_hit[260] & (|(RV_DM_MEM_PERMIT[260] & ~reg_be))) | |
| (addr_hit[261] & (|(RV_DM_MEM_PERMIT[261] & ~reg_be))) | |
| (addr_hit[262] & (|(RV_DM_MEM_PERMIT[262] & ~reg_be))) | |
| (addr_hit[263] & (|(RV_DM_MEM_PERMIT[263] & ~reg_be))) | |
| (addr_hit[264] & (|(RV_DM_MEM_PERMIT[264] & ~reg_be))) | |
| (addr_hit[265] & (|(RV_DM_MEM_PERMIT[265] & ~reg_be))) | |
| (addr_hit[266] & (|(RV_DM_MEM_PERMIT[266] & ~reg_be))) | |
| (addr_hit[267] & (|(RV_DM_MEM_PERMIT[267] & ~reg_be))) | |
| (addr_hit[268] & (|(RV_DM_MEM_PERMIT[268] & ~reg_be))) | |
| (addr_hit[269] & (|(RV_DM_MEM_PERMIT[269] & ~reg_be))) | |
| (addr_hit[270] & (|(RV_DM_MEM_PERMIT[270] & ~reg_be))) | |
| (addr_hit[271] & (|(RV_DM_MEM_PERMIT[271] & ~reg_be))) | |
| (addr_hit[272] & (|(RV_DM_MEM_PERMIT[272] & ~reg_be))) | |
| (addr_hit[273] & (|(RV_DM_MEM_PERMIT[273] & ~reg_be))) | |
| (addr_hit[274] & (|(RV_DM_MEM_PERMIT[274] & ~reg_be))) | |
| (addr_hit[275] & (|(RV_DM_MEM_PERMIT[275] & ~reg_be))) | |
| (addr_hit[276] & (|(RV_DM_MEM_PERMIT[276] & ~reg_be))) | |
| (addr_hit[277] & (|(RV_DM_MEM_PERMIT[277] & ~reg_be))) | |
| (addr_hit[278] & (|(RV_DM_MEM_PERMIT[278] & ~reg_be))) | |
| (addr_hit[279] & (|(RV_DM_MEM_PERMIT[279] & ~reg_be))) | |
| (addr_hit[280] & (|(RV_DM_MEM_PERMIT[280] & ~reg_be))))); |
| end |
| |
| // Generate write-enables |
| assign halted_we = addr_hit[0] & reg_we & !reg_error; |
| |
| assign halted_wd = reg_wdata[0]; |
| assign going_we = addr_hit[1] & reg_we & !reg_error; |
| |
| assign going_wd = reg_wdata[0]; |
| assign resuming_we = addr_hit[2] & reg_we & !reg_error; |
| |
| assign resuming_wd = reg_wdata[0]; |
| assign exception_we = addr_hit[3] & reg_we & !reg_error; |
| |
| assign exception_wd = reg_wdata[0]; |
| assign dataaddr_0_we = addr_hit[23] & reg_we & !reg_error; |
| |
| assign dataaddr_0_wd = reg_wdata[31:0]; |
| assign dataaddr_1_we = addr_hit[24] & reg_we & !reg_error; |
| |
| assign dataaddr_1_wd = reg_wdata[31:0]; |
| |
| // Assign write-enables to checker logic vector. |
| always_comb begin |
| reg_we_check = '0; |
| reg_we_check[0] = halted_we; |
| reg_we_check[1] = going_we; |
| reg_we_check[2] = resuming_we; |
| reg_we_check[3] = exception_we; |
| reg_we_check[4] = 1'b0; |
| reg_we_check[5] = 1'b0; |
| reg_we_check[6] = 1'b0; |
| reg_we_check[7] = 1'b0; |
| reg_we_check[8] = 1'b0; |
| reg_we_check[9] = 1'b0; |
| reg_we_check[10] = 1'b0; |
| reg_we_check[11] = 1'b0; |
| reg_we_check[12] = 1'b0; |
| reg_we_check[13] = 1'b0; |
| reg_we_check[14] = 1'b0; |
| reg_we_check[15] = 1'b0; |
| reg_we_check[16] = 1'b0; |
| reg_we_check[17] = 1'b0; |
| reg_we_check[18] = 1'b0; |
| reg_we_check[19] = 1'b0; |
| reg_we_check[20] = 1'b0; |
| reg_we_check[21] = 1'b0; |
| reg_we_check[22] = 1'b0; |
| reg_we_check[23] = dataaddr_0_we; |
| reg_we_check[24] = dataaddr_1_we; |
| reg_we_check[25] = 1'b0; |
| reg_we_check[26] = 1'b0; |
| reg_we_check[27] = 1'b0; |
| reg_we_check[28] = 1'b0; |
| reg_we_check[29] = 1'b0; |
| reg_we_check[30] = 1'b0; |
| reg_we_check[31] = 1'b0; |
| reg_we_check[32] = 1'b0; |
| reg_we_check[33] = 1'b0; |
| reg_we_check[34] = 1'b0; |
| reg_we_check[35] = 1'b0; |
| reg_we_check[36] = 1'b0; |
| reg_we_check[37] = 1'b0; |
| reg_we_check[38] = 1'b0; |
| reg_we_check[39] = 1'b0; |
| reg_we_check[40] = 1'b0; |
| reg_we_check[41] = 1'b0; |
| reg_we_check[42] = 1'b0; |
| reg_we_check[43] = 1'b0; |
| reg_we_check[44] = 1'b0; |
| reg_we_check[45] = 1'b0; |
| reg_we_check[46] = 1'b0; |
| reg_we_check[47] = 1'b0; |
| reg_we_check[48] = 1'b0; |
| reg_we_check[49] = 1'b0; |
| reg_we_check[50] = 1'b0; |
| reg_we_check[51] = 1'b0; |
| reg_we_check[52] = 1'b0; |
| reg_we_check[53] = 1'b0; |
| reg_we_check[54] = 1'b0; |
| reg_we_check[55] = 1'b0; |
| reg_we_check[56] = 1'b0; |
| reg_we_check[57] = 1'b0; |
| reg_we_check[58] = 1'b0; |
| reg_we_check[59] = 1'b0; |
| reg_we_check[60] = 1'b0; |
| reg_we_check[61] = 1'b0; |
| reg_we_check[62] = 1'b0; |
| reg_we_check[63] = 1'b0; |
| reg_we_check[64] = 1'b0; |
| reg_we_check[65] = 1'b0; |
| reg_we_check[66] = 1'b0; |
| reg_we_check[67] = 1'b0; |
| reg_we_check[68] = 1'b0; |
| reg_we_check[69] = 1'b0; |
| reg_we_check[70] = 1'b0; |
| reg_we_check[71] = 1'b0; |
| reg_we_check[72] = 1'b0; |
| reg_we_check[73] = 1'b0; |
| reg_we_check[74] = 1'b0; |
| reg_we_check[75] = 1'b0; |
| reg_we_check[76] = 1'b0; |
| reg_we_check[77] = 1'b0; |
| reg_we_check[78] = 1'b0; |
| reg_we_check[79] = 1'b0; |
| reg_we_check[80] = 1'b0; |
| reg_we_check[81] = 1'b0; |
| reg_we_check[82] = 1'b0; |
| reg_we_check[83] = 1'b0; |
| reg_we_check[84] = 1'b0; |
| reg_we_check[85] = 1'b0; |
| reg_we_check[86] = 1'b0; |
| reg_we_check[87] = 1'b0; |
| reg_we_check[88] = 1'b0; |
| reg_we_check[89] = 1'b0; |
| reg_we_check[90] = 1'b0; |
| reg_we_check[91] = 1'b0; |
| reg_we_check[92] = 1'b0; |
| reg_we_check[93] = 1'b0; |
| reg_we_check[94] = 1'b0; |
| reg_we_check[95] = 1'b0; |
| reg_we_check[96] = 1'b0; |
| reg_we_check[97] = 1'b0; |
| reg_we_check[98] = 1'b0; |
| reg_we_check[99] = 1'b0; |
| reg_we_check[100] = 1'b0; |
| reg_we_check[101] = 1'b0; |
| reg_we_check[102] = 1'b0; |
| reg_we_check[103] = 1'b0; |
| reg_we_check[104] = 1'b0; |
| reg_we_check[105] = 1'b0; |
| reg_we_check[106] = 1'b0; |
| reg_we_check[107] = 1'b0; |
| reg_we_check[108] = 1'b0; |
| reg_we_check[109] = 1'b0; |
| reg_we_check[110] = 1'b0; |
| reg_we_check[111] = 1'b0; |
| reg_we_check[112] = 1'b0; |
| reg_we_check[113] = 1'b0; |
| reg_we_check[114] = 1'b0; |
| reg_we_check[115] = 1'b0; |
| reg_we_check[116] = 1'b0; |
| reg_we_check[117] = 1'b0; |
| reg_we_check[118] = 1'b0; |
| reg_we_check[119] = 1'b0; |
| reg_we_check[120] = 1'b0; |
| reg_we_check[121] = 1'b0; |
| reg_we_check[122] = 1'b0; |
| reg_we_check[123] = 1'b0; |
| reg_we_check[124] = 1'b0; |
| reg_we_check[125] = 1'b0; |
| reg_we_check[126] = 1'b0; |
| reg_we_check[127] = 1'b0; |
| reg_we_check[128] = 1'b0; |
| reg_we_check[129] = 1'b0; |
| reg_we_check[130] = 1'b0; |
| reg_we_check[131] = 1'b0; |
| reg_we_check[132] = 1'b0; |
| reg_we_check[133] = 1'b0; |
| reg_we_check[134] = 1'b0; |
| reg_we_check[135] = 1'b0; |
| reg_we_check[136] = 1'b0; |
| reg_we_check[137] = 1'b0; |
| reg_we_check[138] = 1'b0; |
| reg_we_check[139] = 1'b0; |
| reg_we_check[140] = 1'b0; |
| reg_we_check[141] = 1'b0; |
| reg_we_check[142] = 1'b0; |
| reg_we_check[143] = 1'b0; |
| reg_we_check[144] = 1'b0; |
| reg_we_check[145] = 1'b0; |
| reg_we_check[146] = 1'b0; |
| reg_we_check[147] = 1'b0; |
| reg_we_check[148] = 1'b0; |
| reg_we_check[149] = 1'b0; |
| reg_we_check[150] = 1'b0; |
| reg_we_check[151] = 1'b0; |
| reg_we_check[152] = 1'b0; |
| reg_we_check[153] = 1'b0; |
| reg_we_check[154] = 1'b0; |
| reg_we_check[155] = 1'b0; |
| reg_we_check[156] = 1'b0; |
| reg_we_check[157] = 1'b0; |
| reg_we_check[158] = 1'b0; |
| reg_we_check[159] = 1'b0; |
| reg_we_check[160] = 1'b0; |
| reg_we_check[161] = 1'b0; |
| reg_we_check[162] = 1'b0; |
| reg_we_check[163] = 1'b0; |
| reg_we_check[164] = 1'b0; |
| reg_we_check[165] = 1'b0; |
| reg_we_check[166] = 1'b0; |
| reg_we_check[167] = 1'b0; |
| reg_we_check[168] = 1'b0; |
| reg_we_check[169] = 1'b0; |
| reg_we_check[170] = 1'b0; |
| reg_we_check[171] = 1'b0; |
| reg_we_check[172] = 1'b0; |
| reg_we_check[173] = 1'b0; |
| reg_we_check[174] = 1'b0; |
| reg_we_check[175] = 1'b0; |
| reg_we_check[176] = 1'b0; |
| reg_we_check[177] = 1'b0; |
| reg_we_check[178] = 1'b0; |
| reg_we_check[179] = 1'b0; |
| reg_we_check[180] = 1'b0; |
| reg_we_check[181] = 1'b0; |
| reg_we_check[182] = 1'b0; |
| reg_we_check[183] = 1'b0; |
| reg_we_check[184] = 1'b0; |
| reg_we_check[185] = 1'b0; |
| reg_we_check[186] = 1'b0; |
| reg_we_check[187] = 1'b0; |
| reg_we_check[188] = 1'b0; |
| reg_we_check[189] = 1'b0; |
| reg_we_check[190] = 1'b0; |
| reg_we_check[191] = 1'b0; |
| reg_we_check[192] = 1'b0; |
| reg_we_check[193] = 1'b0; |
| reg_we_check[194] = 1'b0; |
| reg_we_check[195] = 1'b0; |
| reg_we_check[196] = 1'b0; |
| reg_we_check[197] = 1'b0; |
| reg_we_check[198] = 1'b0; |
| reg_we_check[199] = 1'b0; |
| reg_we_check[200] = 1'b0; |
| reg_we_check[201] = 1'b0; |
| reg_we_check[202] = 1'b0; |
| reg_we_check[203] = 1'b0; |
| reg_we_check[204] = 1'b0; |
| reg_we_check[205] = 1'b0; |
| reg_we_check[206] = 1'b0; |
| reg_we_check[207] = 1'b0; |
| reg_we_check[208] = 1'b0; |
| reg_we_check[209] = 1'b0; |
| reg_we_check[210] = 1'b0; |
| reg_we_check[211] = 1'b0; |
| reg_we_check[212] = 1'b0; |
| reg_we_check[213] = 1'b0; |
| reg_we_check[214] = 1'b0; |
| reg_we_check[215] = 1'b0; |
| reg_we_check[216] = 1'b0; |
| reg_we_check[217] = 1'b0; |
| reg_we_check[218] = 1'b0; |
| reg_we_check[219] = 1'b0; |
| reg_we_check[220] = 1'b0; |
| reg_we_check[221] = 1'b0; |
| reg_we_check[222] = 1'b0; |
| reg_we_check[223] = 1'b0; |
| reg_we_check[224] = 1'b0; |
| reg_we_check[225] = 1'b0; |
| reg_we_check[226] = 1'b0; |
| reg_we_check[227] = 1'b0; |
| reg_we_check[228] = 1'b0; |
| reg_we_check[229] = 1'b0; |
| reg_we_check[230] = 1'b0; |
| reg_we_check[231] = 1'b0; |
| reg_we_check[232] = 1'b0; |
| reg_we_check[233] = 1'b0; |
| reg_we_check[234] = 1'b0; |
| reg_we_check[235] = 1'b0; |
| reg_we_check[236] = 1'b0; |
| reg_we_check[237] = 1'b0; |
| reg_we_check[238] = 1'b0; |
| reg_we_check[239] = 1'b0; |
| reg_we_check[240] = 1'b0; |
| reg_we_check[241] = 1'b0; |
| reg_we_check[242] = 1'b0; |
| reg_we_check[243] = 1'b0; |
| reg_we_check[244] = 1'b0; |
| reg_we_check[245] = 1'b0; |
| reg_we_check[246] = 1'b0; |
| reg_we_check[247] = 1'b0; |
| reg_we_check[248] = 1'b0; |
| reg_we_check[249] = 1'b0; |
| reg_we_check[250] = 1'b0; |
| reg_we_check[251] = 1'b0; |
| reg_we_check[252] = 1'b0; |
| reg_we_check[253] = 1'b0; |
| reg_we_check[254] = 1'b0; |
| reg_we_check[255] = 1'b0; |
| reg_we_check[256] = 1'b0; |
| reg_we_check[257] = 1'b0; |
| reg_we_check[258] = 1'b0; |
| reg_we_check[259] = 1'b0; |
| reg_we_check[260] = 1'b0; |
| reg_we_check[261] = 1'b0; |
| reg_we_check[262] = 1'b0; |
| reg_we_check[263] = 1'b0; |
| reg_we_check[264] = 1'b0; |
| reg_we_check[265] = 1'b0; |
| reg_we_check[266] = 1'b0; |
| reg_we_check[267] = 1'b0; |
| reg_we_check[268] = 1'b0; |
| reg_we_check[269] = 1'b0; |
| reg_we_check[270] = 1'b0; |
| reg_we_check[271] = 1'b0; |
| reg_we_check[272] = 1'b0; |
| reg_we_check[273] = 1'b0; |
| reg_we_check[274] = 1'b0; |
| reg_we_check[275] = 1'b0; |
| reg_we_check[276] = 1'b0; |
| reg_we_check[277] = 1'b0; |
| reg_we_check[278] = 1'b0; |
| reg_we_check[279] = 1'b0; |
| reg_we_check[280] = 1'b0; |
| end |
| |
| // Read data return |
| always_comb begin |
| reg_rdata_next = '0; |
| unique case (1'b1) |
| addr_hit[0]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[1]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[2]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[3]: begin |
| reg_rdata_next[0] = '0; |
| end |
| |
| addr_hit[4]: begin |
| reg_rdata_next[31:0] = whereto_qs; |
| end |
| |
| addr_hit[5]: begin |
| reg_rdata_next[31:0] = abstractcmd_0_qs; |
| end |
| |
| addr_hit[6]: begin |
| reg_rdata_next[31:0] = abstractcmd_1_qs; |
| end |
| |
| addr_hit[7]: begin |
| reg_rdata_next[31:0] = abstractcmd_2_qs; |
| end |
| |
| addr_hit[8]: begin |
| reg_rdata_next[31:0] = abstractcmd_3_qs; |
| end |
| |
| addr_hit[9]: begin |
| reg_rdata_next[31:0] = abstractcmd_4_qs; |
| end |
| |
| addr_hit[10]: begin |
| reg_rdata_next[31:0] = abstractcmd_5_qs; |
| end |
| |
| addr_hit[11]: begin |
| reg_rdata_next[31:0] = abstractcmd_6_qs; |
| end |
| |
| addr_hit[12]: begin |
| reg_rdata_next[31:0] = abstractcmd_7_qs; |
| end |
| |
| addr_hit[13]: begin |
| reg_rdata_next[31:0] = abstractcmd_8_qs; |
| end |
| |
| addr_hit[14]: begin |
| reg_rdata_next[31:0] = abstractcmd_9_qs; |
| end |
| |
| addr_hit[15]: begin |
| reg_rdata_next[31:0] = program_buffer_0_qs; |
| end |
| |
| addr_hit[16]: begin |
| reg_rdata_next[31:0] = program_buffer_1_qs; |
| end |
| |
| addr_hit[17]: begin |
| reg_rdata_next[31:0] = program_buffer_2_qs; |
| end |
| |
| addr_hit[18]: begin |
| reg_rdata_next[31:0] = program_buffer_3_qs; |
| end |
| |
| addr_hit[19]: begin |
| reg_rdata_next[31:0] = program_buffer_4_qs; |
| end |
| |
| addr_hit[20]: begin |
| reg_rdata_next[31:0] = program_buffer_5_qs; |
| end |
| |
| addr_hit[21]: begin |
| reg_rdata_next[31:0] = program_buffer_6_qs; |
| end |
| |
| addr_hit[22]: begin |
| reg_rdata_next[31:0] = program_buffer_7_qs; |
| end |
| |
| addr_hit[23]: begin |
| reg_rdata_next[31:0] = dataaddr_0_qs; |
| end |
| |
| addr_hit[24]: begin |
| reg_rdata_next[31:0] = dataaddr_1_qs; |
| end |
| |
| addr_hit[25]: begin |
| reg_rdata_next[31:0] = flags_0_qs; |
| end |
| |
| addr_hit[26]: begin |
| reg_rdata_next[31:0] = flags_1_qs; |
| end |
| |
| addr_hit[27]: begin |
| reg_rdata_next[31:0] = flags_2_qs; |
| end |
| |
| addr_hit[28]: begin |
| reg_rdata_next[31:0] = flags_3_qs; |
| end |
| |
| addr_hit[29]: begin |
| reg_rdata_next[31:0] = flags_4_qs; |
| end |
| |
| addr_hit[30]: begin |
| reg_rdata_next[31:0] = flags_5_qs; |
| end |
| |
| addr_hit[31]: begin |
| reg_rdata_next[31:0] = flags_6_qs; |
| end |
| |
| addr_hit[32]: begin |
| reg_rdata_next[31:0] = flags_7_qs; |
| end |
| |
| addr_hit[33]: begin |
| reg_rdata_next[31:0] = flags_8_qs; |
| end |
| |
| addr_hit[34]: begin |
| reg_rdata_next[31:0] = flags_9_qs; |
| end |
| |
| addr_hit[35]: begin |
| reg_rdata_next[31:0] = flags_10_qs; |
| end |
| |
| addr_hit[36]: begin |
| reg_rdata_next[31:0] = flags_11_qs; |
| end |
| |
| addr_hit[37]: begin |
| reg_rdata_next[31:0] = flags_12_qs; |
| end |
| |
| addr_hit[38]: begin |
| reg_rdata_next[31:0] = flags_13_qs; |
| end |
| |
| addr_hit[39]: begin |
| reg_rdata_next[31:0] = flags_14_qs; |
| end |
| |
| addr_hit[40]: begin |
| reg_rdata_next[31:0] = flags_15_qs; |
| end |
| |
| addr_hit[41]: begin |
| reg_rdata_next[31:0] = flags_16_qs; |
| end |
| |
| addr_hit[42]: begin |
| reg_rdata_next[31:0] = flags_17_qs; |
| end |
| |
| addr_hit[43]: begin |
| reg_rdata_next[31:0] = flags_18_qs; |
| end |
| |
| addr_hit[44]: begin |
| reg_rdata_next[31:0] = flags_19_qs; |
| end |
| |
| addr_hit[45]: begin |
| reg_rdata_next[31:0] = flags_20_qs; |
| end |
| |
| addr_hit[46]: begin |
| reg_rdata_next[31:0] = flags_21_qs; |
| end |
| |
| addr_hit[47]: begin |
| reg_rdata_next[31:0] = flags_22_qs; |
| end |
| |
| addr_hit[48]: begin |
| reg_rdata_next[31:0] = flags_23_qs; |
| end |
| |
| addr_hit[49]: begin |
| reg_rdata_next[31:0] = flags_24_qs; |
| end |
| |
| addr_hit[50]: begin |
| reg_rdata_next[31:0] = flags_25_qs; |
| end |
| |
| addr_hit[51]: begin |
| reg_rdata_next[31:0] = flags_26_qs; |
| end |
| |
| addr_hit[52]: begin |
| reg_rdata_next[31:0] = flags_27_qs; |
| end |
| |
| addr_hit[53]: begin |
| reg_rdata_next[31:0] = flags_28_qs; |
| end |
| |
| addr_hit[54]: begin |
| reg_rdata_next[31:0] = flags_29_qs; |
| end |
| |
| addr_hit[55]: begin |
| reg_rdata_next[31:0] = flags_30_qs; |
| end |
| |
| addr_hit[56]: begin |
| reg_rdata_next[31:0] = flags_31_qs; |
| end |
| |
| addr_hit[57]: begin |
| reg_rdata_next[31:0] = flags_32_qs; |
| end |
| |
| addr_hit[58]: begin |
| reg_rdata_next[31:0] = flags_33_qs; |
| end |
| |
| addr_hit[59]: begin |
| reg_rdata_next[31:0] = flags_34_qs; |
| end |
| |
| addr_hit[60]: begin |
| reg_rdata_next[31:0] = flags_35_qs; |
| end |
| |
| addr_hit[61]: begin |
| reg_rdata_next[31:0] = flags_36_qs; |
| end |
| |
| addr_hit[62]: begin |
| reg_rdata_next[31:0] = flags_37_qs; |
| end |
| |
| addr_hit[63]: begin |
| reg_rdata_next[31:0] = flags_38_qs; |
| end |
| |
| addr_hit[64]: begin |
| reg_rdata_next[31:0] = flags_39_qs; |
| end |
| |
| addr_hit[65]: begin |
| reg_rdata_next[31:0] = flags_40_qs; |
| end |
| |
| addr_hit[66]: begin |
| reg_rdata_next[31:0] = flags_41_qs; |
| end |
| |
| addr_hit[67]: begin |
| reg_rdata_next[31:0] = flags_42_qs; |
| end |
| |
| addr_hit[68]: begin |
| reg_rdata_next[31:0] = flags_43_qs; |
| end |
| |
| addr_hit[69]: begin |
| reg_rdata_next[31:0] = flags_44_qs; |
| end |
| |
| addr_hit[70]: begin |
| reg_rdata_next[31:0] = flags_45_qs; |
| end |
| |
| addr_hit[71]: begin |
| reg_rdata_next[31:0] = flags_46_qs; |
| end |
| |
| addr_hit[72]: begin |
| reg_rdata_next[31:0] = flags_47_qs; |
| end |
| |
| addr_hit[73]: begin |
| reg_rdata_next[31:0] = flags_48_qs; |
| end |
| |
| addr_hit[74]: begin |
| reg_rdata_next[31:0] = flags_49_qs; |
| end |
| |
| addr_hit[75]: begin |
| reg_rdata_next[31:0] = flags_50_qs; |
| end |
| |
| addr_hit[76]: begin |
| reg_rdata_next[31:0] = flags_51_qs; |
| end |
| |
| addr_hit[77]: begin |
| reg_rdata_next[31:0] = flags_52_qs; |
| end |
| |
| addr_hit[78]: begin |
| reg_rdata_next[31:0] = flags_53_qs; |
| end |
| |
| addr_hit[79]: begin |
| reg_rdata_next[31:0] = flags_54_qs; |
| end |
| |
| addr_hit[80]: begin |
| reg_rdata_next[31:0] = flags_55_qs; |
| end |
| |
| addr_hit[81]: begin |
| reg_rdata_next[31:0] = flags_56_qs; |
| end |
| |
| addr_hit[82]: begin |
| reg_rdata_next[31:0] = flags_57_qs; |
| end |
| |
| addr_hit[83]: begin |
| reg_rdata_next[31:0] = flags_58_qs; |
| end |
| |
| addr_hit[84]: begin |
| reg_rdata_next[31:0] = flags_59_qs; |
| end |
| |
| addr_hit[85]: begin |
| reg_rdata_next[31:0] = flags_60_qs; |
| end |
| |
| addr_hit[86]: begin |
| reg_rdata_next[31:0] = flags_61_qs; |
| end |
| |
| addr_hit[87]: begin |
| reg_rdata_next[31:0] = flags_62_qs; |
| end |
| |
| addr_hit[88]: begin |
| reg_rdata_next[31:0] = flags_63_qs; |
| end |
| |
| addr_hit[89]: begin |
| reg_rdata_next[31:0] = flags_64_qs; |
| end |
| |
| addr_hit[90]: begin |
| reg_rdata_next[31:0] = flags_65_qs; |
| end |
| |
| addr_hit[91]: begin |
| reg_rdata_next[31:0] = flags_66_qs; |
| end |
| |
| addr_hit[92]: begin |
| reg_rdata_next[31:0] = flags_67_qs; |
| end |
| |
| addr_hit[93]: begin |
| reg_rdata_next[31:0] = flags_68_qs; |
| end |
| |
| addr_hit[94]: begin |
| reg_rdata_next[31:0] = flags_69_qs; |
| end |
| |
| addr_hit[95]: begin |
| reg_rdata_next[31:0] = flags_70_qs; |
| end |
| |
| addr_hit[96]: begin |
| reg_rdata_next[31:0] = flags_71_qs; |
| end |
| |
| addr_hit[97]: begin |
| reg_rdata_next[31:0] = flags_72_qs; |
| end |
| |
| addr_hit[98]: begin |
| reg_rdata_next[31:0] = flags_73_qs; |
| end |
| |
| addr_hit[99]: begin |
| reg_rdata_next[31:0] = flags_74_qs; |
| end |
| |
| addr_hit[100]: begin |
| reg_rdata_next[31:0] = flags_75_qs; |
| end |
| |
| addr_hit[101]: begin |
| reg_rdata_next[31:0] = flags_76_qs; |
| end |
| |
| addr_hit[102]: begin |
| reg_rdata_next[31:0] = flags_77_qs; |
| end |
| |
| addr_hit[103]: begin |
| reg_rdata_next[31:0] = flags_78_qs; |
| end |
| |
| addr_hit[104]: begin |
| reg_rdata_next[31:0] = flags_79_qs; |
| end |
| |
| addr_hit[105]: begin |
| reg_rdata_next[31:0] = flags_80_qs; |
| end |
| |
| addr_hit[106]: begin |
| reg_rdata_next[31:0] = flags_81_qs; |
| end |
| |
| addr_hit[107]: begin |
| reg_rdata_next[31:0] = flags_82_qs; |
| end |
| |
| addr_hit[108]: begin |
| reg_rdata_next[31:0] = flags_83_qs; |
| end |
| |
| addr_hit[109]: begin |
| reg_rdata_next[31:0] = flags_84_qs; |
| end |
| |
| addr_hit[110]: begin |
| reg_rdata_next[31:0] = flags_85_qs; |
| end |
| |
| addr_hit[111]: begin |
| reg_rdata_next[31:0] = flags_86_qs; |
| end |
| |
| addr_hit[112]: begin |
| reg_rdata_next[31:0] = flags_87_qs; |
| end |
| |
| addr_hit[113]: begin |
| reg_rdata_next[31:0] = flags_88_qs; |
| end |
| |
| addr_hit[114]: begin |
| reg_rdata_next[31:0] = flags_89_qs; |
| end |
| |
| addr_hit[115]: begin |
| reg_rdata_next[31:0] = flags_90_qs; |
| end |
| |
| addr_hit[116]: begin |
| reg_rdata_next[31:0] = flags_91_qs; |
| end |
| |
| addr_hit[117]: begin |
| reg_rdata_next[31:0] = flags_92_qs; |
| end |
| |
| addr_hit[118]: begin |
| reg_rdata_next[31:0] = flags_93_qs; |
| end |
| |
| addr_hit[119]: begin |
| reg_rdata_next[31:0] = flags_94_qs; |
| end |
| |
| addr_hit[120]: begin |
| reg_rdata_next[31:0] = flags_95_qs; |
| end |
| |
| addr_hit[121]: begin |
| reg_rdata_next[31:0] = flags_96_qs; |
| end |
| |
| addr_hit[122]: begin |
| reg_rdata_next[31:0] = flags_97_qs; |
| end |
| |
| addr_hit[123]: begin |
| reg_rdata_next[31:0] = flags_98_qs; |
| end |
| |
| addr_hit[124]: begin |
| reg_rdata_next[31:0] = flags_99_qs; |
| end |
| |
| addr_hit[125]: begin |
| reg_rdata_next[31:0] = flags_100_qs; |
| end |
| |
| addr_hit[126]: begin |
| reg_rdata_next[31:0] = flags_101_qs; |
| end |
| |
| addr_hit[127]: begin |
| reg_rdata_next[31:0] = flags_102_qs; |
| end |
| |
| addr_hit[128]: begin |
| reg_rdata_next[31:0] = flags_103_qs; |
| end |
| |
| addr_hit[129]: begin |
| reg_rdata_next[31:0] = flags_104_qs; |
| end |
| |
| addr_hit[130]: begin |
| reg_rdata_next[31:0] = flags_105_qs; |
| end |
| |
| addr_hit[131]: begin |
| reg_rdata_next[31:0] = flags_106_qs; |
| end |
| |
| addr_hit[132]: begin |
| reg_rdata_next[31:0] = flags_107_qs; |
| end |
| |
| addr_hit[133]: begin |
| reg_rdata_next[31:0] = flags_108_qs; |
| end |
| |
| addr_hit[134]: begin |
| reg_rdata_next[31:0] = flags_109_qs; |
| end |
| |
| addr_hit[135]: begin |
| reg_rdata_next[31:0] = flags_110_qs; |
| end |
| |
| addr_hit[136]: begin |
| reg_rdata_next[31:0] = flags_111_qs; |
| end |
| |
| addr_hit[137]: begin |
| reg_rdata_next[31:0] = flags_112_qs; |
| end |
| |
| addr_hit[138]: begin |
| reg_rdata_next[31:0] = flags_113_qs; |
| end |
| |
| addr_hit[139]: begin |
| reg_rdata_next[31:0] = flags_114_qs; |
| end |
| |
| addr_hit[140]: begin |
| reg_rdata_next[31:0] = flags_115_qs; |
| end |
| |
| addr_hit[141]: begin |
| reg_rdata_next[31:0] = flags_116_qs; |
| end |
| |
| addr_hit[142]: begin |
| reg_rdata_next[31:0] = flags_117_qs; |
| end |
| |
| addr_hit[143]: begin |
| reg_rdata_next[31:0] = flags_118_qs; |
| end |
| |
| addr_hit[144]: begin |
| reg_rdata_next[31:0] = flags_119_qs; |
| end |
| |
| addr_hit[145]: begin |
| reg_rdata_next[31:0] = flags_120_qs; |
| end |
| |
| addr_hit[146]: begin |
| reg_rdata_next[31:0] = flags_121_qs; |
| end |
| |
| addr_hit[147]: begin |
| reg_rdata_next[31:0] = flags_122_qs; |
| end |
| |
| addr_hit[148]: begin |
| reg_rdata_next[31:0] = flags_123_qs; |
| end |
| |
| addr_hit[149]: begin |
| reg_rdata_next[31:0] = flags_124_qs; |
| end |
| |
| addr_hit[150]: begin |
| reg_rdata_next[31:0] = flags_125_qs; |
| end |
| |
| addr_hit[151]: begin |
| reg_rdata_next[31:0] = flags_126_qs; |
| end |
| |
| addr_hit[152]: begin |
| reg_rdata_next[31:0] = flags_127_qs; |
| end |
| |
| addr_hit[153]: begin |
| reg_rdata_next[31:0] = flags_128_qs; |
| end |
| |
| addr_hit[154]: begin |
| reg_rdata_next[31:0] = flags_129_qs; |
| end |
| |
| addr_hit[155]: begin |
| reg_rdata_next[31:0] = flags_130_qs; |
| end |
| |
| addr_hit[156]: begin |
| reg_rdata_next[31:0] = flags_131_qs; |
| end |
| |
| addr_hit[157]: begin |
| reg_rdata_next[31:0] = flags_132_qs; |
| end |
| |
| addr_hit[158]: begin |
| reg_rdata_next[31:0] = flags_133_qs; |
| end |
| |
| addr_hit[159]: begin |
| reg_rdata_next[31:0] = flags_134_qs; |
| end |
| |
| addr_hit[160]: begin |
| reg_rdata_next[31:0] = flags_135_qs; |
| end |
| |
| addr_hit[161]: begin |
| reg_rdata_next[31:0] = flags_136_qs; |
| end |
| |
| addr_hit[162]: begin |
| reg_rdata_next[31:0] = flags_137_qs; |
| end |
| |
| addr_hit[163]: begin |
| reg_rdata_next[31:0] = flags_138_qs; |
| end |
| |
| addr_hit[164]: begin |
| reg_rdata_next[31:0] = flags_139_qs; |
| end |
| |
| addr_hit[165]: begin |
| reg_rdata_next[31:0] = flags_140_qs; |
| end |
| |
| addr_hit[166]: begin |
| reg_rdata_next[31:0] = flags_141_qs; |
| end |
| |
| addr_hit[167]: begin |
| reg_rdata_next[31:0] = flags_142_qs; |
| end |
| |
| addr_hit[168]: begin |
| reg_rdata_next[31:0] = flags_143_qs; |
| end |
| |
| addr_hit[169]: begin |
| reg_rdata_next[31:0] = flags_144_qs; |
| end |
| |
| addr_hit[170]: begin |
| reg_rdata_next[31:0] = flags_145_qs; |
| end |
| |
| addr_hit[171]: begin |
| reg_rdata_next[31:0] = flags_146_qs; |
| end |
| |
| addr_hit[172]: begin |
| reg_rdata_next[31:0] = flags_147_qs; |
| end |
| |
| addr_hit[173]: begin |
| reg_rdata_next[31:0] = flags_148_qs; |
| end |
| |
| addr_hit[174]: begin |
| reg_rdata_next[31:0] = flags_149_qs; |
| end |
| |
| addr_hit[175]: begin |
| reg_rdata_next[31:0] = flags_150_qs; |
| end |
| |
| addr_hit[176]: begin |
| reg_rdata_next[31:0] = flags_151_qs; |
| end |
| |
| addr_hit[177]: begin |
| reg_rdata_next[31:0] = flags_152_qs; |
| end |
| |
| addr_hit[178]: begin |
| reg_rdata_next[31:0] = flags_153_qs; |
| end |
| |
| addr_hit[179]: begin |
| reg_rdata_next[31:0] = flags_154_qs; |
| end |
| |
| addr_hit[180]: begin |
| reg_rdata_next[31:0] = flags_155_qs; |
| end |
| |
| addr_hit[181]: begin |
| reg_rdata_next[31:0] = flags_156_qs; |
| end |
| |
| addr_hit[182]: begin |
| reg_rdata_next[31:0] = flags_157_qs; |
| end |
| |
| addr_hit[183]: begin |
| reg_rdata_next[31:0] = flags_158_qs; |
| end |
| |
| addr_hit[184]: begin |
| reg_rdata_next[31:0] = flags_159_qs; |
| end |
| |
| addr_hit[185]: begin |
| reg_rdata_next[31:0] = flags_160_qs; |
| end |
| |
| addr_hit[186]: begin |
| reg_rdata_next[31:0] = flags_161_qs; |
| end |
| |
| addr_hit[187]: begin |
| reg_rdata_next[31:0] = flags_162_qs; |
| end |
| |
| addr_hit[188]: begin |
| reg_rdata_next[31:0] = flags_163_qs; |
| end |
| |
| addr_hit[189]: begin |
| reg_rdata_next[31:0] = flags_164_qs; |
| end |
| |
| addr_hit[190]: begin |
| reg_rdata_next[31:0] = flags_165_qs; |
| end |
| |
| addr_hit[191]: begin |
| reg_rdata_next[31:0] = flags_166_qs; |
| end |
| |
| addr_hit[192]: begin |
| reg_rdata_next[31:0] = flags_167_qs; |
| end |
| |
| addr_hit[193]: begin |
| reg_rdata_next[31:0] = flags_168_qs; |
| end |
| |
| addr_hit[194]: begin |
| reg_rdata_next[31:0] = flags_169_qs; |
| end |
| |
| addr_hit[195]: begin |
| reg_rdata_next[31:0] = flags_170_qs; |
| end |
| |
| addr_hit[196]: begin |
| reg_rdata_next[31:0] = flags_171_qs; |
| end |
| |
| addr_hit[197]: begin |
| reg_rdata_next[31:0] = flags_172_qs; |
| end |
| |
| addr_hit[198]: begin |
| reg_rdata_next[31:0] = flags_173_qs; |
| end |
| |
| addr_hit[199]: begin |
| reg_rdata_next[31:0] = flags_174_qs; |
| end |
| |
| addr_hit[200]: begin |
| reg_rdata_next[31:0] = flags_175_qs; |
| end |
| |
| addr_hit[201]: begin |
| reg_rdata_next[31:0] = flags_176_qs; |
| end |
| |
| addr_hit[202]: begin |
| reg_rdata_next[31:0] = flags_177_qs; |
| end |
| |
| addr_hit[203]: begin |
| reg_rdata_next[31:0] = flags_178_qs; |
| end |
| |
| addr_hit[204]: begin |
| reg_rdata_next[31:0] = flags_179_qs; |
| end |
| |
| addr_hit[205]: begin |
| reg_rdata_next[31:0] = flags_180_qs; |
| end |
| |
| addr_hit[206]: begin |
| reg_rdata_next[31:0] = flags_181_qs; |
| end |
| |
| addr_hit[207]: begin |
| reg_rdata_next[31:0] = flags_182_qs; |
| end |
| |
| addr_hit[208]: begin |
| reg_rdata_next[31:0] = flags_183_qs; |
| end |
| |
| addr_hit[209]: begin |
| reg_rdata_next[31:0] = flags_184_qs; |
| end |
| |
| addr_hit[210]: begin |
| reg_rdata_next[31:0] = flags_185_qs; |
| end |
| |
| addr_hit[211]: begin |
| reg_rdata_next[31:0] = flags_186_qs; |
| end |
| |
| addr_hit[212]: begin |
| reg_rdata_next[31:0] = flags_187_qs; |
| end |
| |
| addr_hit[213]: begin |
| reg_rdata_next[31:0] = flags_188_qs; |
| end |
| |
| addr_hit[214]: begin |
| reg_rdata_next[31:0] = flags_189_qs; |
| end |
| |
| addr_hit[215]: begin |
| reg_rdata_next[31:0] = flags_190_qs; |
| end |
| |
| addr_hit[216]: begin |
| reg_rdata_next[31:0] = flags_191_qs; |
| end |
| |
| addr_hit[217]: begin |
| reg_rdata_next[31:0] = flags_192_qs; |
| end |
| |
| addr_hit[218]: begin |
| reg_rdata_next[31:0] = flags_193_qs; |
| end |
| |
| addr_hit[219]: begin |
| reg_rdata_next[31:0] = flags_194_qs; |
| end |
| |
| addr_hit[220]: begin |
| reg_rdata_next[31:0] = flags_195_qs; |
| end |
| |
| addr_hit[221]: begin |
| reg_rdata_next[31:0] = flags_196_qs; |
| end |
| |
| addr_hit[222]: begin |
| reg_rdata_next[31:0] = flags_197_qs; |
| end |
| |
| addr_hit[223]: begin |
| reg_rdata_next[31:0] = flags_198_qs; |
| end |
| |
| addr_hit[224]: begin |
| reg_rdata_next[31:0] = flags_199_qs; |
| end |
| |
| addr_hit[225]: begin |
| reg_rdata_next[31:0] = flags_200_qs; |
| end |
| |
| addr_hit[226]: begin |
| reg_rdata_next[31:0] = flags_201_qs; |
| end |
| |
| addr_hit[227]: begin |
| reg_rdata_next[31:0] = flags_202_qs; |
| end |
| |
| addr_hit[228]: begin |
| reg_rdata_next[31:0] = flags_203_qs; |
| end |
| |
| addr_hit[229]: begin |
| reg_rdata_next[31:0] = flags_204_qs; |
| end |
| |
| addr_hit[230]: begin |
| reg_rdata_next[31:0] = flags_205_qs; |
| end |
| |
| addr_hit[231]: begin |
| reg_rdata_next[31:0] = flags_206_qs; |
| end |
| |
| addr_hit[232]: begin |
| reg_rdata_next[31:0] = flags_207_qs; |
| end |
| |
| addr_hit[233]: begin |
| reg_rdata_next[31:0] = flags_208_qs; |
| end |
| |
| addr_hit[234]: begin |
| reg_rdata_next[31:0] = flags_209_qs; |
| end |
| |
| addr_hit[235]: begin |
| reg_rdata_next[31:0] = flags_210_qs; |
| end |
| |
| addr_hit[236]: begin |
| reg_rdata_next[31:0] = flags_211_qs; |
| end |
| |
| addr_hit[237]: begin |
| reg_rdata_next[31:0] = flags_212_qs; |
| end |
| |
| addr_hit[238]: begin |
| reg_rdata_next[31:0] = flags_213_qs; |
| end |
| |
| addr_hit[239]: begin |
| reg_rdata_next[31:0] = flags_214_qs; |
| end |
| |
| addr_hit[240]: begin |
| reg_rdata_next[31:0] = flags_215_qs; |
| end |
| |
| addr_hit[241]: begin |
| reg_rdata_next[31:0] = flags_216_qs; |
| end |
| |
| addr_hit[242]: begin |
| reg_rdata_next[31:0] = flags_217_qs; |
| end |
| |
| addr_hit[243]: begin |
| reg_rdata_next[31:0] = flags_218_qs; |
| end |
| |
| addr_hit[244]: begin |
| reg_rdata_next[31:0] = flags_219_qs; |
| end |
| |
| addr_hit[245]: begin |
| reg_rdata_next[31:0] = flags_220_qs; |
| end |
| |
| addr_hit[246]: begin |
| reg_rdata_next[31:0] = flags_221_qs; |
| end |
| |
| addr_hit[247]: begin |
| reg_rdata_next[31:0] = flags_222_qs; |
| end |
| |
| addr_hit[248]: begin |
| reg_rdata_next[31:0] = flags_223_qs; |
| end |
| |
| addr_hit[249]: begin |
| reg_rdata_next[31:0] = flags_224_qs; |
| end |
| |
| addr_hit[250]: begin |
| reg_rdata_next[31:0] = flags_225_qs; |
| end |
| |
| addr_hit[251]: begin |
| reg_rdata_next[31:0] = flags_226_qs; |
| end |
| |
| addr_hit[252]: begin |
| reg_rdata_next[31:0] = flags_227_qs; |
| end |
| |
| addr_hit[253]: begin |
| reg_rdata_next[31:0] = flags_228_qs; |
| end |
| |
| addr_hit[254]: begin |
| reg_rdata_next[31:0] = flags_229_qs; |
| end |
| |
| addr_hit[255]: begin |
| reg_rdata_next[31:0] = flags_230_qs; |
| end |
| |
| addr_hit[256]: begin |
| reg_rdata_next[31:0] = flags_231_qs; |
| end |
| |
| addr_hit[257]: begin |
| reg_rdata_next[31:0] = flags_232_qs; |
| end |
| |
| addr_hit[258]: begin |
| reg_rdata_next[31:0] = flags_233_qs; |
| end |
| |
| addr_hit[259]: begin |
| reg_rdata_next[31:0] = flags_234_qs; |
| end |
| |
| addr_hit[260]: begin |
| reg_rdata_next[31:0] = flags_235_qs; |
| end |
| |
| addr_hit[261]: begin |
| reg_rdata_next[31:0] = flags_236_qs; |
| end |
| |
| addr_hit[262]: begin |
| reg_rdata_next[31:0] = flags_237_qs; |
| end |
| |
| addr_hit[263]: begin |
| reg_rdata_next[31:0] = flags_238_qs; |
| end |
| |
| addr_hit[264]: begin |
| reg_rdata_next[31:0] = flags_239_qs; |
| end |
| |
| addr_hit[265]: begin |
| reg_rdata_next[31:0] = flags_240_qs; |
| end |
| |
| addr_hit[266]: begin |
| reg_rdata_next[31:0] = flags_241_qs; |
| end |
| |
| addr_hit[267]: begin |
| reg_rdata_next[31:0] = flags_242_qs; |
| end |
| |
| addr_hit[268]: begin |
| reg_rdata_next[31:0] = flags_243_qs; |
| end |
| |
| addr_hit[269]: begin |
| reg_rdata_next[31:0] = flags_244_qs; |
| end |
| |
| addr_hit[270]: begin |
| reg_rdata_next[31:0] = flags_245_qs; |
| end |
| |
| addr_hit[271]: begin |
| reg_rdata_next[31:0] = flags_246_qs; |
| end |
| |
| addr_hit[272]: begin |
| reg_rdata_next[31:0] = flags_247_qs; |
| end |
| |
| addr_hit[273]: begin |
| reg_rdata_next[31:0] = flags_248_qs; |
| end |
| |
| addr_hit[274]: begin |
| reg_rdata_next[31:0] = flags_249_qs; |
| end |
| |
| addr_hit[275]: begin |
| reg_rdata_next[31:0] = flags_250_qs; |
| end |
| |
| addr_hit[276]: begin |
| reg_rdata_next[31:0] = flags_251_qs; |
| end |
| |
| addr_hit[277]: begin |
| reg_rdata_next[31:0] = flags_252_qs; |
| end |
| |
| addr_hit[278]: begin |
| reg_rdata_next[31:0] = flags_253_qs; |
| end |
| |
| addr_hit[279]: begin |
| reg_rdata_next[31:0] = flags_254_qs; |
| end |
| |
| addr_hit[280]: begin |
| reg_rdata_next[31:0] = flags_255_qs; |
| end |
| |
| default: begin |
| reg_rdata_next = '1; |
| end |
| endcase |
| end |
| |
| // shadow busy |
| logic shadow_busy; |
| assign shadow_busy = 1'b0; |
| |
| // register busy |
| assign reg_busy = shadow_busy; |
| |
| // Unused signal tieoff |
| |
| // wdata / byte enable are not always fully used |
| // add a blanket unused statement to handle lint waivers |
| logic unused_wdata; |
| logic unused_be; |
| assign unused_wdata = ^reg_wdata; |
| assign unused_be = ^reg_be; |
| |
| // Assertions for Register Interface |
| `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) |
| `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) |
| |
| `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) |
| |
| `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) |
| |
| // this is formulated as an assumption such that the FPV testbenches do disprove this |
| // property by mistake |
| //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) |
| |
| endmodule |
