hw/ip/rv_dm/dv/rv_dm_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: rv_dm

  // Top level dut name (sv module).
  dut: rv_dm

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:rv_dm_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/rv_dm/data/rv_dm_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/rv_dm/data/rv_dm.hjson"

  // Import additional common sim cfg files.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["rv_dm_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  overrides: [
    {
      // This sets the width of UVM data (UVM_REG_DATA_WIDTH) to sufficiently large value. RV_DM DV
      // contains a heterogeneous set of CSR RAL models accessed via TL and the JTAG interface, each
      // requiring a different data width to be set.
      // TODO: Remove these overrides here and the original ones in common_sim_cfg.hjson. None of
      // tese settings are needed.
      name: tl_dw
      value: 64
    }
    {
      name: tl_dbw
      value: 8
    }
    {
      name: default_vcs_cov_cfg_file
      value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/ip/rv_dm/dv/cov/cover.cfg"
    }
    {
      name: cover_reg_top_vcs_cov_cfg_file
      value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover_reg_top.cfg+{proj_root}/hw/ip/rv_dm/dv/cov/cover_reg_top.cfg"
    }
  ]

  // Default UVM test and seq class name.
  uvm_test: rv_dm_base_test
  uvm_test_seq: rv_dm_base_vseq

  // TODO: Update cover_reg_top hier file to accommodate JTAG DTM, DM CSRs and debug mem TL
  // interfaces.

  // List of test specifications.
  tests: [
    {
      name: rv_dm_smoke
      uvm_test_seq: rv_dm_smoke_vseq
      reseed: 2
    }
    {
      name: rv_dm_jtag_dtm_csr_hw_reset
      uvm_test_seq: rv_dm_jtag_dtm_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_hw_reset"]
      reseed: 5
    }
    {
      name: rv_dm_jtag_dtm_csr_rw
      uvm_test_seq: rv_dm_jtag_dtm_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_rw"]
      reseed: 20
    }
    {
      name: rv_dm_jtag_dtm_csr_bit_bash
      uvm_test_seq: rv_dm_jtag_dtm_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_bit_bash"]
      reseed: 5
    }
    {
      name: rv_dm_jtag_dtm_csr_aliasing
      uvm_test_seq: rv_dm_jtag_dtm_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_aliasing"]
      reseed: 5
    }
    {
      name: rv_dm_jtag_dmi_csr_hw_reset
      uvm_test_seq: rv_dm_jtag_dmi_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_hw_reset"]
      reseed: 5
    }
    {
      name: rv_dm_jtag_dmi_csr_rw
      uvm_test_seq: rv_dm_jtag_dmi_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_rw"]
      reseed: 20
    }
    {
      name: rv_dm_jtag_dmi_csr_bit_bash
      uvm_test_seq: rv_dm_jtag_dmi_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_bit_bash"]
      reseed: 5
    }
    {
      name: rv_dm_jtag_dmi_csr_aliasing
      uvm_test_seq: rv_dm_jtag_dmi_csr_vseq
      build_mode: "cover_reg_top"
      run_opts: ["+en_scb=0", "+csr_aliasing"]
      reseed: 5
    }
    {
      name: rv_dm_sba_tl_access
      uvm_test_seq: rv_dm_sba_tl_access_vseq
      reseed: 20
    }
    {
      name: rv_dm_delayed_resp_sba_tl_access
      uvm_test_seq: rv_dm_delayed_resp_sba_tl_access_vseq
      run_opts: ["+zero_delays=0"]
      reseed: 20
    }
    {
      name: rv_dm_bad_sba_tl_access
      uvm_test_seq: rv_dm_bad_sba_tl_access_vseq
      reseed: 20
    }
    {
      name: rv_dm_autoincr_sba_tl_access
      uvm_test_seq: rv_dm_autoincr_sba_tl_access_vseq
      reseed: 20
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["rv_dm_smoke",
              "rv_dm_jtag_dtm_csr_hw_reset",
              "rv_dm_jtag_dtm_csr_rw",
              "rv_dm_jtag_dmi_csr_hw_reset",
              "rv_dm_jtag_dmi_csr_rw"]
    }
  ]
}