hw/ip/rom_ctrl/dv/rom_ctrl_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: rom_ctrl

  // Top level dut name (sv module).
  dut: rom_ctrl

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:rom_ctrl_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/rom_ctrl/data/rom_ctrl_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/rom_ctrl/data/rom_ctrl.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Config files to get the correct flags for crypto_dpi_prince
                "{proj_root}/hw/ip/prim/dv/prim_prince/crypto_dpi_prince/crypto_dpi_prince_sim_opts.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/passthru_mem_intg_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  en_build_modes: ["{tool}_crypto_dpi_prince_build_opts"]

  // Add additional tops for simulation.
  sim_tops: ["rom_ctrl_bind", "rom_ctrl_cov_bind",
             "sec_cm_prim_sparse_fsm_flop_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Add ROM_CTRL specific exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_unr_excl.el",
                       "{proj_root}/hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el"]

  // Default UVM test and seq class name.
  uvm_test: rom_ctrl_base_test
  uvm_test_seq: rom_ctrl_base_vseq

  run_opts: ["+cdc_instrumentation_enabled=1"]

  // List of test specifications.
  tests: [
    {
      name: rom_ctrl_smoke
      uvm_test_seq: rom_ctrl_smoke_vseq
    }
    {
      name: rom_ctrl_stress_all
      uvm_test_seq: rom_ctrl_stress_all_vseq
    }
    {
      name: rom_ctrl_max_throughput_chk
      uvm_test_seq: rom_ctrl_throughput_vseq
      run_opts: ["+zero_delays=1"]
    }
    {
      name: rom_ctrl_corrupt_sig_fatal_chk
      uvm_test_seq: rom_ctrl_corrupt_sig_fatal_chk_vseq
    }
    {
      name: rom_ctrl_kmac_err_chk
      uvm_test_seq: rom_ctrl_kmac_err_chk_vseq
    }

    // TODO: add more tests here
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["rom_ctrl_smoke"]
    }
  ]
}