hw/ip/rv_dm/data/rv_dm.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{ name: "rv_dm",
  clocking: [
    {clock: "clk_i", reset: "rst_ni"}
  ]
  bus_interfaces: [
    { protocol: "tlul", direction: "host",   name: "sba" }
    { protocol: "tlul", direction: "device", name: "regs" }
    { protocol: "tlul", direction: "device", name: "rom" }
  ],
  scan: "true", // Enable `scanmode_i` port
  scan_reset: "true", // Enable `scan_rst_ni` port
  param_list: [
    { name:    "NrHarts",
      type:    "int",
      default: "1",
      desc:    "Number of hardware threads in the system."
      local:   "true"
    },
    { name:    "IdcodeValue",
      type:    "logic [31:0]",
      default: "32'h 0000_0001",
      desc:    "RISC-V debug module JTAG ID code."
      local:   "false",
      expose:  "true"
    },
  ]
  interrupt_list: [
  ],
  alert_list: [
    { name: "fatal_fault",
      desc: '''
      This fatal alert is triggered when a fatal TL-UL bus integrity fault is detected.
      '''
    }
  ],
  inter_signal_list: [
    { struct:  "jtag",
      type:    "req_rsp",
      name:    "jtag",
      act:     "rsp",
      package: "jtag_pkg",
    },
    { struct:  "lc_tx"
      type:    "uni"
      name:    "lc_hw_debug_en"
      act:     "rcv"
      default: "lc_ctrl_pkg::Off"
      package: "lc_ctrl_pkg"
    },
    // TBD: should we connect this to the clock manager?
    { struct:  "logic"
      type:    "uni"
      name:    "unavailable"
      act:     "rcv"
      default: "1'b0"
    },
    { struct:  "logic"
      type:    "uni"
      name:    "ndmreset_req"
      act:     "req"
    },
    { struct:  "logic"
      type:    "uni"
      name:    "dmactive"
      act:     "req"
    },
    { struct:  "logic [rv_dm_reg_pkg::NrHarts-1:0]"
      type:    "uni"
      name:    "debug_req"
      act:     "req"
    },
  ]
  countermeasures: [
    { name: "BUS.INTEGRITY",
      desc: "End-to-end bus integrity scheme."
    }
    { name: "LC_HW_DEBUG_EN.INTERSIG.MUBI",
      desc: "The life cycle hardware debug enable signal is multibit encoded."
    }
    { name: "DM_EN.CTRL.LC_GATED",
      desc: '''
            The debug module is enabled with the LC_HW_DEBUG_EN signal.
            This enablement is implemented by gating / enabling critical
            blocks with separately buffered copies of the life cycle signal.
            This comprises the debug module interface (DMI) attached to the TAP,
            the reset request line, the system bus access module (SBA), the debug
            request output, the TL-UL adapter for the debug ROM, and the ifetch indicator
            being fed into the TL-UL adapter for the debug ROM.
            '''
    }
    { name: "EXEC.CTRL.MUBI",
      desc: '''
            The instruction fetch enable signal that is modulated with LC_HW_DEBUG_EN
            and that feeds into the TL-UL adapter is multibit encoded.
            '''
    }
  ]
  regwidth: "32",
  registers: {
    regs:[
    ]
    rom: [
      // ROM size (given as `items` below) must be a power of two.
      { window: {
          name: "ROM"
          items: "1024" // 4 KiB
          swaccess: "ro",
          desc: '''Access window into the debug ROM.'''
        }
      }
    ]
  }
}