| // Copyright lowRISC contributors. |
| // Licensed under the Apache License, Version 2.0, see LICENSE for details. |
| // SPDX-License-Identifier: Apache-2.0 |
| // |
| # ALERT_HANDLER register template |
| |
| { |
| name: "alert_handler", |
| design_spec: "../doc", |
| dv_doc: "../doc/dv", |
| hw_checklist: "../doc/checklist", |
| sw_checklist: "/sw/device/lib/dif/dif_alert_handler" |
| version: "1.0", |
| life_stage: "L1", |
| design_stage: "D3", |
| verification_stage: "V2S", |
| dif_stage: "S2", |
| notes: "Use both FPV and DV to perform block level verification.", |
| clocking: [ |
| {clock: "clk_i", reset: "rst_ni", primary: true}, |
| {clock: "clk_edn_i", reset: "rst_edn_ni"} |
| ] |
| bus_interfaces: [ |
| { protocol: "tlul", direction: "device", hier_path: "u_reg_wrap.u_reg" } |
| ], |
| regwidth: "32", |
| param_list: [ |
| // Random netlist constants |
| { name: "RndCnstLfsrSeed", |
| desc: "Compile-time random bits for initial LFSR seed", |
| type: "alert_pkg::lfsr_seed_t" |
| randcount: "32", |
| randtype: "data", // randomize randcount databits |
| } |
| { name: "RndCnstLfsrPerm", |
| desc: "Compile-time random permutation for LFSR output", |
| type: "alert_pkg::lfsr_perm_t" |
| randcount: "32", |
| randtype: "perm", // random permutation for randcount elements |
| } |
| // Normal parameters |
| { name: "NAlerts", |
| desc: "Number of alert channels.", |
| type: "int", |
| default: "65", |
| local: "true" |
| }, |
| { name: "NLpg", |
| desc: "Number of LPGs.", |
| type: "int", |
| default: "24", |
| local: "true" |
| }, |
| { name: "NLpgWidth", |
| desc: "Width of LPG ID.", |
| type: "int", |
| default: "5", |
| local: "true" |
| }, |
| { name: "LpgMap", |
| desc: ''' |
| Defines a mapping from alerts to LPGs. |
| ''' |
| type: "logic [NAlerts-1:0][NLpgWidth-1:0]", |
| default: ''' |
| { |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd19, |
| 5'd23, |
| 5'd23, |
| 5'd22, |
| 5'd22, |
| 5'd21, |
| 5'd20, |
| 5'd20, |
| 5'd19, |
| 5'd18, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd17, |
| 5'd16, |
| 5'd12, |
| 5'd12, |
| 5'd14, |
| 5'd11, |
| 5'd13, |
| 5'd13, |
| 5'd12, |
| 5'd11, |
| 5'd11, |
| 5'd11, |
| 5'd11, |
| 5'd10, |
| 5'd9, |
| 5'd8, |
| 5'd7, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd6, |
| 5'd5, |
| 5'd0, |
| 5'd4, |
| 5'd3, |
| 5'd2, |
| 5'd1, |
| 5'd0, |
| 5'd0, |
| 5'd0, |
| 5'd0, |
| 5'd0 |
| } |
| ''', |
| local: "true" |
| }, |
| { name: "EscCntDw", |
| desc: "Width of the escalation timer.", |
| type: "int", |
| default: "32", |
| local: "true" |
| }, |
| { name: "AccuCntDw", |
| desc: "Width of the accumulation counter.", |
| type: "int", |
| default: "16", |
| local: "true" |
| }, |
| { name: "AsyncOn", |
| desc: ''' |
| Each bit of this parameter corresponds to an escalation channel and |
| defines whether the protocol is synchronous (0) or asynchronous (1). |
| ''' |
| type: "logic [NAlerts-1:0]", |
| default: ''' |
| { |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1, |
| 1'b1 |
| } |
| ''' |
| local: "true" |
| }, |
| { name: "N_CLASSES", |
| desc: "Number of classes", |
| type: "int", |
| default: "4", |
| local: "true" |
| }, |
| { name: "N_ESC_SEV", |
| desc: "Number of escalation severities", |
| type: "int", |
| default: "4", |
| local: "true" |
| }, |
| { name: "N_PHASES", |
| desc: "Number of escalation phases", |
| type: "int", |
| default: "4", |
| local: "true" |
| }, |
| { name: "N_LOC_ALERT", |
| desc: "Number of local alerts", |
| type: "int", |
| default: "7", |
| local: "true" |
| }, |
| { name: "PING_CNT_DW", |
| desc: "Width of ping counter", |
| type: "int", |
| default: "16", |
| local: "true" |
| }, |
| { name: "PHASE_DW", |
| desc: "Width of phase ID", |
| type: "int", |
| default: "2", |
| local: "true" |
| }, |
| { name: "CLASS_DW", |
| desc: "Width of class ID", |
| type: "int", |
| default: "2", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_ALERT_PINGFAIL", |
| desc: "Local alert ID for alert ping failure.", |
| type: "int", |
| default: "0", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_ESC_PINGFAIL", |
| desc: "Local alert ID for escalation ping failure.", |
| type: "int", |
| default: "1", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_ALERT_INTEGFAIL", |
| desc: "Local alert ID for alert integrity failure.", |
| type: "int", |
| default: "2", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_ESC_INTEGFAIL", |
| desc: "Local alert ID for escalation integrity failure.", |
| type: "int", |
| default: "3", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_BUS_INTEGFAIL", |
| desc: "Local alert ID for bus integrity failure.", |
| type: "int", |
| default: "4", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR", |
| desc: "Local alert ID for shadow register update error.", |
| type: "int", |
| default: "5", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR", |
| desc: "Local alert ID for shadow register storage error.", |
| type: "int", |
| default: "6", |
| local: "true" |
| }, |
| { name: "LOCAL_ALERT_ID_LAST", |
| desc: "Last local alert ID.", |
| type: "int", |
| default: "6", |
| local: "true" |
| }, |
| ], |
| |
| inter_signal_list: [ |
| { struct: "alert_crashdump", |
| type: "uni", |
| name: "crashdump", |
| act: "req", |
| package: "alert_pkg" |
| }, |
| { struct: "edn" |
| type: "req_rsp" |
| name: "edn" |
| act: "req" |
| width: "1" |
| package: "edn_pkg" |
| }, |
| { struct: "esc_rx" |
| type: "uni" |
| name: "esc_rx" |
| act: "rcv" |
| width: "4", // N_ESC_SEV |
| package: "prim_esc_pkg" |
| }, |
| { struct: "esc_tx" |
| type: "uni" |
| name: "esc_tx" |
| act: "req" |
| width: "4", // N_ESC_SEV |
| package: "prim_esc_pkg" |
| }, |
| ] |
| |
| countermeasures: [ |
| { name: "BUS.INTEGRITY", |
| desc: "End-to-end bus integrity scheme." |
| } |
| { name: "CONFIG.SHADOW", |
| desc: "Important CSRs are shadowed." |
| } |
| { name: "PING_TIMER.CONFIG.REGWEN", |
| desc: "The ping timer configuration registers are REGWEN protected." |
| } |
| { name: "ALERT.CONFIG.REGWEN", |
| desc: "The individual alert enables are REGWEN protected." |
| } |
| { name: "ALERT_LOC.CONFIG.REGWEN", |
| desc: "The individual local alert enables are REGWEN protected." |
| } |
| { name: "CLASS.CONFIG.REGWEN", |
| desc: "The class configuration registers are REGWEN protected." |
| } |
| { name: "ALERT.INTERSIG.DIFF", |
| desc: "Differentially encoded alert channels." |
| } |
| { name: "LPG.INTERSIG.MUBI", |
| desc: "LPG signals are encoded with MUBI types." |
| } |
| { name: "ESC.INTERSIG.DIFF", |
| desc: "Differentially encoded escalation channels." |
| } |
| { name: "ALERT_RX.INTERSIG.BKGN_CHK", |
| desc: "Periodic background checks on alert channels (ping mechanism)." |
| } |
| { name: "ESC_TX.INTERSIG.BKGN_CHK", |
| desc: "Periodic background checks on escalation channels (ping mechanism)." |
| } |
| { name: "ESC_RX.INTERSIG.BKGN_CHK", |
| desc: "Escalation receivers can detect absence of periodic ping requests." |
| } |
| { name: "ESC_TIMER.FSM.SPARSE", |
| desc: "Escalation timer FSMs are sparsely encoded." |
| } |
| { name: "PING_TIMER.FSM.SPARSE", |
| desc: "Ping timer FSM is sparsely encoded." |
| } |
| { name: "ESC_TIMER.FSM.LOCAL_ESC", |
| desc: "Escalation timer FSMs move into an invalid state upon local escalation." |
| } |
| { name: "PING_TIMER.FSM.LOCAL_ESC", |
| desc: "Ping timer FSM moves into an invalid state upon local escalation." |
| } |
| { name: "ESC_TIMER.FSM.GLOBAL_ESC", |
| desc: ''' |
| The escalation timer FSMs are the root of global escalation, |
| hence if any of them moves into an invalid state by virtue of |
| ESC_TIMER.FSM.LOCAL_ESC, this will trigger all escalation actions |
| and thereby global escalation as well. |
| ''' |
| } |
| { name: "ACCU.CTR.REDUN", |
| desc: "Accumulator counters employ a cross-counter implementation." |
| } |
| { name: "ESC_TIMER.CTR.REDUN", |
| desc: "Escalation timer counters employ a duplicated counter implementation." |
| } |
| { name: "PING_TIMER.CTR.REDUN", |
| desc: "Ping timer counters employ a duplicated counter implementation." |
| } |
| { name: "PING_TIMER.LFSR.REDUN", |
| desc: "Ping timer LFSR is redundant." |
| } |
| ] |
| |
| # interrupt registers for the classes |
| interrupt_list: [ |
| { name: "classa", |
| desc: ''' |
| Interrupt state bit of Class A. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. |
| ''', |
| }, |
| { name: "classb", |
| desc: ''' |
| Interrupt state bit of Class B. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. |
| ''', |
| }, |
| { name: "classc", |
| desc: ''' |
| Interrupt state bit of Class C. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. |
| ''', |
| }, |
| { name: "classd", |
| desc: ''' |
| Interrupt state bit of Class D. Set by HW in case an alert within this class triggered. Defaults true, write one to clear. |
| ''', |
| }, |
| ], |
| |
| registers: [ |
| # register lock for ping timeout counter |
| { name: "PING_TIMER_REGWEN", |
| desc: ''' |
| Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED. |
| ''', |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { |
| bits: "0", |
| desc: ''' |
| When true, the !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED registers can be modified. |
| When false, they become read-only. Defaults true, write one to clear. |
| This should be cleared once the alert handler has been configured and the ping |
| timer mechanism has been kicked off. |
| ''' |
| resval: 1, |
| }, |
| ] |
| }, |
| { name: "PING_TIMEOUT_CYC_SHADOWED", |
| desc: ''' |
| Ping timeout cycle count. |
| ''' |
| shadowed: "true", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "PING_TIMER_REGWEN", |
| fields: [ |
| { |
| bits: "PING_CNT_DW-1:0", |
| resval: 256, |
| desc: ''' |
| Timeout value in cycles. |
| If an alert receiver or an escalation sender does not respond to a ping within this timeout window, a pingfail alert will be raised. |
| It is recommended to set this value to the equivalent of 256 cycles of the slowest alert sender clock domain in the system (or greater). |
| ''' |
| } |
| ] |
| } |
| { name: "PING_TIMER_EN_SHADOWED", |
| desc: ''' |
| Ping timer enable. |
| ''' |
| shadowed: "true", |
| swaccess: "rw1s", |
| hwaccess: "hro", |
| regwen: "PING_TIMER_REGWEN", |
| fields: [ |
| { |
| bits: "0", |
| resval: 0, |
| desc: ''' |
| Setting this to 1 enables the ping timer mechanism. |
| This bit cannot be cleared to 0 once it has been set to 1. |
| |
| Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. |
| ''' |
| } |
| ] |
| } |
| # all alerts |
| { multireg: { name: "ALERT_REGWEN", |
| desc: "Register write enable for alert enable bits.", |
| count: "NAlerts", |
| compact: "false", |
| swaccess: "rw0c", |
| hwaccess: "hro", |
| hwqe: "false", |
| cname: "alert", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Alert configuration write enable bit. |
| If this is cleared to 0, the corresponding !!ALERT_EN_SHADOWED |
| and !!ALERT_CLASS_SHADOWED bits are not writable anymore. |
| |
| Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. |
| ''', |
| resval: "1", |
| } |
| ] |
| } |
| }, |
| { multireg: { name: "ALERT_EN_SHADOWED", |
| desc: '''Enable register for alerts. |
| ''', |
| count: "NAlerts", |
| shadowed: "true", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "ALERT_REGWEN", |
| regwen_multi: "true", |
| cname: "alert", |
| tags: [// Enable `alert_en` might cause top-level escalators to trigger |
| // unexpected reset |
| "excl:CsrAllTests:CsrExclWrite"] |
| fields: [ |
| { bits: "0", |
| name: "EN_A", |
| resval: 0 |
| desc: ''' |
| Alert enable bit. |
| |
| Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. |
| ''' |
| } |
| ] |
| } |
| }, |
| { multireg: { name: "ALERT_CLASS_SHADOWED", |
| desc: '''Class assignment of alerts. |
| ''', |
| count: "NAlerts", |
| shadowed: "true", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "ALERT_REGWEN", |
| regwen_multi: "true", |
| cname: "alert", |
| fields: [ |
| { |
| bits: "CLASS_DW-1:0", |
| name: "CLASS_A", |
| resval: 0 |
| desc: "Classification ", |
| enum: [ |
| { value: "0", name: "ClassA", desc: "" }, |
| { value: "1", name: "ClassB", desc: "" }, |
| { value: "2", name: "ClassC", desc: "" }, |
| { value: "3", name: "ClassD", desc: "" }, |
| ] |
| } |
| ] |
| } |
| }, |
| { multireg: { |
| name: "ALERT_CAUSE", |
| desc: "Alert Cause Register", |
| count: "NAlerts", |
| compact: "false", |
| cname: "ALERT", |
| swaccess: "rw1c", |
| hwaccess: "hrw", |
| fields: [ |
| { bits: "0", name: "A", desc: "Cause bit ", resval: 0} |
| ], |
| } |
| }, |
| # local alerts |
| { multireg: { name: "LOC_ALERT_REGWEN", |
| desc: "Register write enable for alert enable bits.", |
| count: "N_LOC_ALERT", |
| compact: "false", |
| swaccess: "rw0c", |
| hwaccess: "none", |
| cname: "LOC_ALERT", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Alert configuration write enable bit. |
| If this is cleared to 0, the corresponding !!LOC_ALERT_EN_SHADOWED |
| and !!LOC_ALERT_CLASS_SHADOWED bits are not writable anymore. |
| |
| Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. |
| ''', |
| resval: "1", |
| } |
| ] |
| } |
| }, |
| { multireg: { name: "LOC_ALERT_EN_SHADOWED", |
| desc: |
| ''' |
| Enable register for the local alerts |
| "alert pingfail" (0), "escalation pingfail" (1), |
| "alert integfail" (2), "escalation integfail" (3), |
| "bus integrity failure" (4), "shadow reg update error" (5) |
| and "shadow reg storage error" (6). |
| ''', |
| count: "N_LOC_ALERT", |
| shadowed: "true", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "LOC_ALERT_REGWEN", |
| regwen_multi: "true", |
| cname: "LOC_ALERT", |
| fields: [ |
| { bits: "0", |
| name: "EN_LA", |
| resval: 0 |
| desc: ''' |
| Alert enable bit. |
| |
| Note that the alert pinging mechanism will only ping alerts that have been enabled and locked. |
| ''' |
| } |
| ] |
| } |
| }, |
| { multireg: { name: "LOC_ALERT_CLASS_SHADOWED", |
| desc: ''' |
| Class assignment of the local alerts |
| "alert pingfail" (0), "escalation pingfail" (1), |
| "alert integfail" (2), "escalation integfail" (3), |
| "bus integrity failure" (4), "shadow reg update error" (5) |
| and "shadow reg storage error" (6). |
| ''', |
| count: "N_LOC_ALERT", |
| shadowed: "true", |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "LOC_ALERT_REGWEN", |
| regwen_multi: "true", |
| cname: "LOC_ALERT", |
| fields: [ |
| { |
| bits: "CLASS_DW-1:0", |
| name: "CLASS_LA", |
| resval: 0 |
| desc: "Classification ", |
| enum: [ |
| { value: "0", name: "ClassA", desc: "" }, |
| { value: "1", name: "ClassB", desc: "" }, |
| { value: "2", name: "ClassC", desc: "" }, |
| { value: "3", name: "ClassD", desc: "" }, |
| ] |
| } |
| ] |
| } |
| }, |
| { multireg: { |
| name: "LOC_ALERT_CAUSE", |
| desc: '''Alert Cause Register for the local alerts |
| "alert pingfail" (0), "escalation pingfail" (1), |
| "alert integfail" (2), "escalation integfail" (3), |
| "bus integrity failure" (4), "shadow reg update error" (5) |
| and "shadow reg storage error" (6). |
| ''', |
| count: "N_LOC_ALERT", |
| compact: "false", |
| cname: "LOC_ALERT", |
| swaccess: "rw1c", |
| hwaccess: "hrw", |
| tags: [// Top level CSR automation test, CPU clock is disabled, so escalation response will |
| // not send back to alert handler. This will set loc_alert_cause and could not predict |
| // automatically. |
| // TODO: remove the exclusion after set up top-level esc_receiver_driver |
| "excl:CsrNonInitTests:CsrExclCheck"], |
| fields: [ |
| { bits: "0", name: "LA", desc: "Cause bit ", resval: 0} |
| ] |
| } |
| }, |
| # classes |
| |
| { name: "CLASSA_REGWEN", |
| desc: ''' |
| Lock bit for Class A configuration. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| desc: ''' |
| Class configuration enable bit. |
| If this is cleared to 0, the corresponding class configuration |
| registers cannot be written anymore. |
| ''', |
| resval: 1, |
| } |
| ] |
| }, |
| { name: "CLASSA_CTRL_SHADOWED", |
| desc: "Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is false." |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "CLASSA_REGWEN", |
| shadowed: "true", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Enable escalation mechanisms (accumulation and |
| interrupt timeout) for Class A. Note that interrupts can fire |
| regardless of whether the escalation mechanisms are enabled for |
| this class or not. |
| ''', |
| } |
| { bits: "1", |
| name: "LOCK", |
| desc: ''' |
| Enable automatic locking of escalation counter for class A. |
| If true, there is no way to stop the escalation protocol for class A |
| once it has been triggered. |
| ''' |
| } |
| { bits: "2", |
| name: "EN_E0", |
| resval: 1, |
| desc: "Enable escalation signal 0 for Class A", |
| } |
| { bits: "3", |
| name: "EN_E1", |
| resval: 1, |
| desc: "Enable escalation signal 1 for Class A", |
| } |
| { bits: "4", |
| name: "EN_E2", |
| resval: 1, |
| desc: "Enable escalation signal 2 for Class A", |
| } |
| { bits: "5", |
| name: "EN_E3", |
| resval: 1, |
| desc: "Enable escalation signal 3 for Class A", |
| } |
| { bits: "7:6", |
| name: "MAP_E0", |
| resval: 0, |
| desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", |
| } |
| { bits: "9:8", |
| name: "MAP_E1", |
| resval: 1, |
| desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", |
| } |
| { bits: "11:10", |
| name: "MAP_E2", |
| resval: 2, |
| desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", |
| } |
| { bits: "13:12", |
| name: "MAP_E3", |
| resval: 3, |
| desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", |
| } |
| ] |
| }, |
| { name: "CLASSA_CLR_REGWEN", |
| desc: ''' |
| Clear enable for escalation protocol of Class A alerts. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "hwo", |
| fields: [ |
| { bits: "0", |
| desc: '''Register defaults to true, can only be cleared. This register is set |
| to false by the hardware if the escalation protocol has been triggered and the bit |
| !!CLASSA_CTRL_SHADOWED.LOCK is true. |
| ''', |
| resval: 1, |
| } |
| ], |
| tags: [// The value of this register is set to false only by hardware, under the condition |
| // that escalation is triggered and the corresponding lock bit is true |
| // Cannot not be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSA_CLR_SHADOWED", |
| desc: ''' |
| Clear for escalation protocol of Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| hwqe: "true", |
| shadowed: "true", |
| regwen: "CLASSA_CLR_REGWEN", |
| fields: [ |
| { bits: "0", |
| desc: '''Writing 1 to this register clears the accumulator and aborts escalation |
| (if it has been triggered). This clear is disabled if !!CLASSA_CLR_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSA_ACCUM_CNT", |
| desc: ''' |
| Current accumulation value for alert Class A. Software can clear this register |
| with a write to !!CLASSA_CLR_SHADOWED register unless !!CLASSA_CLR_REGWEN is false. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "AccuCntDw-1:0" } |
| ], |
| tags: [// The value of this register is determined by how many alerts have been triggered |
| // Cannot be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSA_ACCUM_THRESH_SHADOWED", |
| desc: ''' |
| Accumulation threshold value for alert Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "AccuCntDw-1:0", |
| desc: '''Once the accumulation value register is equal to the threshold escalation will |
| be triggered on the next alert occurrence within this class A begins. Note that this |
| register can not be modified if !!CLASSA_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSA_TIMEOUT_CYC_SHADOWED", |
| desc: ''' |
| Interrupt timeout in cycles. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''If the interrupt corresponding to this class is not |
| handled within the specified amount of cycles, escalation will be triggered. |
| Set to a positive value to enable the interrupt timeout for Class A. The timeout is set to zero |
| by default, which disables this feature. Note that this register can not be modified if |
| !!CLASSA_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSA_CRASHDUMP_TRIGGER_SHADOWED", |
| desc: ''' |
| Crashdump trigger configuration for Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| resval: "0", |
| fields: [ |
| { bits: "PHASE_DW-1:0", |
| desc: ''' |
| Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation |
| timer states. It is recommended to capture the crashdump upon entering the first escalation phase |
| that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order |
| to prevent spurious alert events from masking the original alert causes. |
| Note that this register can not be modified if !!CLASSA_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSA_PHASE0_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 0 for Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSA_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSA_PHASE1_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 1 for Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSA_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSA_PHASE2_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 2 for Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSA_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSA_PHASE3_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 3 for Class A. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSA_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSA_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSA_ESC_CNT", |
| desc: ''' |
| Escalation counter in cycles for Class A. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''Returns the current timeout or escalation count (depending on !!CLASSA_STATE). |
| This register can not be directly cleared. However, SW can indirectly clear as follows. |
| |
| If the class is in the Timeout state, the timeout can be aborted by clearing the |
| corresponding interrupt bit. |
| |
| If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be |
| aborted by writing to !!CLASSA_CLR_SHADOWED. Note however that has no effect if !!CLASSA_REGWEN |
| is set to false (either by SW or by HW via the !!CLASSA_CTRL_SHADOWED.LOCK feature). |
| ''' |
| } |
| ], |
| tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted |
| // Cannot be auto-predicted so excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSA_STATE", |
| desc: ''' |
| Current escalation state of Class A. See also !!CLASSA_ESC_CNT. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "2:0", |
| enum: [ |
| { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, |
| { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, |
| { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, |
| { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, |
| { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, |
| { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, |
| { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, |
| { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } |
| ] |
| } |
| ], |
| tags: [// The current escalation state cannot be auto-predicted |
| // so this register is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| |
| { name: "CLASSB_REGWEN", |
| desc: ''' |
| Lock bit for Class B configuration. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| desc: ''' |
| Class configuration enable bit. |
| If this is cleared to 0, the corresponding class configuration |
| registers cannot be written anymore. |
| ''', |
| resval: 1, |
| } |
| ] |
| }, |
| { name: "CLASSB_CTRL_SHADOWED", |
| desc: "Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is false." |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "CLASSB_REGWEN", |
| shadowed: "true", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Enable escalation mechanisms (accumulation and |
| interrupt timeout) for Class B. Note that interrupts can fire |
| regardless of whether the escalation mechanisms are enabled for |
| this class or not. |
| ''', |
| } |
| { bits: "1", |
| name: "LOCK", |
| desc: ''' |
| Enable automatic locking of escalation counter for class B. |
| If true, there is no way to stop the escalation protocol for class B |
| once it has been triggered. |
| ''' |
| } |
| { bits: "2", |
| name: "EN_E0", |
| resval: 1, |
| desc: "Enable escalation signal 0 for Class B", |
| } |
| { bits: "3", |
| name: "EN_E1", |
| resval: 1, |
| desc: "Enable escalation signal 1 for Class B", |
| } |
| { bits: "4", |
| name: "EN_E2", |
| resval: 1, |
| desc: "Enable escalation signal 2 for Class B", |
| } |
| { bits: "5", |
| name: "EN_E3", |
| resval: 1, |
| desc: "Enable escalation signal 3 for Class B", |
| } |
| { bits: "7:6", |
| name: "MAP_E0", |
| resval: 0, |
| desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", |
| } |
| { bits: "9:8", |
| name: "MAP_E1", |
| resval: 1, |
| desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", |
| } |
| { bits: "11:10", |
| name: "MAP_E2", |
| resval: 2, |
| desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", |
| } |
| { bits: "13:12", |
| name: "MAP_E3", |
| resval: 3, |
| desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", |
| } |
| ] |
| }, |
| { name: "CLASSB_CLR_REGWEN", |
| desc: ''' |
| Clear enable for escalation protocol of Class B alerts. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "hwo", |
| fields: [ |
| { bits: "0", |
| desc: '''Register defaults to true, can only be cleared. This register is set |
| to false by the hardware if the escalation protocol has been triggered and the bit |
| !!CLASSB_CTRL_SHADOWED.LOCK is true. |
| ''', |
| resval: 1, |
| } |
| ], |
| tags: [// The value of this register is set to false only by hardware, under the condition |
| // that escalation is triggered and the corresponding lock bit is true |
| // Cannot not be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSB_CLR_SHADOWED", |
| desc: ''' |
| Clear for escalation protocol of Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| hwqe: "true", |
| shadowed: "true", |
| regwen: "CLASSB_CLR_REGWEN", |
| fields: [ |
| { bits: "0", |
| desc: '''Writing 1 to this register clears the accumulator and aborts escalation |
| (if it has been triggered). This clear is disabled if !!CLASSB_CLR_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSB_ACCUM_CNT", |
| desc: ''' |
| Current accumulation value for alert Class B. Software can clear this register |
| with a write to !!CLASSB_CLR_SHADOWED register unless !!CLASSB_CLR_REGWEN is false. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "AccuCntDw-1:0" } |
| ], |
| tags: [// The value of this register is determined by how many alerts have been triggered |
| // Cannot be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSB_ACCUM_THRESH_SHADOWED", |
| desc: ''' |
| Accumulation threshold value for alert Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "AccuCntDw-1:0", |
| desc: '''Once the accumulation value register is equal to the threshold escalation will |
| be triggered on the next alert occurrence within this class B begins. Note that this |
| register can not be modified if !!CLASSB_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSB_TIMEOUT_CYC_SHADOWED", |
| desc: ''' |
| Interrupt timeout in cycles. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''If the interrupt corresponding to this class is not |
| handled within the specified amount of cycles, escalation will be triggered. |
| Set to a positive value to enable the interrupt timeout for Class B. The timeout is set to zero |
| by default, which disables this feature. Note that this register can not be modified if |
| !!CLASSB_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSB_CRASHDUMP_TRIGGER_SHADOWED", |
| desc: ''' |
| Crashdump trigger configuration for Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| resval: "0", |
| fields: [ |
| { bits: "PHASE_DW-1:0", |
| desc: ''' |
| Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation |
| timer states. It is recommended to capture the crashdump upon entering the first escalation phase |
| that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order |
| to prevent spurious alert events from masking the original alert causes. |
| Note that this register can not be modified if !!CLASSB_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSB_PHASE0_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 0 for Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSB_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSB_PHASE1_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 1 for Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSB_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSB_PHASE2_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 2 for Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSB_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSB_PHASE3_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 3 for Class B. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSB_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSB_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSB_ESC_CNT", |
| desc: ''' |
| Escalation counter in cycles for Class B. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''Returns the current timeout or escalation count (depending on !!CLASSB_STATE). |
| This register can not be directly cleared. However, SW can indirectly clear as follows. |
| |
| If the class is in the Timeout state, the timeout can be aborted by clearing the |
| corresponding interrupt bit. |
| |
| If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be |
| aborted by writing to !!CLASSB_CLR_SHADOWED. Note however that has no effect if !!CLASSB_REGWEN |
| is set to false (either by SW or by HW via the !!CLASSB_CTRL_SHADOWED.LOCK feature). |
| ''' |
| } |
| ], |
| tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted |
| // Cannot be auto-predicted so excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSB_STATE", |
| desc: ''' |
| Current escalation state of Class B. See also !!CLASSB_ESC_CNT. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "2:0", |
| enum: [ |
| { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, |
| { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, |
| { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, |
| { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, |
| { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, |
| { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, |
| { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, |
| { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } |
| ] |
| } |
| ], |
| tags: [// The current escalation state cannot be auto-predicted |
| // so this register is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| |
| { name: "CLASSC_REGWEN", |
| desc: ''' |
| Lock bit for Class C configuration. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| desc: ''' |
| Class configuration enable bit. |
| If this is cleared to 0, the corresponding class configuration |
| registers cannot be written anymore. |
| ''', |
| resval: 1, |
| } |
| ] |
| }, |
| { name: "CLASSC_CTRL_SHADOWED", |
| desc: "Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is false." |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "CLASSC_REGWEN", |
| shadowed: "true", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Enable escalation mechanisms (accumulation and |
| interrupt timeout) for Class C. Note that interrupts can fire |
| regardless of whether the escalation mechanisms are enabled for |
| this class or not. |
| ''', |
| } |
| { bits: "1", |
| name: "LOCK", |
| desc: ''' |
| Enable automatic locking of escalation counter for class C. |
| If true, there is no way to stop the escalation protocol for class C |
| once it has been triggered. |
| ''' |
| } |
| { bits: "2", |
| name: "EN_E0", |
| resval: 1, |
| desc: "Enable escalation signal 0 for Class C", |
| } |
| { bits: "3", |
| name: "EN_E1", |
| resval: 1, |
| desc: "Enable escalation signal 1 for Class C", |
| } |
| { bits: "4", |
| name: "EN_E2", |
| resval: 1, |
| desc: "Enable escalation signal 2 for Class C", |
| } |
| { bits: "5", |
| name: "EN_E3", |
| resval: 1, |
| desc: "Enable escalation signal 3 for Class C", |
| } |
| { bits: "7:6", |
| name: "MAP_E0", |
| resval: 0, |
| desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", |
| } |
| { bits: "9:8", |
| name: "MAP_E1", |
| resval: 1, |
| desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", |
| } |
| { bits: "11:10", |
| name: "MAP_E2", |
| resval: 2, |
| desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", |
| } |
| { bits: "13:12", |
| name: "MAP_E3", |
| resval: 3, |
| desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", |
| } |
| ] |
| }, |
| { name: "CLASSC_CLR_REGWEN", |
| desc: ''' |
| Clear enable for escalation protocol of Class C alerts. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "hwo", |
| fields: [ |
| { bits: "0", |
| desc: '''Register defaults to true, can only be cleared. This register is set |
| to false by the hardware if the escalation protocol has been triggered and the bit |
| !!CLASSC_CTRL_SHADOWED.LOCK is true. |
| ''', |
| resval: 1, |
| } |
| ], |
| tags: [// The value of this register is set to false only by hardware, under the condition |
| // that escalation is triggered and the corresponding lock bit is true |
| // Cannot not be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSC_CLR_SHADOWED", |
| desc: ''' |
| Clear for escalation protocol of Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| hwqe: "true", |
| shadowed: "true", |
| regwen: "CLASSC_CLR_REGWEN", |
| fields: [ |
| { bits: "0", |
| desc: '''Writing 1 to this register clears the accumulator and aborts escalation |
| (if it has been triggered). This clear is disabled if !!CLASSC_CLR_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSC_ACCUM_CNT", |
| desc: ''' |
| Current accumulation value for alert Class C. Software can clear this register |
| with a write to !!CLASSC_CLR_SHADOWED register unless !!CLASSC_CLR_REGWEN is false. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "AccuCntDw-1:0" } |
| ], |
| tags: [// The value of this register is determined by how many alerts have been triggered |
| // Cannot be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSC_ACCUM_THRESH_SHADOWED", |
| desc: ''' |
| Accumulation threshold value for alert Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "AccuCntDw-1:0", |
| desc: '''Once the accumulation value register is equal to the threshold escalation will |
| be triggered on the next alert occurrence within this class C begins. Note that this |
| register can not be modified if !!CLASSC_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSC_TIMEOUT_CYC_SHADOWED", |
| desc: ''' |
| Interrupt timeout in cycles. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''If the interrupt corresponding to this class is not |
| handled within the specified amount of cycles, escalation will be triggered. |
| Set to a positive value to enable the interrupt timeout for Class C. The timeout is set to zero |
| by default, which disables this feature. Note that this register can not be modified if |
| !!CLASSC_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSC_CRASHDUMP_TRIGGER_SHADOWED", |
| desc: ''' |
| Crashdump trigger configuration for Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| resval: "0", |
| fields: [ |
| { bits: "PHASE_DW-1:0", |
| desc: ''' |
| Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation |
| timer states. It is recommended to capture the crashdump upon entering the first escalation phase |
| that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order |
| to prevent spurious alert events from masking the original alert causes. |
| Note that this register can not be modified if !!CLASSC_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSC_PHASE0_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 0 for Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSC_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSC_PHASE1_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 1 for Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSC_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSC_PHASE2_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 2 for Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSC_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSC_PHASE3_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 3 for Class C. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSC_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSC_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSC_ESC_CNT", |
| desc: ''' |
| Escalation counter in cycles for Class C. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''Returns the current timeout or escalation count (depending on !!CLASSC_STATE). |
| This register can not be directly cleared. However, SW can indirectly clear as follows. |
| |
| If the class is in the Timeout state, the timeout can be aborted by clearing the |
| corresponding interrupt bit. |
| |
| If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be |
| aborted by writing to !!CLASSC_CLR_SHADOWED. Note however that has no effect if !!CLASSC_REGWEN |
| is set to false (either by SW or by HW via the !!CLASSC_CTRL_SHADOWED.LOCK feature). |
| ''' |
| } |
| ], |
| tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted |
| // Cannot be auto-predicted so excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSC_STATE", |
| desc: ''' |
| Current escalation state of Class C. See also !!CLASSC_ESC_CNT. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "2:0", |
| enum: [ |
| { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, |
| { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, |
| { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, |
| { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, |
| { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, |
| { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, |
| { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, |
| { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } |
| ] |
| } |
| ], |
| tags: [// The current escalation state cannot be auto-predicted |
| // so this register is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| |
| { name: "CLASSD_REGWEN", |
| desc: ''' |
| Lock bit for Class D configuration. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "none", |
| fields: [ |
| { bits: "0", |
| desc: ''' |
| Class configuration enable bit. |
| If this is cleared to 0, the corresponding class configuration |
| registers cannot be written anymore. |
| ''', |
| resval: 1, |
| } |
| ] |
| }, |
| { name: "CLASSD_CTRL_SHADOWED", |
| desc: "Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is false." |
| swaccess: "rw", |
| hwaccess: "hro", |
| regwen: "CLASSD_REGWEN", |
| shadowed: "true", |
| fields: [ |
| { bits: "0", |
| name: "EN", |
| desc: ''' |
| Enable escalation mechanisms (accumulation and |
| interrupt timeout) for Class D. Note that interrupts can fire |
| regardless of whether the escalation mechanisms are enabled for |
| this class or not. |
| ''', |
| } |
| { bits: "1", |
| name: "LOCK", |
| desc: ''' |
| Enable automatic locking of escalation counter for class D. |
| If true, there is no way to stop the escalation protocol for class D |
| once it has been triggered. |
| ''' |
| } |
| { bits: "2", |
| name: "EN_E0", |
| resval: 1, |
| desc: "Enable escalation signal 0 for Class D", |
| } |
| { bits: "3", |
| name: "EN_E1", |
| resval: 1, |
| desc: "Enable escalation signal 1 for Class D", |
| } |
| { bits: "4", |
| name: "EN_E2", |
| resval: 1, |
| desc: "Enable escalation signal 2 for Class D", |
| } |
| { bits: "5", |
| name: "EN_E3", |
| resval: 1, |
| desc: "Enable escalation signal 3 for Class D", |
| } |
| { bits: "7:6", |
| name: "MAP_E0", |
| resval: 0, |
| desc: "Determines in which escalation phase escalation signal 0 shall be asserted.", |
| } |
| { bits: "9:8", |
| name: "MAP_E1", |
| resval: 1, |
| desc: "Determines in which escalation phase escalation signal 1 shall be asserted.", |
| } |
| { bits: "11:10", |
| name: "MAP_E2", |
| resval: 2, |
| desc: "Determines in which escalation phase escalation signal 2 shall be asserted.", |
| } |
| { bits: "13:12", |
| name: "MAP_E3", |
| resval: 3, |
| desc: "Determines in which escalation phase escalation signal 3 shall be asserted.", |
| } |
| ] |
| }, |
| { name: "CLASSD_CLR_REGWEN", |
| desc: ''' |
| Clear enable for escalation protocol of Class D alerts. |
| ''' |
| swaccess: "rw0c", |
| hwaccess: "hwo", |
| fields: [ |
| { bits: "0", |
| desc: '''Register defaults to true, can only be cleared. This register is set |
| to false by the hardware if the escalation protocol has been triggered and the bit |
| !!CLASSD_CTRL_SHADOWED.LOCK is true. |
| ''', |
| resval: 1, |
| } |
| ], |
| tags: [// The value of this register is set to false only by hardware, under the condition |
| // that escalation is triggered and the corresponding lock bit is true |
| // Cannot not be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSD_CLR_SHADOWED", |
| desc: ''' |
| Clear for escalation protocol of Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| hwqe: "true", |
| shadowed: "true", |
| regwen: "CLASSD_CLR_REGWEN", |
| fields: [ |
| { bits: "0", |
| desc: '''Writing 1 to this register clears the accumulator and aborts escalation |
| (if it has been triggered). This clear is disabled if !!CLASSD_CLR_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSD_ACCUM_CNT", |
| desc: ''' |
| Current accumulation value for alert Class D. Software can clear this register |
| with a write to !!CLASSD_CLR_SHADOWED register unless !!CLASSD_CLR_REGWEN is false. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "AccuCntDw-1:0" } |
| ], |
| tags: [// The value of this register is determined by how many alerts have been triggered |
| // Cannot be auto-predicted so it is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSD_ACCUM_THRESH_SHADOWED", |
| desc: ''' |
| Accumulation threshold value for alert Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "AccuCntDw-1:0", |
| desc: '''Once the accumulation value register is equal to the threshold escalation will |
| be triggered on the next alert occurrence within this class D begins. Note that this |
| register can not be modified if !!CLASSD_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSD_TIMEOUT_CYC_SHADOWED", |
| desc: ''' |
| Interrupt timeout in cycles. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''If the interrupt corresponding to this class is not |
| handled within the specified amount of cycles, escalation will be triggered. |
| Set to a positive value to enable the interrupt timeout for Class D. The timeout is set to zero |
| by default, which disables this feature. Note that this register can not be modified if |
| !!CLASSD_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSD_CRASHDUMP_TRIGGER_SHADOWED", |
| desc: ''' |
| Crashdump trigger configuration for Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| resval: "0", |
| fields: [ |
| { bits: "PHASE_DW-1:0", |
| desc: ''' |
| Determine in which escalation phase to capture the crashdump containing all alert cause CSRs and escalation |
| timer states. It is recommended to capture the crashdump upon entering the first escalation phase |
| that activates a countermeasure with many side-effects (e.g. life cycle state scrapping) in order |
| to prevent spurious alert events from masking the original alert causes. |
| Note that this register can not be modified if !!CLASSD_REGWEN is false. |
| ''' |
| } |
| ] |
| }, |
| { name: "CLASSD_PHASE0_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 0 for Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSD_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSD_PHASE1_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 1 for Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSD_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSD_PHASE2_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 2 for Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSD_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSD_PHASE3_CYC_SHADOWED", |
| desc: ''' |
| Duration of escalation phase 3 for Class D. |
| ''' |
| swaccess: "rw", |
| hwaccess: "hro", |
| shadowed: "true", |
| regwen: "CLASSD_REGWEN", |
| fields: [ |
| { bits: "EscCntDw-1:0" , |
| desc: '''Escalation phase duration in cycles. Note that this register can not be |
| modified if !!CLASSD_REGWEN is false.''' |
| } |
| ] |
| } |
| { name: "CLASSD_ESC_CNT", |
| desc: ''' |
| Escalation counter in cycles for Class D. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "EscCntDw-1:0", |
| desc: '''Returns the current timeout or escalation count (depending on !!CLASSD_STATE). |
| This register can not be directly cleared. However, SW can indirectly clear as follows. |
| |
| If the class is in the Timeout state, the timeout can be aborted by clearing the |
| corresponding interrupt bit. |
| |
| If this class is in any of the escalation phases (e.g. Phase0), escalation protocol can be |
| aborted by writing to !!CLASSD_CLR_SHADOWED. Note however that has no effect if !!CLASSD_REGWEN |
| is set to false (either by SW or by HW via the !!CLASSD_CTRL_SHADOWED.LOCK feature). |
| ''' |
| } |
| ], |
| tags: [// The value of this register is determined by counting how many cycles the escalation phase has lasted |
| // Cannot be auto-predicted so excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| { name: "CLASSD_STATE", |
| desc: ''' |
| Current escalation state of Class D. See also !!CLASSD_ESC_CNT. |
| ''' |
| swaccess: "ro", |
| hwaccess: "hwo", |
| hwext: "true", |
| fields: [ |
| { bits: "2:0", |
| enum: [ |
| { value: "0b000", name: "Idle", desc: "No timeout or escalation triggered." }, |
| { value: "0b001", name: "Timeout", desc: "IRQ timeout counter is active." }, |
| { value: "0b010", name: "FsmError", desc: "Terminal error state if FSM has been glitched." }, |
| { value: "0b011", name: "Terminal", desc: "Terminal state after escalation protocol." }, |
| { value: "0b100", name: "Phase0", desc: "Escalation Phase0 is active." }, |
| { value: "0b101", name: "Phase1", desc: "Escalation Phase1 is active." }, |
| { value: "0b110", name: "Phase2", desc: "Escalation Phase2 is active." }, |
| { value: "0b111", name: "Phase3", desc: "Escalation Phase3 is active." } |
| ] |
| } |
| ], |
| tags: [// The current escalation state cannot be auto-predicted |
| // so this register is excluded from read check |
| "excl:CsrNonInitTests:CsrExclWriteCheck"] |
| }, |
| ], |
| } |
