hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson - 3p/lowrisc/opentitan - Git at Google

 // Copyright lowRISC contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 {
   name: "sysrst_ctrl"
   import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
                      "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
                      "sysrst_ctrl_sec_cm_testplan.hjson"]
   testpoints: [
     {
       name: smoke
       desc: '''
             Verify end to end data transfer in normal operation mode.

             * Write a random data to the input keys.
             * Read the data at the output pins and compare it with the input data.
             '''
       stage: V1
       tests: ["sysrst_ctrl_smoke"]
     }

     {
       name: input_output_inverted
       desc: '''
             Verify end to end data transfer with inverted input and inverted output.

             * Write a random data to the input keys.
             * Randomly configure KEY_INVERT_CTL to invert or not invert inputs and outputs.
             * In case of no inversions or inverting both check that input matches output.
             * In case where the input is inverted but not the output or the other way around check that input does not match output.
             '''
       stage: V1
       tests: ["sysrst_ctrl_in_out_inverted"]
     }

     {
       name: combo_detect_ec_rst
       desc: '''
             Verify the combo detection with ec_rst action.

             * Set the input keys by configuring COM_SEL_CTL_0 register.
             * Set the combo duration via the COM_DET_CTL_0 register.
             * Select the action to be taken by configuring COM_OUT_CTL_0 register.
             * Set the pulse width via EC_RST_CTL register only to raise ec_rst action.
             * Drive the input with a randomized delay.
             * Read the COMBO_INTR_STATUS register.
               In case the input was driven for longer than the debounce delay, check if the interrupt is raised and clear the interrupt.
             '''
       stage: V1
       tests: ["sysrst_ctrl_combo_detect_ec_rst"]
     }

     {
       name: combo_detect_ec_rst_with_pre_cond
       desc: '''
             Verify the pre-condition for combo detection.

             * Define `pwrb_in == 0` as a pre-condition by writing the COM_PRE_SEL_CTL_0 register
               with value 'h8.
             * Set the pre-condition duration time via the `COM_PRE_DET_CTL` register.
             * Wait for the pre-condition to be satisfied.
             * Trigger the combo_detect_ec_rst sequence.
             * NOTE: This is a directed test with no random values for V1 stage,
               further this test will be randomized.
             '''
       stage: V1
       tests: ["sysrst_ctrl_combo_detect_ec_rst_with_pre_cond"]
     }

     {
       name: combo_detect
       desc: '''
             Verify the combo detection with random action.

             * Randomly set the input keys by configuring COM_SEL_CTL_0-3 register.
             * Set the random combo duration via the COM_DET_CTL_0-3 register.
             * Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
             * Set the pulse width via EC_RST_CTL register.
             * Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
               Clear the interrupt in case it was raised.
             '''
       stage: V2
       tests: ["sysrst_ctrl_combo_detect"]
     }

     {
       name: combo_detect_with_pre_cond
       desc: '''
             Verify the combo detection with random action and precondition.

             * Randomly set the input keys combination as precondition by configuring COM_PRE_SEL_CTL_0-3 register.
             * Randomly set the input keys combination for combo detection by configuring COM_SEL_CTL_0-3 register.
             * Set the random combo precondition duration via the COM_PRE_DET_CTL_0-3 register.
             * Set the random combo duration via the COM_DET_CTL_0-3 register.
             * Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
             * Set the pulse width via EC_RST_CTL register.
             * Randomly set the input keys, such that precondition and subsequent combo detection logic are activated randomly.
             * Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
               Clear the interrupt in case it was raised.
             * Check for bat_disable, rst_req or wake_up_o assertion depending on COM_OUT_CTL_0-3 register
             '''
       stage: V2
       tests: ["sysrst_ctrl_combo_detect_with_pre_cond"]
     }

     {
       name: auto_block_key_outputs
       desc: '''
             Verify the auto block key output feature.

             * Trigger the input keys combo.
             * Set the debounce timer value in AUTO_BLOCK_DEBOUNCE_CTL register.
             * Select the output override value by configuring AUTO_BLOCK_OUT_CTL register.
             * Check whether the input keys stays low for the selected debounce time.
             * Read the AUTO_BLOCK_OUT_CTL register to check if the output key is overridden.
             '''
       stage: V2
       tests: ["sysrst_ctrl_auto_blk_key_output"]
     }

     {
       name: keyboard_input_triggered_interrupt
       desc: '''
             Verify the keyboard and input triggered interrupt feature by detecting the edge
             transitions on input pins.

             * Set the input signals and edge transition by configuring KEY_INTR_CTL register.
             * Set the debounce timer value via KEY_INTR_DEBOUNCE_CTL register.
             * Read the KEY_INTR_STATUS register to check if the interrupt caused and clear the interrupt.
             '''
       stage: V2
       tests: ["sysrst_ctrl_edge_detect"]
     }

     {
       name: pin_output_keyboard_inversion_control
       desc: '''
             Verify the keyboard inversion feature by override logic.

             * Select the output signals to override via PIN_OUT_CTL register.
             * Allow the output signals to override the value via PIN_ALLOWED_CTL register.
             * Set the override value to the output signal via PIN_OUT_VALUE register.
             * Check whether the override happens correctly.
             '''
       stage: V2
       tests: ["sysrst_ctrl_pin_override_test"]
     }

     {
       name: pin_input_value_accessibility
       desc: '''
             Verify the pin input value accessibilty.

             * Trigger the key[0,1,2], ac_present_in, pwrb_in, ec_rst_in_l input pins with random values.
             * Read the PIN_IN_VALUE register and check if the read value is same as input value.
             '''
       stage: V2
       tests: ["sysrst_ctrl_pin_access_test"]
     }

     {
       name: ec_power_on_reset
       desc: '''
             Verify the EC and power on reset.

             * Disable EC reset override.
             * Set EC reset timer to stretch reset.
             * Make sure ec_rst_out_l is asserted even after OpenTitan reset is released.
             * Set PIN_OUT_CTL.EC_RST_L to 0 to release the ec_rst_out_l reset.
             '''
       stage: V2
       tests: ["sysrst_ctrl_ec_pwr_on_rst"]
     }

     {
       name: flash_write_protect_output
       desc: '''
             Verify the flash write protect.

             * Make sure flash_wp_out_l signal is asserted low by reading PIN_OUT_CTL.flash_wp_l.
             * Enable the override function by setting PIN_OUT_CTL.FLASH_WP_L to value 1.
             * Randomize the corresponding flash_wp_l_i input pin.
             * Check flash_wp_l_i does not have a bypass path to flash_wp_l_o.
             * Check if flash_wp_l_o is released only by the override function.
             '''
       stage: V2
       tests: ["sysrst_ctrl_flash_wr_prot_out"]
     }

     {
       name: ultra_low_power_test
       desc: '''
             Verify the ultra low power feature.

             * Configure ULP_AC_DEBOUNCE_CTL, ULP_LID_DEBOUNCE_CTL and ULP_PWRB_DEBOUNCE_CTL register to set the debounce timer value.
             * Disable the bus clock to check detection logic works in sleep mode.
             * Trigger the ac_present_i, lid_open_in and ec_rst_l_i input keys.
             * Turn on the bus clock to read the status register.
             * Read the WKUP_STATUS register to check if the event has occured.
             * Read the ULP_STATUS register and check if the ultra low power wakeup event is detected.
             '''
       stage: V2
       tests: ["sysrst_ctrl_ultra_low_pwr"]
     }

     {
       name: stress_all
       desc: '''
             Test all the sequences randomly in one sequence.

             * Combine above sequences in one test then randomly select for running.
             * All sequences should be finished and checked by the scoreboard.
       '''
       stage: V2
       tests: ["sysrst_ctrl_stress_all"]
     }
   ]

   covergroups: [
     {
       name: sysrst_ctrl_combo_detect_action_cg
       desc: '''
             Cover all the combo detect, combo_sel and combo_pre_sel actions.
             Create 4 instance to cover the combo detect register [0-3].
             Sample the covergroup when the event occurs.
             Cross the covergroup with combo_detect_sel_cg and combo_pre_sel_cg to cover all the input combination with
             all the possible combo_detect actions.
             '''
     }
     {
       name: sysrst_ctrl_combo_detect_det_cg
       desc: '''
             Cover the combo detect debounce timer.
             Create 4 instance to cover the combo detect register [0-3].
             '''
     }
     {
       name: sysrst_ctrl_combo_precondition_det_cg
       desc: '''
             Cover the combo detect precondition debounce timer.
             Create 4 instance to cover the combo detect precondition register [0-3].
             '''
     }
     {
       name: sysrst_ctrl_auto_block_debounce_ctl_cg
       desc: '''
             Cover the auto block enable/disable feature.
             Cover the auto block debounce timer.
             '''
     }
     {
       name: sysrst_ctrl_combo_intr_status_cg
       desc: '''
             Cover the combo detect status of all 4 set of combo registers.
             Cover all the input combinations has generated selected outcome actions and cross
             with the status generated.
             '''
     }
     {
       name: sysrst_ctrl_key_intr_status_cg
       desc: '''
             Cover the H2L/L2H edge detect event of all the inputs.
             '''
     }
     {
       name: sysrst_ctrl_ulp_status_cg
       desc: '''
             Cover the ultra low power event triggered.
             Cover the following condition triggers the ultra low power event:
             * High to low transition on pwrb_in input pin
             * Low to High transition on lid_open pin.
             * A level high on ac_present pin.
             Cross the above three condition with the ulp_status.
             '''
     }
     {
       name: sysrst_ctrl_wkup_event_cg
       desc: '''
             Cover the ultra low power wakeup event and status.
             Cover the wkup event could occur due to following condition:
             * High to low transition on pwrb_in input pin when ulp feature is enable.
             * Low to High transition on lid_open pin when ulp feature is enable.
             * A level high on ac_present pin when ulp feature is enable.
             * When an interrupt is generated.
             Cross the above condition with the wkup_status register.
             '''
     }
     {
       name: sysrst_ctrl_key_invert_ctl_cg
       desc: '''
             Cover the invert values of all input and output values.
             '''
     }
     {
       name: sysrst_ctrl_pin_in_value_cg
       desc: '''
             Cover the raw input values before inversion for all inputs.
             '''
     }
     {
       name: sysrst_ctrl_auto_blk_out_ctl_cg
       desc: '''
             Cover the auto blk input select and their values.
             Cross the key outputs selected to override with their override values.
             Sample the covergroup when the event occurs.
             '''
     }
     {
       name: pin_cfg_cg
       desc: '''
             Cover the override enable/disable of all the inputs.
             Cover the override values of all the input values.
             Cover the allowed value 0 and 1 of all the inputs.
             Cross all the above coverpoints.
             '''
     }
     {
       name: debounce_timer_cg
       desc: '''
             Cover the debounce timer of the following registers
             * ec_rst_ctl register.
             * key_intr_debounce_ctl register.
             * ulp_ac_debounce_ctl register.
             * ulp_pwrb_debounce_ctl register.
             * ulp_lid_debounce_ctl register.
             '''
     }
   ]
 }
	// Copyright lowRISC contributors.
	// Licensed under the Apache License, Version 2.0, see LICENSE for details.
	// SPDX-License-Identifier: Apache-2.0
	{
	name: "sysrst_ctrl"
	import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
	"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
	"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
	"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
	"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
	"sysrst_ctrl_sec_cm_testplan.hjson"]
	testpoints: [
	{
	name: smoke
	desc: '''
	Verify end to end data transfer in normal operation mode.

	* Write a random data to the input keys.
	* Read the data at the output pins and compare it with the input data.
	'''
	stage: V1
	tests: ["sysrst_ctrl_smoke"]
	}

	{
	name: input_output_inverted
	desc: '''
	Verify end to end data transfer with inverted input and inverted output.

	* Write a random data to the input keys.
	* Randomly configure KEY_INVERT_CTL to invert or not invert inputs and outputs.
	* In case of no inversions or inverting both check that input matches output.
	* In case where the input is inverted but not the output or the other way around check that input does not match output.
	'''
	stage: V1
	tests: ["sysrst_ctrl_in_out_inverted"]
	}

	{
	name: combo_detect_ec_rst
	desc: '''
	Verify the combo detection with ec_rst action.

	* Set the input keys by configuring COM_SEL_CTL_0 register.
	* Set the combo duration via the COM_DET_CTL_0 register.
	* Select the action to be taken by configuring COM_OUT_CTL_0 register.
	* Set the pulse width via EC_RST_CTL register only to raise ec_rst action.
	* Drive the input with a randomized delay.
	* Read the COMBO_INTR_STATUS register.
	In case the input was driven for longer than the debounce delay, check if the interrupt is raised and clear the interrupt.
	'''
	stage: V1
	tests: ["sysrst_ctrl_combo_detect_ec_rst"]
	}

	{
	name: combo_detect_ec_rst_with_pre_cond
	desc: '''
	Verify the pre-condition for combo detection.

	* Define `pwrb_in == 0` as a pre-condition by writing the COM_PRE_SEL_CTL_0 register
	with value 'h8.
	* Set the pre-condition duration time via the `COM_PRE_DET_CTL` register.
	* Wait for the pre-condition to be satisfied.
	* Trigger the combo_detect_ec_rst sequence.
	* NOTE: This is a directed test with no random values for V1 stage,
	further this test will be randomized.
	'''
	stage: V1
	tests: ["sysrst_ctrl_combo_detect_ec_rst_with_pre_cond"]
	}

	{
	name: combo_detect
	desc: '''
	Verify the combo detection with random action.

	* Randomly set the input keys by configuring COM_SEL_CTL_0-3 register.
	* Set the random combo duration via the COM_DET_CTL_0-3 register.
	* Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
	* Set the pulse width via EC_RST_CTL register.
	* Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
	Clear the interrupt in case it was raised.
	'''
	stage: V2
	tests: ["sysrst_ctrl_combo_detect"]
	}

	{
	name: combo_detect_with_pre_cond
	desc: '''
	Verify the combo detection with random action and precondition.

	* Randomly set the input keys combination as precondition by configuring COM_PRE_SEL_CTL_0-3 register.
	* Randomly set the input keys combination for combo detection by configuring COM_SEL_CTL_0-3 register.
	* Set the random combo precondition duration via the COM_PRE_DET_CTL_0-3 register.
	* Set the random combo duration via the COM_DET_CTL_0-3 register.
	* Randomly select the action to be taken by configuring COM_OUT_CTL_0-3 register.
	* Set the pulse width via EC_RST_CTL register.
	* Randomly set the input keys, such that precondition and subsequent combo detection logic are activated randomly.
	* Read the COMBO_INTR_STATUS register to check whether an interrupt is correctly raised for all the combinations.
	Clear the interrupt in case it was raised.
	* Check for bat_disable, rst_req or wake_up_o assertion depending on COM_OUT_CTL_0-3 register
	'''
	stage: V2
	tests: ["sysrst_ctrl_combo_detect_with_pre_cond"]
	}

	{
	name: auto_block_key_outputs
	desc: '''
	Verify the auto block key output feature.

	* Trigger the input keys combo.
	* Set the debounce timer value in AUTO_BLOCK_DEBOUNCE_CTL register.
	* Select the output override value by configuring AUTO_BLOCK_OUT_CTL register.
	* Check whether the input keys stays low for the selected debounce time.
	* Read the AUTO_BLOCK_OUT_CTL register to check if the output key is overridden.
	'''
	stage: V2
	tests: ["sysrst_ctrl_auto_blk_key_output"]
	}

	{
	name: keyboard_input_triggered_interrupt
	desc: '''
	Verify the keyboard and input triggered interrupt feature by detecting the edge
	transitions on input pins.

	* Set the input signals and edge transition by configuring KEY_INTR_CTL register.
	* Set the debounce timer value via KEY_INTR_DEBOUNCE_CTL register.
	* Read the KEY_INTR_STATUS register to check if the interrupt caused and clear the interrupt.
	'''
	stage: V2
	tests: ["sysrst_ctrl_edge_detect"]
	}

	{
	name: pin_output_keyboard_inversion_control
	desc: '''
	Verify the keyboard inversion feature by override logic.

	* Select the output signals to override via PIN_OUT_CTL register.
	* Allow the output signals to override the value via PIN_ALLOWED_CTL register.
	* Set the override value to the output signal via PIN_OUT_VALUE register.
	* Check whether the override happens correctly.
	'''
	stage: V2
	tests: ["sysrst_ctrl_pin_override_test"]
	}

	{
	name: pin_input_value_accessibility
	desc: '''
	Verify the pin input value accessibilty.

	* Trigger the key[0,1,2], ac_present_in, pwrb_in, ec_rst_in_l input pins with random values.
	* Read the PIN_IN_VALUE register and check if the read value is same as input value.
	'''
	stage: V2
	tests: ["sysrst_ctrl_pin_access_test"]
	}

	{
	name: ec_power_on_reset
	desc: '''
	Verify the EC and power on reset.

	* Disable EC reset override.
	* Set EC reset timer to stretch reset.
	* Make sure ec_rst_out_l is asserted even after OpenTitan reset is released.
	* Set PIN_OUT_CTL.EC_RST_L to 0 to release the ec_rst_out_l reset.
	'''
	stage: V2
	tests: ["sysrst_ctrl_ec_pwr_on_rst"]
	}

	{
	name: flash_write_protect_output
	desc: '''
	Verify the flash write protect.

	* Make sure flash_wp_out_l signal is asserted low by reading PIN_OUT_CTL.flash_wp_l.
	* Enable the override function by setting PIN_OUT_CTL.FLASH_WP_L to value 1.
	* Randomize the corresponding flash_wp_l_i input pin.
	* Check flash_wp_l_i does not have a bypass path to flash_wp_l_o.
	* Check if flash_wp_l_o is released only by the override function.
	'''
	stage: V2
	tests: ["sysrst_ctrl_flash_wr_prot_out"]
	}

	{
	name: ultra_low_power_test
	desc: '''
	Verify the ultra low power feature.

	* Configure ULP_AC_DEBOUNCE_CTL, ULP_LID_DEBOUNCE_CTL and ULP_PWRB_DEBOUNCE_CTL register to set the debounce timer value.
	* Disable the bus clock to check detection logic works in sleep mode.
	* Trigger the ac_present_i, lid_open_in and ec_rst_l_i input keys.
	* Turn on the bus clock to read the status register.
	* Read the WKUP_STATUS register to check if the event has occured.
	* Read the ULP_STATUS register and check if the ultra low power wakeup event is detected.
	'''
	stage: V2
	tests: ["sysrst_ctrl_ultra_low_pwr"]
	}

	{
	name: stress_all
	desc: '''
	Test all the sequences randomly in one sequence.

	* Combine above sequences in one test then randomly select for running.
	* All sequences should be finished and checked by the scoreboard.
	'''
	stage: V2
	tests: ["sysrst_ctrl_stress_all"]
	}
	]

	covergroups: [
	{
	name: sysrst_ctrl_combo_detect_action_cg
	desc: '''
	Cover all the combo detect, combo_sel and combo_pre_sel actions.
	Create 4 instance to cover the combo detect register [0-3].
	Sample the covergroup when the event occurs.
	Cross the covergroup with combo_detect_sel_cg and combo_pre_sel_cg to cover all the input combination with
	all the possible combo_detect actions.
	'''
	}
	{
	name: sysrst_ctrl_combo_detect_det_cg
	desc: '''
	Cover the combo detect debounce timer.
	Create 4 instance to cover the combo detect register [0-3].
	'''
	}
	{
	name: sysrst_ctrl_combo_precondition_det_cg
	desc: '''
	Cover the combo detect precondition debounce timer.
	Create 4 instance to cover the combo detect precondition register [0-3].
	'''
	}
	{
	name: sysrst_ctrl_auto_block_debounce_ctl_cg
	desc: '''
	Cover the auto block enable/disable feature.
	Cover the auto block debounce timer.
	'''
	}
	{
	name: sysrst_ctrl_combo_intr_status_cg
	desc: '''
	Cover the combo detect status of all 4 set of combo registers.
	Cover all the input combinations has generated selected outcome actions and cross
	with the status generated.
	'''
	}
	{
	name: sysrst_ctrl_key_intr_status_cg
	desc: '''
	Cover the H2L/L2H edge detect event of all the inputs.
	'''
	}
	{
	name: sysrst_ctrl_ulp_status_cg
	desc: '''
	Cover the ultra low power event triggered.
	Cover the following condition triggers the ultra low power event:
	* High to low transition on pwrb_in input pin
	* Low to High transition on lid_open pin.
	* A level high on ac_present pin.
	Cross the above three condition with the ulp_status.
	'''
	}
	{
	name: sysrst_ctrl_wkup_event_cg
	desc: '''
	Cover the ultra low power wakeup event and status.
	Cover the wkup event could occur due to following condition:
	* High to low transition on pwrb_in input pin when ulp feature is enable.
	* Low to High transition on lid_open pin when ulp feature is enable.
	* A level high on ac_present pin when ulp feature is enable.
	* When an interrupt is generated.
	Cross the above condition with the wkup_status register.
	'''
	}
	{
	name: sysrst_ctrl_key_invert_ctl_cg
	desc: '''
	Cover the invert values of all input and output values.
	'''
	}
	{
	name: sysrst_ctrl_pin_in_value_cg
	desc: '''
	Cover the raw input values before inversion for all inputs.
	'''
	}
	{
	name: sysrst_ctrl_auto_blk_out_ctl_cg
	desc: '''
	Cover the auto blk input select and their values.
	Cross the key outputs selected to override with their override values.
	Sample the covergroup when the event occurs.
	'''
	}
	{
	name: pin_cfg_cg
	desc: '''
	Cover the override enable/disable of all the inputs.
	Cover the override values of all the input values.
	Cover the allowed value 0 and 1 of all the inputs.
	Cross all the above coverpoints.
	'''
	}
	{
	name: debounce_timer_cg
	desc: '''
	Cover the debounce timer of the following registers
	* ec_rst_ctl register.
	* key_intr_debounce_ctl register.
	* ulp_ac_debounce_ctl register.
	* ulp_pwrb_debounce_ctl register.
	* ulp_lid_debounce_ctl register.
	'''
	}
	]
	}