This checklist is for Hardware Stage transitions for the Ibex Processor Core. All checklist items refer to the content in the Checklist.
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | SPEC_COMPLETE | Done | |
Documentation | CSR_DEFINED | Done | lowRISC/ibex#307 |
RTL | CLKRST_CONNECTED | Done | |
RTL | IP_TOP | Done | |
RTL | IP_INSTANTIABLE | Done | |
RTL | PHYSICAL_MACROS_DEFINED_80 | N/A | |
RTL | FUNC_IMPLEMENTED | Done | |
RTL | ASSERT_KNOWN_ADDED | Done | |
Code Quality | LINT_SETUP | Done |
PHYSICAL_MACROS_DEFINED_80 is waived as Ibex doesn't have memories inside.
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | NEW_FEATURES | N/A | |
Documentation | BLOCK_DIAGRAM | Done | |
Documentation | DOC_INTERFACE | Done | |
Documentation | DOC_INTEGRATION_GUIDE | Waived | This checklist item has been added retrospectively. |
Documentation | MISSING_FUNC | N/A | |
Documentation | FEATURE_FROZEN | Done | |
RTL | FEATURE_COMPLETE | Done | |
RTL | PORT_FROZEN | Done | |
RTL | ARCHITECTURE_FROZEN | Done | |
RTL | REVIEW_TODO | Done | Minor TODOs remain, waived |
RTL | STYLE_X | Done | will be reworked (#366) |
RTL | CDC_SYNCMACRO | Done | |
Code Quality | LINT_PASS | Done | Lint waivers created, not finalized |
Code Quality | CDC_SETUP | Waived | No block-level flow available - waived to top-level signoff. |
Code Quality | RDC_SETUP | Waived | No block-level flow available - waived to top-level signoff. |
Code Quality | AREA_CHECK | Done | Area smoke check done (on FPGA) |
Code Quality | TIMING_CHECK | Done | FPGA timing acceptable |
Security | SEC_CM_DOCUMENTED | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Security | SEC_CM_ASSETS_LISTED | Done | |
Security | SEC_CM_IMPLEMENTED | Done | |
Security | SEC_CM_RND_CNST | Done | |
Security | SEC_CM_NON_RESET_FLOPS | Done | |
Security | SEC_CM_SHADOW_REGS | Done | |
Security | SEC_CM_RTL_REVIEWED | Done | |
Security | SEC_CM_COUNCIL_REVIEWED | Done |
Type | Item | Resolution | Note/Collaterals |
---|---|---|---|
Documentation | NEW_FEATURES_D3 | Not Started | |
RTL | TODO_COMPLETE | Not Started | |
Code Quality | LINT_COMPLETE | Not Started | |
Code Quality | CDC_COMPLETE | Not Started | |
Code Quality | RDC_COMPLETE | Not Started | |
Review | REVIEW_RTL | Not Started | |
Review | REVIEW_DELETED_FF | Not Started | |
Review | REVIEW_SW_CHANGE | Not Started | |
Review | REVIEW_SW_ERRATA | Not Started |
Ibex verification is tracked in the Ibex documentation. Ibex is at V2S.
Features specific to rv_core_ibex do not have block-level verification. Top-level testing suffices for these, see the rv_core_ibex DV document for more details.
The V1 checklist may be found in the Ibex documentation.
The V2 checklist may be found in the Ibex documentation.
The V2S checklist may be found in the Ibex documentation.
The V3 checklist may be found in the Ibex documentation.