)]}'
{
  "commit": "ee3b976e2bd2fea9c2e4d09705969218bbdd2af6",
  "tree": "360bd620021d3eeed07db31c8c83d4850c067ae3",
  "parents": [
    "0d62c3c104417b714d6713444d2bef4815be9709"
  ],
  "author": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Thu Apr 01 11:49:50 2021 -0700"
  },
  "committer": {
    "name": "Eunchan Kim",
    "email": "eunchan@opentitan.org",
    "time": "Tue Apr 06 13:05:14 2021 -0700"
  },
  "message": "[spi_device] Add more syn constraints\n\n- Defined false_path from csb to any output to host systems\n- Defined input/output clock to use later (half-clock constraints)\n\nSigned-off-by: Eunchan Kim \u003ceunchan@opentitan.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "52fabaae39e5fc95ea98cc604ac8543730927301",
      "old_mode": 33188,
      "old_path": "hw/ip/spi_device/rtl/spi_device.sv",
      "new_id": "8ff0fd98962660d3fd31ce5ac422de4e71be24f3",
      "new_mode": 33188,
      "new_path": "hw/ip/spi_device/rtl/spi_device.sv"
    },
    {
      "type": "modify",
      "old_id": "f6450bd313028407738901da55a1c422cee54008",
      "old_mode": 33188,
      "old_path": "hw/top_earlgrey/syn/asic.constraints.sdc",
      "new_id": "84ac04b67796f58d7ff0e1ec45f5dc644fc21f30",
      "new_mode": 33188,
      "new_path": "hw/top_earlgrey/syn/asic.constraints.sdc"
    }
  ]
}