2019-10-07 Philipp Wagner <phw@lowrisc.org>
    * When executing the test suite, Ibex always writes an instruction
      log. Update the Makefile to write it to a test-specific location
      (next to all other log files).
    * On Ibex, provide an additional .objdump-noalias disassembly file
      with no aliases and numeric register names (instead of ABI names).
      This file matches the Ibex trace and can be used to debug the test
      runs.

2019-08-29 Robert Balas <balasr@iis.ee.ethz.ch>
    * Added support for using RI5CY as a target.
    * Added subdirectory riscv-target/ri5cy

2019-08-08 Lee Moore <moore@imperas.com>
    * Added support for lowRISC/ibex RTL as a target using Verilator.
      In conjunction with Philipp Wagner of lowRISC phw@lowrisc.org

2019-07-18 Paul Donahue <pdonahue@ventanamicro.com>
    * Fix typos/grammar and use correct architectural terms.

2019-06-21 Ben Selfridge <benselfridge@galois.com>
    * Added support for using the the GRIFT simulator as a target.
    * Added subdirectory riscv-target/grift
    * updated README.md and doc/README.adoc

2019-05-23 Prashanth Mundkur <prashanth.mundkur@gmail.com>
    * Added support and instructions for using the C and OCaml simulators from the Sail RISC-V formal model as targets.
	* added subdirectories riscv-target/sail-riscv-c and riscv-target/sail-riscv-ocaml
	* updated README.md and doc/README.adoc

2019-04-05 Allen Baum <allen.baum@esperantotech.com>
    * spec/TestFormatSpec.adoc:  Adding details, minor corrections, ToBeDiscussed
      items and clarifications to the specification of the future compliance test
      suite. Also removing restrictions on having absolate addresses in signature

2019-02-21 Lee Moore <moore@imperas.com>
    * Fixed     bug in RVTEST_IO_ASSERT_GPR_EQ which was not preserving register t0
    * Corrected commit I-LUI-01.S, register target changed but missed assertion

2019-02-21 Deborah Soung <debs@sifive.com>
    * added RiscvFormalSpec as a target with its own unique environment

2019-02-15 Radek Hajek <radek.hajek@codasip.com>
    * updated rv32i tests to support all registers (x31) with assertions
    * updated spec/TestFormatSpec.adoc example ISA test with new assertions

2019-02-05 Deborah Soung <debs@sifive.com>
    * [Issue #33] fixing rv32si/ma_fetch.S test
    * [Issue #32] fixing breakpoint test

2019-02-01 Lee Moore <moore@imperas.com>
    * updated Infrastructure macros to support non-volatile registers
    * updated riscvOVPsim

2019-01-29 Deborah Soung <debs@sifive.com>
    * Added Rocket Chip generated cores as a target
        * riscv-target/rocket/compliance_io.h created
	* riscv-target/rocket/compliance_test.h created
	* riscv-target/rocket/*/Makefile.include created for existing test suites
	* README.adoc updated with instructions for using Rocket cores as targets
	
2019-01-22 Premysl Vaclavik  <pvaclavik@codasip.com>
    * feature: initial version of Compliance Test Format Specification
        * This new document outlines how we should like the compliance
          system to work going forward. By contrast the doc/README.adoc file
          describes the current system as it is.
        * Approved at Compliance TG meeting of 9 Jan 2019.

2019-01-02 Radek Hajek <radek.hajek@codasip.com>
    * unified macros in all compliance tests

2018-12-20 Lee Moore <moore@imperas.com>
    * fixed riscvOVPsim 

2018-11-22 Simon Davidmann <simond@imperas.com>
    * added information on test suite status
    
2018-11-21 Olof Kindgren <olof.kindgren@gmail.com>
    * Added support for using external target directories with $TARGETDIR

2018-11-21 Neel Gala <neelgala@incoresemi.com>
   	* riscv-test-suite/rv_/references/_.reference_output: changed signature 
	  format for all tests to include only 4-bytes per line starting with the
  	  most significant byte on the left.
    	* riscv-target/spike/device/rv_/Makefile.include: Added a patch for 
	  spike-device Makefiles where the old-signature format is post-processed 
      	  to generate a signature in the new format at the end of each test.
	* riscv-target/riscvOVPsim/device/rv_/Makefile.include: same patch as above.
    	* Makefile: default target for Makefile is now to run all tests supported by 
	  the target mentioned defined by RISCV_TARGET variable.

2018-10-11 Simon Davidmann <simond@imperas.com>
    * Ported github riscv/riscv-tests for RV32 processors to this compliance env
    * rv32ua rv32uc rv32ud rv32uf rv32ud rv32ui

2018-09-10  Lee Moore  <moore@imperas.com>
	* Added tests to RV32I to improve coverage, usage of Imperas Mutating Fault Simulator to 
	  identify untested usage cases
	* Macro renames to support GPR, (S)FPR, (D)FPR
	* Added test suite RV32IM to test 32 bit Multiply and Divide instructions 
	* Added test suite RV32IMC to test 32 bit Compressed instructions
	* Added test suite RV64I to test 64 bit Integer instructions
	* Added test suite RV64IM to test 64 bit Multiply and Divide instructions 
	
	
2018-06-15  Radek Hajek  <hajek@codasip.com>

	Modifications to support Codasip simulator.

	The simulator is renamed as Codasip-simulator (was
	Codasip-IA-simulator), compliance_test.h has been moved to target
	directories and a COMPILE_TARGET has been added to Makefile to
	allow use of LLVM.

	* Makefile: Include Codasip simulator target.
	* riscv-target/codasip-IA-simulator/compliance_io.h: Renamed as
	riscv-target/Codasip-simulator/compliance_io.h.
	* riscv-target/Codasip-simulator/compliance_io.h: Renamed from
	riscv-target/codasip-IA-simulator/compliance_io.
	* riscv-target/Codasip-simulator/compliance_test.h: Created.
	* riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include:
	Renamed as
	riscv-target/Codasip-simulator/device/rv32i/Makefile.include
	* riscv-target/Codasip-simulator/device/rv32i/Makefile.include:
	Renamed from
	riscv-target/codasip-IA-simulator/device/rv32i/Makefile.include.
	* riscv-test-env/compliance_test.h: Renamed as
	riscv-target/riscvOVPsim/compliance_test.h.
	* riscv-target/riscvOVPsim/compliance_test.h: Renamed from
	riscv-test-env/compliance_test.h.
	* riscv-target/riscvOVPsim/device/rv32i/Makefile.include: Updated
	for new environment.
	* riscv-target/spike/compliance_test.h: Created.
	* riscv-target/spike/device/rv32i/Makefile.include: Updated for
	new environment.
	* riscv-test-suite/rv32i/Makefile: Likewise.

2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	Put placeholders in empty directories to make sure they show in
	the GitHub hierarchy.

	* riscv-test-suite/rv32i/.gitignore: Created.
	* riscv-test-suite/rv32m/.gitignore: Created.

2018-06-10  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* README.md: Make references to files in the repo into links.

2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* .gitignore: Ignore editor backup files.

2018-06-09  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* README.md: Add better link to documentation README.md.

2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* README.md: Move AsciiDoc details into new README.md in the doc
	directory.

2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* README.md: Fix typo in link to AsciiDoc cheat sheet

2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* COPYING.BSD: Created.
	* COPYING.CC: Created.
	* README.md: Add git process, licensing and engineering process.

2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	* README.md: Correct details for running the compliance tests and
	directory for OVPsim.

2018-06-08  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	Clean restructuring to just the work of interest.

	* thought-experiments: Directory removed.
	* .gitignore: Merged with TestStructure/.gitignore
	* Makefile: Renamed from TestStructure/Makefile.
	* TestStructure/Makefile: Renamed as Makefile.
	* README.md: Merged with TestStructure/README.md.
	* TestStructure/.gitignore: Deleted and contents moved into
	.gitignore.
	* TestStructure/README.md: Deleted and contents moved into
	README.md.
	* TestStructure/doc: Directory deleted.
	* TestStructure/riscv-target: Directory moved to riscv-target.
	* riscv-target: Directory moved from TestStructure/riscv-target
	* TestStructure/riscv-test-env: Directory moved to riscv-test-env.
	* riscv-test-env: Directory moved from
	TestStructure/riscv-test-env.
	* TestStructure/riscv-test-suite: Directory moved to
	riscv-test-suite.
	* riscv-test-suite: Directory moved from
	TestStructure/riscv-test-suite.
	* thought-experiments: Directory deleted.

2018-05-21  Jeremy Bennett  <jeremy.bennett@embecosm.com>

	Initial commit to populate the repository.

	* ChangeLog: Created.
	* README.md: Created.