// Generated register defines for PADCTRL

// Copyright information found in source file:
// Copyright lowRISC contributors.

// Licensing information found in source file:
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0

#ifndef _PADCTRL_REG_DEFS_
#define _PADCTRL_REG_DEFS_

// Register write enable for all control registers.
#define PADCTRL_REGEN(id) (PADCTRL##id##_BASE_ADDR + 0x0)
#define PADCTRL_REGEN 0

// Dedicated pad attributes.
#define PADCTRL_DIO_PADS(id) (PADCTRL##id##_BASE_ADDR + 0x4)
#define PADCTRL_DIO_PADS_ATTR0_MASK 0x3f
#define PADCTRL_DIO_PADS_ATTR0_OFFSET 0
#define PADCTRL_DIO_PADS_ATTR1_MASK 0x3f
#define PADCTRL_DIO_PADS_ATTR1_OFFSET 6
#define PADCTRL_DIO_PADS_ATTR2_MASK 0x3f
#define PADCTRL_DIO_PADS_ATTR2_OFFSET 12
#define PADCTRL_DIO_PADS_ATTR3_MASK 0x3f
#define PADCTRL_DIO_PADS_ATTR3_OFFSET 18

// Muxed pad attributes.
#define PADCTRL_MIO_PADS0(id) (PADCTRL##id##_BASE_ADDR + 0x8)
#define PADCTRL_MIO_PADS0_ATTR0_MASK 0x3f
#define PADCTRL_MIO_PADS0_ATTR0_OFFSET 0
#define PADCTRL_MIO_PADS0_ATTR1_MASK 0x3f
#define PADCTRL_MIO_PADS0_ATTR1_OFFSET 6
#define PADCTRL_MIO_PADS0_ATTR2_MASK 0x3f
#define PADCTRL_MIO_PADS0_ATTR2_OFFSET 12
#define PADCTRL_MIO_PADS0_ATTR3_MASK 0x3f
#define PADCTRL_MIO_PADS0_ATTR3_OFFSET 18
#define PADCTRL_MIO_PADS0_ATTR4_MASK 0x3f
#define PADCTRL_MIO_PADS0_ATTR4_OFFSET 24

// Muxed pad attributes.
#define PADCTRL_MIO_PADS1(id) (PADCTRL##id##_BASE_ADDR + 0xc)
#define PADCTRL_MIO_PADS1_ATTR5_MASK 0x3f
#define PADCTRL_MIO_PADS1_ATTR5_OFFSET 0
#define PADCTRL_MIO_PADS1_ATTR6_MASK 0x3f
#define PADCTRL_MIO_PADS1_ATTR6_OFFSET 6
#define PADCTRL_MIO_PADS1_ATTR7_MASK 0x3f
#define PADCTRL_MIO_PADS1_ATTR7_OFFSET 12
#define PADCTRL_MIO_PADS1_ATTR8_MASK 0x3f
#define PADCTRL_MIO_PADS1_ATTR8_OFFSET 18
#define PADCTRL_MIO_PADS1_ATTR9_MASK 0x3f
#define PADCTRL_MIO_PADS1_ATTR9_OFFSET 24

// Muxed pad attributes.
#define PADCTRL_MIO_PADS2(id) (PADCTRL##id##_BASE_ADDR + 0x10)
#define PADCTRL_MIO_PADS2_ATTR10_MASK 0x3f
#define PADCTRL_MIO_PADS2_ATTR10_OFFSET 0
#define PADCTRL_MIO_PADS2_ATTR11_MASK 0x3f
#define PADCTRL_MIO_PADS2_ATTR11_OFFSET 6
#define PADCTRL_MIO_PADS2_ATTR12_MASK 0x3f
#define PADCTRL_MIO_PADS2_ATTR12_OFFSET 12
#define PADCTRL_MIO_PADS2_ATTR13_MASK 0x3f
#define PADCTRL_MIO_PADS2_ATTR13_OFFSET 18
#define PADCTRL_MIO_PADS2_ATTR14_MASK 0x3f
#define PADCTRL_MIO_PADS2_ATTR14_OFFSET 24

// Muxed pad attributes.
#define PADCTRL_MIO_PADS3(id) (PADCTRL##id##_BASE_ADDR + 0x14)
#define PADCTRL_MIO_PADS3_ATTR15_MASK 0x3f
#define PADCTRL_MIO_PADS3_ATTR15_OFFSET 0
#define PADCTRL_MIO_PADS3_ATTR16_MASK 0x3f
#define PADCTRL_MIO_PADS3_ATTR16_OFFSET 6
#define PADCTRL_MIO_PADS3_ATTR17_MASK 0x3f
#define PADCTRL_MIO_PADS3_ATTR17_OFFSET 12

#endif  // _PADCTRL_REG_DEFS_
// End generated register defines for PADCTRL