tree 99147f5c8aa2db0565c93c51562e357d7c51dc72
parent 0f9bcddbb40fc91d133c960019806f8ae5b82b8c
author Eunchan Kim <eunchan@google.com> 1572472476 -0700
committer Eunchan Kim <eunchan@google.com> 1572556214 -0700
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[hmac] Block the msg fifo request with packer ready

This is follow-up PR for #683

Problem 1:

    In #683, the design unguarded msg_fifo_gnt signal from
    `fifo_wready`. It only needs to see `packer_ready`. This results
    unintended request acceptance as `msg_write` is also gated by
    `fifo_wready`.

What happend with the problem is, when the MSG_FIFO is full, it
de-asserts `fifo_wready`. At this time, `prim_packer` has still enough
room to accept one more request. It doesn't drop `packer_ready`
(`prim_packer.ready_o`) yet. So `msg_fifo_gnt` can be high whenever the
request comes. That request should've come to `prim_packer`, which
didn't happen due to the `msg_write` is gated by `fifo_wready`.

Resolution:

    `msg_write` is not gated by `fifo_wready`.

I've tested hmac_back_pressure test with modified design. It still
fails. But the failure isn't due to the modified design but the
scoreboard assumes getting the fifo_full status which cannot be happen
as the request was back-pressured and accepted after fifo_full condition
is resolved.

Also, fifo_full interrupt now happens when MSG_FIFO and prim_packer both
cannot accept the new request, not only seeing MSG_FIFO `fifo_wready`.

Cindy has a fix PR for this issue.