hw/ip/sysrst_ctrl/rtl/sysrst_ctrl_reg_top.sv - 3p/lowrisc/opentitan - Git at Google

 // Copyright lowRISC contributors.
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 //
 // Register Top module auto-generated by `reggen`

 `include "prim_assert.sv"

 module sysrst_ctrl_reg_top (
   input clk_i,
   input rst_ni,
   input clk_aon_i,
   input rst_aon_ni,
   input  tlul_pkg::tl_h2d_t tl_i,
   output tlul_pkg::tl_d2h_t tl_o,
   // To HW
   output sysrst_ctrl_reg_pkg::sysrst_ctrl_reg2hw_t reg2hw, // Write
   input  sysrst_ctrl_reg_pkg::sysrst_ctrl_hw2reg_t hw2reg, // Read

   // Integrity check errors
   output logic intg_err_o,

   // Config
   input devmode_i // If 1, explicit error return for unmapped register access
 );

   import sysrst_ctrl_reg_pkg::* ;

   localparam int AW = 8;
   localparam int DW = 32;
   localparam int DBW = DW/8;                    // Byte Width

   // register signals
   logic           reg_we;
   logic           reg_re;
   logic [AW-1:0]  reg_addr;
   logic [DW-1:0]  reg_wdata;
   logic [DBW-1:0] reg_be;
   logic [DW-1:0]  reg_rdata;
   logic           reg_error;

   logic          addrmiss, wr_err;

   logic [DW-1:0] reg_rdata_next;
   logic reg_busy;

   tlul_pkg::tl_h2d_t tl_reg_h2d;
   tlul_pkg::tl_d2h_t tl_reg_d2h;


   // incoming payload check
   logic intg_err;
   tlul_cmd_intg_chk u_chk (
     .tl_i(tl_i),
     .err_o(intg_err)
   );

   // also check for spurious write enables
   logic reg_we_err;
   logic [42:0] reg_we_check;
   prim_reg_we_check #(
     .OneHotWidth(43)
   ) u_prim_reg_we_check (
     .clk_i(clk_i),
     .rst_ni(rst_ni),
     .oh_i  (reg_we_check),
     .en_i  (reg_we && !addrmiss),
     .err_o (reg_we_err)
   );

   logic err_q;
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       err_q <= '0;
     end else if (intg_err || reg_we_err) begin
       err_q <= 1'b1;
     end
   end

   // integrity error output is permanent and should be used for alert generation
   // register errors are transactional
   assign intg_err_o = err_q | intg_err | reg_we_err;

   // outgoing integrity generation
   tlul_pkg::tl_d2h_t tl_o_pre;
   tlul_rsp_intg_gen #(
     .EnableRspIntgGen(1),
     .EnableDataIntgGen(1)
   ) u_rsp_intg_gen (
     .tl_i(tl_o_pre),
     .tl_o(tl_o)
   );

   assign tl_reg_h2d = tl_i;
   assign tl_o_pre   = tl_reg_d2h;

   tlul_adapter_reg #(
     .RegAw(AW),
     .RegDw(DW),
     .EnableDataIntgGen(0)
   ) u_reg_if (
     .clk_i  (clk_i),
     .rst_ni (rst_ni),

     .tl_i (tl_reg_h2d),
     .tl_o (tl_reg_d2h),

     .en_ifetch_i(prim_mubi_pkg::MuBi4False),
     .intg_error_o(),

     .we_o    (reg_we),
     .re_o    (reg_re),
     .addr_o  (reg_addr),
     .wdata_o (reg_wdata),
     .be_o    (reg_be),
     .busy_i  (reg_busy),
     .rdata_i (reg_rdata),
     .error_i (reg_error)
   );

   // cdc oversampling signals

   assign reg_rdata = reg_rdata_next ;
   assign reg_error = (devmode_i & addrmiss) | wr_err | intg_err;

   // Define SW related signals
   // Format: <reg>_<field>_{wd|we|qs}
   //        or <reg>_{wd|we|qs} if field == 1 or 0
   logic intr_state_we;
   logic intr_state_qs;
   logic intr_state_wd;
   logic intr_enable_we;
   logic intr_enable_qs;
   logic intr_enable_wd;
   logic intr_test_we;
   logic intr_test_wd;
   logic alert_test_we;
   logic alert_test_wd;
   logic regwen_we;
   logic regwen_qs;
   logic regwen_wd;
   logic ec_rst_ctl_we;
   logic [15:0] ec_rst_ctl_qs;
   logic ec_rst_ctl_busy;
   logic ulp_ac_debounce_ctl_we;
   logic [15:0] ulp_ac_debounce_ctl_qs;
   logic ulp_ac_debounce_ctl_busy;
   logic ulp_lid_debounce_ctl_we;
   logic [15:0] ulp_lid_debounce_ctl_qs;
   logic ulp_lid_debounce_ctl_busy;
   logic ulp_pwrb_debounce_ctl_we;
   logic [15:0] ulp_pwrb_debounce_ctl_qs;
   logic ulp_pwrb_debounce_ctl_busy;
   logic ulp_ctl_we;
   logic [0:0] ulp_ctl_qs;
   logic ulp_ctl_busy;
   logic ulp_status_we;
   logic [0:0] ulp_status_qs;
   logic ulp_status_busy;
   logic wkup_status_we;
   logic [0:0] wkup_status_qs;
   logic wkup_status_busy;
   logic key_invert_ctl_we;
   logic [11:0] key_invert_ctl_qs;
   logic key_invert_ctl_busy;
   logic pin_allowed_ctl_we;
   logic [15:0] pin_allowed_ctl_qs;
   logic pin_allowed_ctl_busy;
   logic pin_out_ctl_we;
   logic [7:0] pin_out_ctl_qs;
   logic pin_out_ctl_busy;
   logic pin_out_value_we;
   logic [7:0] pin_out_value_qs;
   logic pin_out_value_busy;
   logic pin_in_value_pwrb_in_qs;
   logic pin_in_value_key0_in_qs;
   logic pin_in_value_key1_in_qs;
   logic pin_in_value_key2_in_qs;
   logic pin_in_value_lid_open_qs;
   logic pin_in_value_ac_present_qs;
   logic pin_in_value_ec_rst_l_qs;
   logic pin_in_value_flash_wp_l_qs;
   logic key_intr_ctl_we;
   logic [13:0] key_intr_ctl_qs;
   logic key_intr_ctl_busy;
   logic key_intr_debounce_ctl_we;
   logic [15:0] key_intr_debounce_ctl_qs;
   logic key_intr_debounce_ctl_busy;
   logic auto_block_debounce_ctl_we;
   logic [16:0] auto_block_debounce_ctl_qs;
   logic auto_block_debounce_ctl_busy;
   logic auto_block_out_ctl_we;
   logic [6:0] auto_block_out_ctl_qs;
   logic auto_block_out_ctl_busy;
   logic com_pre_sel_ctl_0_we;
   logic [4:0] com_pre_sel_ctl_0_qs;
   logic com_pre_sel_ctl_0_busy;
   logic com_pre_sel_ctl_1_we;
   logic [4:0] com_pre_sel_ctl_1_qs;
   logic com_pre_sel_ctl_1_busy;
   logic com_pre_sel_ctl_2_we;
   logic [4:0] com_pre_sel_ctl_2_qs;
   logic com_pre_sel_ctl_2_busy;
   logic com_pre_sel_ctl_3_we;
   logic [4:0] com_pre_sel_ctl_3_qs;
   logic com_pre_sel_ctl_3_busy;
   logic com_pre_det_ctl_0_we;
   logic [31:0] com_pre_det_ctl_0_qs;
   logic com_pre_det_ctl_0_busy;
   logic com_pre_det_ctl_1_we;
   logic [31:0] com_pre_det_ctl_1_qs;
   logic com_pre_det_ctl_1_busy;
   logic com_pre_det_ctl_2_we;
   logic [31:0] com_pre_det_ctl_2_qs;
   logic com_pre_det_ctl_2_busy;
   logic com_pre_det_ctl_3_we;
   logic [31:0] com_pre_det_ctl_3_qs;
   logic com_pre_det_ctl_3_busy;
   logic com_sel_ctl_0_we;
   logic [4:0] com_sel_ctl_0_qs;
   logic com_sel_ctl_0_busy;
   logic com_sel_ctl_1_we;
   logic [4:0] com_sel_ctl_1_qs;
   logic com_sel_ctl_1_busy;
   logic com_sel_ctl_2_we;
   logic [4:0] com_sel_ctl_2_qs;
   logic com_sel_ctl_2_busy;
   logic com_sel_ctl_3_we;
   logic [4:0] com_sel_ctl_3_qs;
   logic com_sel_ctl_3_busy;
   logic com_det_ctl_0_we;
   logic [31:0] com_det_ctl_0_qs;
   logic com_det_ctl_0_busy;
   logic com_det_ctl_1_we;
   logic [31:0] com_det_ctl_1_qs;
   logic com_det_ctl_1_busy;
   logic com_det_ctl_2_we;
   logic [31:0] com_det_ctl_2_qs;
   logic com_det_ctl_2_busy;
   logic com_det_ctl_3_we;
   logic [31:0] com_det_ctl_3_qs;
   logic com_det_ctl_3_busy;
   logic com_out_ctl_0_we;
   logic [3:0] com_out_ctl_0_qs;
   logic com_out_ctl_0_busy;
   logic com_out_ctl_1_we;
   logic [3:0] com_out_ctl_1_qs;
   logic com_out_ctl_1_busy;
   logic com_out_ctl_2_we;
   logic [3:0] com_out_ctl_2_qs;
   logic com_out_ctl_2_busy;
   logic com_out_ctl_3_we;
   logic [3:0] com_out_ctl_3_qs;
   logic com_out_ctl_3_busy;
   logic combo_intr_status_we;
   logic [3:0] combo_intr_status_qs;
   logic combo_intr_status_busy;
   logic key_intr_status_we;
   logic [13:0] key_intr_status_qs;
   logic key_intr_status_busy;
   // Define register CDC handling.
   // CDC handling is done on a per-reg instead of per-field boundary.

   logic [15:0]  aon_ec_rst_ctl_qs_int;
   logic [15:0] aon_ec_rst_ctl_qs;
   logic [15:0] aon_ec_rst_ctl_wdata;
   logic aon_ec_rst_ctl_we;
   logic unused_aon_ec_rst_ctl_wdata;
   logic aon_ec_rst_ctl_regwen;

   always_comb begin
     aon_ec_rst_ctl_qs = 16'h7d0;
     aon_ec_rst_ctl_qs = aon_ec_rst_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h7d0),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_ec_rst_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (ec_rst_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (ec_rst_ctl_busy),
     .src_qs_o     (ec_rst_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_ec_rst_ctl_qs),
     .dst_we_o     (aon_ec_rst_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_ec_rst_ctl_regwen),
     .dst_wd_o     (aon_ec_rst_ctl_wdata)
   );
   assign unused_aon_ec_rst_ctl_wdata =
       ^aon_ec_rst_ctl_wdata;

   logic [15:0]  aon_ulp_ac_debounce_ctl_qs_int;
   logic [15:0] aon_ulp_ac_debounce_ctl_qs;
   logic [15:0] aon_ulp_ac_debounce_ctl_wdata;
   logic aon_ulp_ac_debounce_ctl_we;
   logic unused_aon_ulp_ac_debounce_ctl_wdata;
   logic aon_ulp_ac_debounce_ctl_regwen;

   always_comb begin
     aon_ulp_ac_debounce_ctl_qs = 16'h1f40;
     aon_ulp_ac_debounce_ctl_qs = aon_ulp_ac_debounce_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h1f40),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_ulp_ac_debounce_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (ulp_ac_debounce_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (ulp_ac_debounce_ctl_busy),
     .src_qs_o     (ulp_ac_debounce_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_ulp_ac_debounce_ctl_qs),
     .dst_we_o     (aon_ulp_ac_debounce_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_ulp_ac_debounce_ctl_regwen),
     .dst_wd_o     (aon_ulp_ac_debounce_ctl_wdata)
   );
   assign unused_aon_ulp_ac_debounce_ctl_wdata =
       ^aon_ulp_ac_debounce_ctl_wdata;

   logic [15:0]  aon_ulp_lid_debounce_ctl_qs_int;
   logic [15:0] aon_ulp_lid_debounce_ctl_qs;
   logic [15:0] aon_ulp_lid_debounce_ctl_wdata;
   logic aon_ulp_lid_debounce_ctl_we;
   logic unused_aon_ulp_lid_debounce_ctl_wdata;
   logic aon_ulp_lid_debounce_ctl_regwen;

   always_comb begin
     aon_ulp_lid_debounce_ctl_qs = 16'h1f40;
     aon_ulp_lid_debounce_ctl_qs = aon_ulp_lid_debounce_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h1f40),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_ulp_lid_debounce_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (ulp_lid_debounce_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (ulp_lid_debounce_ctl_busy),
     .src_qs_o     (ulp_lid_debounce_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_ulp_lid_debounce_ctl_qs),
     .dst_we_o     (aon_ulp_lid_debounce_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_ulp_lid_debounce_ctl_regwen),
     .dst_wd_o     (aon_ulp_lid_debounce_ctl_wdata)
   );
   assign unused_aon_ulp_lid_debounce_ctl_wdata =
       ^aon_ulp_lid_debounce_ctl_wdata;

   logic [15:0]  aon_ulp_pwrb_debounce_ctl_qs_int;
   logic [15:0] aon_ulp_pwrb_debounce_ctl_qs;
   logic [15:0] aon_ulp_pwrb_debounce_ctl_wdata;
   logic aon_ulp_pwrb_debounce_ctl_we;
   logic unused_aon_ulp_pwrb_debounce_ctl_wdata;
   logic aon_ulp_pwrb_debounce_ctl_regwen;

   always_comb begin
     aon_ulp_pwrb_debounce_ctl_qs = 16'h1f40;
     aon_ulp_pwrb_debounce_ctl_qs = aon_ulp_pwrb_debounce_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h1f40),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_ulp_pwrb_debounce_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (ulp_pwrb_debounce_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (ulp_pwrb_debounce_ctl_busy),
     .src_qs_o     (ulp_pwrb_debounce_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_ulp_pwrb_debounce_ctl_qs),
     .dst_we_o     (aon_ulp_pwrb_debounce_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_ulp_pwrb_debounce_ctl_regwen),
     .dst_wd_o     (aon_ulp_pwrb_debounce_ctl_wdata)
   );
   assign unused_aon_ulp_pwrb_debounce_ctl_wdata =
       ^aon_ulp_pwrb_debounce_ctl_wdata;

   logic  aon_ulp_ctl_qs_int;
   logic [0:0] aon_ulp_ctl_qs;
   logic [0:0] aon_ulp_ctl_wdata;
   logic aon_ulp_ctl_we;
   logic unused_aon_ulp_ctl_wdata;

   always_comb begin
     aon_ulp_ctl_qs = 1'h0;
     aon_ulp_ctl_qs = aon_ulp_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(1),
     .ResetVal(1'h0),
     .BitMask(1'h1),
     .DstWrReq(0)
   ) u_ulp_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (ulp_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[0:0]),
     .src_busy_o   (ulp_ctl_busy),
     .src_qs_o     (ulp_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_ulp_ctl_qs),
     .dst_we_o     (aon_ulp_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_ulp_ctl_wdata)
   );
   assign unused_aon_ulp_ctl_wdata =
       ^aon_ulp_ctl_wdata;

   logic  aon_ulp_status_ds_int;
   logic  aon_ulp_status_qs_int;
   logic [0:0] aon_ulp_status_ds;
   logic aon_ulp_status_qe;
   logic [0:0] aon_ulp_status_qs;
   logic [0:0] aon_ulp_status_wdata;
   logic aon_ulp_status_we;
   logic unused_aon_ulp_status_wdata;

   always_comb begin
     aon_ulp_status_qs = 1'h0;
     aon_ulp_status_ds = 1'h0;
     aon_ulp_status_ds = aon_ulp_status_ds_int;
     aon_ulp_status_qs = aon_ulp_status_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(1),
     .ResetVal(1'h0),
     .BitMask(1'h1),
     .DstWrReq(1)
   ) u_ulp_status_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (ulp_status_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[0:0]),
     .src_busy_o   (ulp_status_busy),
     .src_qs_o     (ulp_status_qs), // for software read back
     .dst_update_i (aon_ulp_status_qe),
     .dst_ds_i     (aon_ulp_status_ds),
     .dst_qs_i     (aon_ulp_status_qs),
     .dst_we_o     (aon_ulp_status_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_ulp_status_wdata)
   );
   assign unused_aon_ulp_status_wdata =
       ^aon_ulp_status_wdata;

   logic  aon_wkup_status_ds_int;
   logic  aon_wkup_status_qs_int;
   logic [0:0] aon_wkup_status_ds;
   logic aon_wkup_status_qe;
   logic [0:0] aon_wkup_status_qs;
   logic [0:0] aon_wkup_status_wdata;
   logic aon_wkup_status_we;
   logic unused_aon_wkup_status_wdata;

   always_comb begin
     aon_wkup_status_qs = 1'h0;
     aon_wkup_status_ds = 1'h0;
     aon_wkup_status_ds = aon_wkup_status_ds_int;
     aon_wkup_status_qs = aon_wkup_status_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(1),
     .ResetVal(1'h0),
     .BitMask(1'h1),
     .DstWrReq(1)
   ) u_wkup_status_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (wkup_status_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[0:0]),
     .src_busy_o   (wkup_status_busy),
     .src_qs_o     (wkup_status_qs), // for software read back
     .dst_update_i (aon_wkup_status_qe),
     .dst_ds_i     (aon_wkup_status_ds),
     .dst_qs_i     (aon_wkup_status_qs),
     .dst_we_o     (aon_wkup_status_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_wkup_status_wdata)
   );
   assign unused_aon_wkup_status_wdata =
       ^aon_wkup_status_wdata;

   logic  aon_key_invert_ctl_key0_in_qs_int;
   logic  aon_key_invert_ctl_key0_out_qs_int;
   logic  aon_key_invert_ctl_key1_in_qs_int;
   logic  aon_key_invert_ctl_key1_out_qs_int;
   logic  aon_key_invert_ctl_key2_in_qs_int;
   logic  aon_key_invert_ctl_key2_out_qs_int;
   logic  aon_key_invert_ctl_pwrb_in_qs_int;
   logic  aon_key_invert_ctl_pwrb_out_qs_int;
   logic  aon_key_invert_ctl_ac_present_qs_int;
   logic  aon_key_invert_ctl_bat_disable_qs_int;
   logic  aon_key_invert_ctl_lid_open_qs_int;
   logic  aon_key_invert_ctl_z3_wakeup_qs_int;
   logic [11:0] aon_key_invert_ctl_qs;
   logic [11:0] aon_key_invert_ctl_wdata;
   logic aon_key_invert_ctl_we;
   logic unused_aon_key_invert_ctl_wdata;
   logic aon_key_invert_ctl_regwen;

   always_comb begin
     aon_key_invert_ctl_qs = 12'h0;
     aon_key_invert_ctl_qs[0] = aon_key_invert_ctl_key0_in_qs_int;
     aon_key_invert_ctl_qs[1] = aon_key_invert_ctl_key0_out_qs_int;
     aon_key_invert_ctl_qs[2] = aon_key_invert_ctl_key1_in_qs_int;
     aon_key_invert_ctl_qs[3] = aon_key_invert_ctl_key1_out_qs_int;
     aon_key_invert_ctl_qs[4] = aon_key_invert_ctl_key2_in_qs_int;
     aon_key_invert_ctl_qs[5] = aon_key_invert_ctl_key2_out_qs_int;
     aon_key_invert_ctl_qs[6] = aon_key_invert_ctl_pwrb_in_qs_int;
     aon_key_invert_ctl_qs[7] = aon_key_invert_ctl_pwrb_out_qs_int;
     aon_key_invert_ctl_qs[8] = aon_key_invert_ctl_ac_present_qs_int;
     aon_key_invert_ctl_qs[9] = aon_key_invert_ctl_bat_disable_qs_int;
     aon_key_invert_ctl_qs[10] = aon_key_invert_ctl_lid_open_qs_int;
     aon_key_invert_ctl_qs[11] = aon_key_invert_ctl_z3_wakeup_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(12),
     .ResetVal(12'h0),
     .BitMask(12'hfff),
     .DstWrReq(0)
   ) u_key_invert_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (key_invert_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[11:0]),
     .src_busy_o   (key_invert_ctl_busy),
     .src_qs_o     (key_invert_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_key_invert_ctl_qs),
     .dst_we_o     (aon_key_invert_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_key_invert_ctl_regwen),
     .dst_wd_o     (aon_key_invert_ctl_wdata)
   );
   assign unused_aon_key_invert_ctl_wdata =
       ^aon_key_invert_ctl_wdata;

   logic  aon_pin_allowed_ctl_bat_disable_0_qs_int;
   logic  aon_pin_allowed_ctl_ec_rst_l_0_qs_int;
   logic  aon_pin_allowed_ctl_pwrb_out_0_qs_int;
   logic  aon_pin_allowed_ctl_key0_out_0_qs_int;
   logic  aon_pin_allowed_ctl_key1_out_0_qs_int;
   logic  aon_pin_allowed_ctl_key2_out_0_qs_int;
   logic  aon_pin_allowed_ctl_z3_wakeup_0_qs_int;
   logic  aon_pin_allowed_ctl_flash_wp_l_0_qs_int;
   logic  aon_pin_allowed_ctl_bat_disable_1_qs_int;
   logic  aon_pin_allowed_ctl_ec_rst_l_1_qs_int;
   logic  aon_pin_allowed_ctl_pwrb_out_1_qs_int;
   logic  aon_pin_allowed_ctl_key0_out_1_qs_int;
   logic  aon_pin_allowed_ctl_key1_out_1_qs_int;
   logic  aon_pin_allowed_ctl_key2_out_1_qs_int;
   logic  aon_pin_allowed_ctl_z3_wakeup_1_qs_int;
   logic  aon_pin_allowed_ctl_flash_wp_l_1_qs_int;
   logic [15:0] aon_pin_allowed_ctl_qs;
   logic [15:0] aon_pin_allowed_ctl_wdata;
   logic aon_pin_allowed_ctl_we;
   logic unused_aon_pin_allowed_ctl_wdata;
   logic aon_pin_allowed_ctl_regwen;

   always_comb begin
     aon_pin_allowed_ctl_qs = 16'h82;
     aon_pin_allowed_ctl_qs[0] = aon_pin_allowed_ctl_bat_disable_0_qs_int;
     aon_pin_allowed_ctl_qs[1] = aon_pin_allowed_ctl_ec_rst_l_0_qs_int;
     aon_pin_allowed_ctl_qs[2] = aon_pin_allowed_ctl_pwrb_out_0_qs_int;
     aon_pin_allowed_ctl_qs[3] = aon_pin_allowed_ctl_key0_out_0_qs_int;
     aon_pin_allowed_ctl_qs[4] = aon_pin_allowed_ctl_key1_out_0_qs_int;
     aon_pin_allowed_ctl_qs[5] = aon_pin_allowed_ctl_key2_out_0_qs_int;
     aon_pin_allowed_ctl_qs[6] = aon_pin_allowed_ctl_z3_wakeup_0_qs_int;
     aon_pin_allowed_ctl_qs[7] = aon_pin_allowed_ctl_flash_wp_l_0_qs_int;
     aon_pin_allowed_ctl_qs[8] = aon_pin_allowed_ctl_bat_disable_1_qs_int;
     aon_pin_allowed_ctl_qs[9] = aon_pin_allowed_ctl_ec_rst_l_1_qs_int;
     aon_pin_allowed_ctl_qs[10] = aon_pin_allowed_ctl_pwrb_out_1_qs_int;
     aon_pin_allowed_ctl_qs[11] = aon_pin_allowed_ctl_key0_out_1_qs_int;
     aon_pin_allowed_ctl_qs[12] = aon_pin_allowed_ctl_key1_out_1_qs_int;
     aon_pin_allowed_ctl_qs[13] = aon_pin_allowed_ctl_key2_out_1_qs_int;
     aon_pin_allowed_ctl_qs[14] = aon_pin_allowed_ctl_z3_wakeup_1_qs_int;
     aon_pin_allowed_ctl_qs[15] = aon_pin_allowed_ctl_flash_wp_l_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h82),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_pin_allowed_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (pin_allowed_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (pin_allowed_ctl_busy),
     .src_qs_o     (pin_allowed_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_pin_allowed_ctl_qs),
     .dst_we_o     (aon_pin_allowed_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_pin_allowed_ctl_regwen),
     .dst_wd_o     (aon_pin_allowed_ctl_wdata)
   );
   assign unused_aon_pin_allowed_ctl_wdata =
       ^aon_pin_allowed_ctl_wdata;

   logic  aon_pin_out_ctl_bat_disable_qs_int;
   logic  aon_pin_out_ctl_ec_rst_l_qs_int;
   logic  aon_pin_out_ctl_pwrb_out_qs_int;
   logic  aon_pin_out_ctl_key0_out_qs_int;
   logic  aon_pin_out_ctl_key1_out_qs_int;
   logic  aon_pin_out_ctl_key2_out_qs_int;
   logic  aon_pin_out_ctl_z3_wakeup_qs_int;
   logic  aon_pin_out_ctl_flash_wp_l_qs_int;
   logic [7:0] aon_pin_out_ctl_qs;
   logic [7:0] aon_pin_out_ctl_wdata;
   logic aon_pin_out_ctl_we;
   logic unused_aon_pin_out_ctl_wdata;

   always_comb begin
     aon_pin_out_ctl_qs = 8'h82;
     aon_pin_out_ctl_qs[0] = aon_pin_out_ctl_bat_disable_qs_int;
     aon_pin_out_ctl_qs[1] = aon_pin_out_ctl_ec_rst_l_qs_int;
     aon_pin_out_ctl_qs[2] = aon_pin_out_ctl_pwrb_out_qs_int;
     aon_pin_out_ctl_qs[3] = aon_pin_out_ctl_key0_out_qs_int;
     aon_pin_out_ctl_qs[4] = aon_pin_out_ctl_key1_out_qs_int;
     aon_pin_out_ctl_qs[5] = aon_pin_out_ctl_key2_out_qs_int;
     aon_pin_out_ctl_qs[6] = aon_pin_out_ctl_z3_wakeup_qs_int;
     aon_pin_out_ctl_qs[7] = aon_pin_out_ctl_flash_wp_l_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(8),
     .ResetVal(8'h82),
     .BitMask(8'hff),
     .DstWrReq(0)
   ) u_pin_out_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (pin_out_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[7:0]),
     .src_busy_o   (pin_out_ctl_busy),
     .src_qs_o     (pin_out_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_pin_out_ctl_qs),
     .dst_we_o     (aon_pin_out_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_pin_out_ctl_wdata)
   );
   assign unused_aon_pin_out_ctl_wdata =
       ^aon_pin_out_ctl_wdata;

   logic  aon_pin_out_value_bat_disable_qs_int;
   logic  aon_pin_out_value_ec_rst_l_qs_int;
   logic  aon_pin_out_value_pwrb_out_qs_int;
   logic  aon_pin_out_value_key0_out_qs_int;
   logic  aon_pin_out_value_key1_out_qs_int;
   logic  aon_pin_out_value_key2_out_qs_int;
   logic  aon_pin_out_value_z3_wakeup_qs_int;
   logic  aon_pin_out_value_flash_wp_l_qs_int;
   logic [7:0] aon_pin_out_value_qs;
   logic [7:0] aon_pin_out_value_wdata;
   logic aon_pin_out_value_we;
   logic unused_aon_pin_out_value_wdata;

   always_comb begin
     aon_pin_out_value_qs = 8'h0;
     aon_pin_out_value_qs[0] = aon_pin_out_value_bat_disable_qs_int;
     aon_pin_out_value_qs[1] = aon_pin_out_value_ec_rst_l_qs_int;
     aon_pin_out_value_qs[2] = aon_pin_out_value_pwrb_out_qs_int;
     aon_pin_out_value_qs[3] = aon_pin_out_value_key0_out_qs_int;
     aon_pin_out_value_qs[4] = aon_pin_out_value_key1_out_qs_int;
     aon_pin_out_value_qs[5] = aon_pin_out_value_key2_out_qs_int;
     aon_pin_out_value_qs[6] = aon_pin_out_value_z3_wakeup_qs_int;
     aon_pin_out_value_qs[7] = aon_pin_out_value_flash_wp_l_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(8),
     .ResetVal(8'h0),
     .BitMask(8'hff),
     .DstWrReq(0)
   ) u_pin_out_value_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (pin_out_value_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[7:0]),
     .src_busy_o   (pin_out_value_busy),
     .src_qs_o     (pin_out_value_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_pin_out_value_qs),
     .dst_we_o     (aon_pin_out_value_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_pin_out_value_wdata)
   );
   assign unused_aon_pin_out_value_wdata =
       ^aon_pin_out_value_wdata;

   logic  aon_key_intr_ctl_pwrb_in_h2l_qs_int;
   logic  aon_key_intr_ctl_key0_in_h2l_qs_int;
   logic  aon_key_intr_ctl_key1_in_h2l_qs_int;
   logic  aon_key_intr_ctl_key2_in_h2l_qs_int;
   logic  aon_key_intr_ctl_ac_present_h2l_qs_int;
   logic  aon_key_intr_ctl_ec_rst_l_h2l_qs_int;
   logic  aon_key_intr_ctl_flash_wp_l_h2l_qs_int;
   logic  aon_key_intr_ctl_pwrb_in_l2h_qs_int;
   logic  aon_key_intr_ctl_key0_in_l2h_qs_int;
   logic  aon_key_intr_ctl_key1_in_l2h_qs_int;
   logic  aon_key_intr_ctl_key2_in_l2h_qs_int;
   logic  aon_key_intr_ctl_ac_present_l2h_qs_int;
   logic  aon_key_intr_ctl_ec_rst_l_l2h_qs_int;
   logic  aon_key_intr_ctl_flash_wp_l_l2h_qs_int;
   logic [13:0] aon_key_intr_ctl_qs;
   logic [13:0] aon_key_intr_ctl_wdata;
   logic aon_key_intr_ctl_we;
   logic unused_aon_key_intr_ctl_wdata;
   logic aon_key_intr_ctl_regwen;

   always_comb begin
     aon_key_intr_ctl_qs = 14'h0;
     aon_key_intr_ctl_qs[0] = aon_key_intr_ctl_pwrb_in_h2l_qs_int;
     aon_key_intr_ctl_qs[1] = aon_key_intr_ctl_key0_in_h2l_qs_int;
     aon_key_intr_ctl_qs[2] = aon_key_intr_ctl_key1_in_h2l_qs_int;
     aon_key_intr_ctl_qs[3] = aon_key_intr_ctl_key2_in_h2l_qs_int;
     aon_key_intr_ctl_qs[4] = aon_key_intr_ctl_ac_present_h2l_qs_int;
     aon_key_intr_ctl_qs[5] = aon_key_intr_ctl_ec_rst_l_h2l_qs_int;
     aon_key_intr_ctl_qs[6] = aon_key_intr_ctl_flash_wp_l_h2l_qs_int;
     aon_key_intr_ctl_qs[7] = aon_key_intr_ctl_pwrb_in_l2h_qs_int;
     aon_key_intr_ctl_qs[8] = aon_key_intr_ctl_key0_in_l2h_qs_int;
     aon_key_intr_ctl_qs[9] = aon_key_intr_ctl_key1_in_l2h_qs_int;
     aon_key_intr_ctl_qs[10] = aon_key_intr_ctl_key2_in_l2h_qs_int;
     aon_key_intr_ctl_qs[11] = aon_key_intr_ctl_ac_present_l2h_qs_int;
     aon_key_intr_ctl_qs[12] = aon_key_intr_ctl_ec_rst_l_l2h_qs_int;
     aon_key_intr_ctl_qs[13] = aon_key_intr_ctl_flash_wp_l_l2h_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(14),
     .ResetVal(14'h0),
     .BitMask(14'h3fff),
     .DstWrReq(0)
   ) u_key_intr_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (key_intr_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[13:0]),
     .src_busy_o   (key_intr_ctl_busy),
     .src_qs_o     (key_intr_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_key_intr_ctl_qs),
     .dst_we_o     (aon_key_intr_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_key_intr_ctl_regwen),
     .dst_wd_o     (aon_key_intr_ctl_wdata)
   );
   assign unused_aon_key_intr_ctl_wdata =
       ^aon_key_intr_ctl_wdata;

   logic [15:0]  aon_key_intr_debounce_ctl_qs_int;
   logic [15:0] aon_key_intr_debounce_ctl_qs;
   logic [15:0] aon_key_intr_debounce_ctl_wdata;
   logic aon_key_intr_debounce_ctl_we;
   logic unused_aon_key_intr_debounce_ctl_wdata;
   logic aon_key_intr_debounce_ctl_regwen;

   always_comb begin
     aon_key_intr_debounce_ctl_qs = 16'h7d0;
     aon_key_intr_debounce_ctl_qs = aon_key_intr_debounce_ctl_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(16),
     .ResetVal(16'h7d0),
     .BitMask(16'hffff),
     .DstWrReq(0)
   ) u_key_intr_debounce_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (key_intr_debounce_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[15:0]),
     .src_busy_o   (key_intr_debounce_ctl_busy),
     .src_qs_o     (key_intr_debounce_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_key_intr_debounce_ctl_qs),
     .dst_we_o     (aon_key_intr_debounce_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_key_intr_debounce_ctl_regwen),
     .dst_wd_o     (aon_key_intr_debounce_ctl_wdata)
   );
   assign unused_aon_key_intr_debounce_ctl_wdata =
       ^aon_key_intr_debounce_ctl_wdata;

   logic [15:0]  aon_auto_block_debounce_ctl_debounce_timer_qs_int;
   logic  aon_auto_block_debounce_ctl_auto_block_enable_qs_int;
   logic [16:0] aon_auto_block_debounce_ctl_qs;
   logic [16:0] aon_auto_block_debounce_ctl_wdata;
   logic aon_auto_block_debounce_ctl_we;
   logic unused_aon_auto_block_debounce_ctl_wdata;
   logic aon_auto_block_debounce_ctl_regwen;

   always_comb begin
     aon_auto_block_debounce_ctl_qs = 17'h7d0;
     aon_auto_block_debounce_ctl_qs[15:0] = aon_auto_block_debounce_ctl_debounce_timer_qs_int;
     aon_auto_block_debounce_ctl_qs[16] = aon_auto_block_debounce_ctl_auto_block_enable_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(17),
     .ResetVal(17'h7d0),
     .BitMask(17'h1ffff),
     .DstWrReq(0)
   ) u_auto_block_debounce_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (auto_block_debounce_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[16:0]),
     .src_busy_o   (auto_block_debounce_ctl_busy),
     .src_qs_o     (auto_block_debounce_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_auto_block_debounce_ctl_qs),
     .dst_we_o     (aon_auto_block_debounce_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_auto_block_debounce_ctl_regwen),
     .dst_wd_o     (aon_auto_block_debounce_ctl_wdata)
   );
   assign unused_aon_auto_block_debounce_ctl_wdata =
       ^aon_auto_block_debounce_ctl_wdata;

   logic  aon_auto_block_out_ctl_key0_out_sel_qs_int;
   logic  aon_auto_block_out_ctl_key1_out_sel_qs_int;
   logic  aon_auto_block_out_ctl_key2_out_sel_qs_int;
   logic  aon_auto_block_out_ctl_key0_out_value_qs_int;
   logic  aon_auto_block_out_ctl_key1_out_value_qs_int;
   logic  aon_auto_block_out_ctl_key2_out_value_qs_int;
   logic [6:0] aon_auto_block_out_ctl_qs;
   logic [6:0] aon_auto_block_out_ctl_wdata;
   logic aon_auto_block_out_ctl_we;
   logic unused_aon_auto_block_out_ctl_wdata;
   logic aon_auto_block_out_ctl_regwen;

   always_comb begin
     aon_auto_block_out_ctl_qs = 7'h0;
     aon_auto_block_out_ctl_qs[0] = aon_auto_block_out_ctl_key0_out_sel_qs_int;
     aon_auto_block_out_ctl_qs[1] = aon_auto_block_out_ctl_key1_out_sel_qs_int;
     aon_auto_block_out_ctl_qs[2] = aon_auto_block_out_ctl_key2_out_sel_qs_int;
     aon_auto_block_out_ctl_qs[4] = aon_auto_block_out_ctl_key0_out_value_qs_int;
     aon_auto_block_out_ctl_qs[5] = aon_auto_block_out_ctl_key1_out_value_qs_int;
     aon_auto_block_out_ctl_qs[6] = aon_auto_block_out_ctl_key2_out_value_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(7),
     .ResetVal(7'h0),
     .BitMask(7'h77),
     .DstWrReq(0)
   ) u_auto_block_out_ctl_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (auto_block_out_ctl_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[6:0]),
     .src_busy_o   (auto_block_out_ctl_busy),
     .src_qs_o     (auto_block_out_ctl_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_auto_block_out_ctl_qs),
     .dst_we_o     (aon_auto_block_out_ctl_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_auto_block_out_ctl_regwen),
     .dst_wd_o     (aon_auto_block_out_ctl_wdata)
   );
   assign unused_aon_auto_block_out_ctl_wdata =
       ^aon_auto_block_out_ctl_wdata;

   logic  aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int;
   logic  aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int;
   logic  aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int;
   logic  aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int;
   logic  aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int;
   logic [4:0] aon_com_pre_sel_ctl_0_qs;
   logic [4:0] aon_com_pre_sel_ctl_0_wdata;
   logic aon_com_pre_sel_ctl_0_we;
   logic unused_aon_com_pre_sel_ctl_0_wdata;
   logic aon_com_pre_sel_ctl_0_regwen;

   always_comb begin
     aon_com_pre_sel_ctl_0_qs = 5'h0;
     aon_com_pre_sel_ctl_0_qs[0] = aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int;
     aon_com_pre_sel_ctl_0_qs[1] = aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int;
     aon_com_pre_sel_ctl_0_qs[2] = aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int;
     aon_com_pre_sel_ctl_0_qs[3] = aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int;
     aon_com_pre_sel_ctl_0_qs[4] = aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_pre_sel_ctl_0_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_sel_ctl_0_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_pre_sel_ctl_0_busy),
     .src_qs_o     (com_pre_sel_ctl_0_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_sel_ctl_0_qs),
     .dst_we_o     (aon_com_pre_sel_ctl_0_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_sel_ctl_0_regwen),
     .dst_wd_o     (aon_com_pre_sel_ctl_0_wdata)
   );
   assign unused_aon_com_pre_sel_ctl_0_wdata =
       ^aon_com_pre_sel_ctl_0_wdata;

   logic  aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int;
   logic  aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int;
   logic  aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int;
   logic  aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int;
   logic  aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int;
   logic [4:0] aon_com_pre_sel_ctl_1_qs;
   logic [4:0] aon_com_pre_sel_ctl_1_wdata;
   logic aon_com_pre_sel_ctl_1_we;
   logic unused_aon_com_pre_sel_ctl_1_wdata;
   logic aon_com_pre_sel_ctl_1_regwen;

   always_comb begin
     aon_com_pre_sel_ctl_1_qs = 5'h0;
     aon_com_pre_sel_ctl_1_qs[0] = aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int;
     aon_com_pre_sel_ctl_1_qs[1] = aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int;
     aon_com_pre_sel_ctl_1_qs[2] = aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int;
     aon_com_pre_sel_ctl_1_qs[3] = aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int;
     aon_com_pre_sel_ctl_1_qs[4] = aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_pre_sel_ctl_1_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_sel_ctl_1_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_pre_sel_ctl_1_busy),
     .src_qs_o     (com_pre_sel_ctl_1_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_sel_ctl_1_qs),
     .dst_we_o     (aon_com_pre_sel_ctl_1_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_sel_ctl_1_regwen),
     .dst_wd_o     (aon_com_pre_sel_ctl_1_wdata)
   );
   assign unused_aon_com_pre_sel_ctl_1_wdata =
       ^aon_com_pre_sel_ctl_1_wdata;

   logic  aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int;
   logic  aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int;
   logic  aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int;
   logic  aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int;
   logic  aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int;
   logic [4:0] aon_com_pre_sel_ctl_2_qs;
   logic [4:0] aon_com_pre_sel_ctl_2_wdata;
   logic aon_com_pre_sel_ctl_2_we;
   logic unused_aon_com_pre_sel_ctl_2_wdata;
   logic aon_com_pre_sel_ctl_2_regwen;

   always_comb begin
     aon_com_pre_sel_ctl_2_qs = 5'h0;
     aon_com_pre_sel_ctl_2_qs[0] = aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int;
     aon_com_pre_sel_ctl_2_qs[1] = aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int;
     aon_com_pre_sel_ctl_2_qs[2] = aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int;
     aon_com_pre_sel_ctl_2_qs[3] = aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int;
     aon_com_pre_sel_ctl_2_qs[4] = aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_pre_sel_ctl_2_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_sel_ctl_2_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_pre_sel_ctl_2_busy),
     .src_qs_o     (com_pre_sel_ctl_2_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_sel_ctl_2_qs),
     .dst_we_o     (aon_com_pre_sel_ctl_2_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_sel_ctl_2_regwen),
     .dst_wd_o     (aon_com_pre_sel_ctl_2_wdata)
   );
   assign unused_aon_com_pre_sel_ctl_2_wdata =
       ^aon_com_pre_sel_ctl_2_wdata;

   logic  aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int;
   logic  aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int;
   logic  aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int;
   logic  aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int;
   logic  aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int;
   logic [4:0] aon_com_pre_sel_ctl_3_qs;
   logic [4:0] aon_com_pre_sel_ctl_3_wdata;
   logic aon_com_pre_sel_ctl_3_we;
   logic unused_aon_com_pre_sel_ctl_3_wdata;
   logic aon_com_pre_sel_ctl_3_regwen;

   always_comb begin
     aon_com_pre_sel_ctl_3_qs = 5'h0;
     aon_com_pre_sel_ctl_3_qs[0] = aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int;
     aon_com_pre_sel_ctl_3_qs[1] = aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int;
     aon_com_pre_sel_ctl_3_qs[2] = aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int;
     aon_com_pre_sel_ctl_3_qs[3] = aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int;
     aon_com_pre_sel_ctl_3_qs[4] = aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_pre_sel_ctl_3_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_sel_ctl_3_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_pre_sel_ctl_3_busy),
     .src_qs_o     (com_pre_sel_ctl_3_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_sel_ctl_3_qs),
     .dst_we_o     (aon_com_pre_sel_ctl_3_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_sel_ctl_3_regwen),
     .dst_wd_o     (aon_com_pre_sel_ctl_3_wdata)
   );
   assign unused_aon_com_pre_sel_ctl_3_wdata =
       ^aon_com_pre_sel_ctl_3_wdata;

   logic [31:0]  aon_com_pre_det_ctl_0_qs_int;
   logic [31:0] aon_com_pre_det_ctl_0_qs;
   logic [31:0] aon_com_pre_det_ctl_0_wdata;
   logic aon_com_pre_det_ctl_0_we;
   logic unused_aon_com_pre_det_ctl_0_wdata;
   logic aon_com_pre_det_ctl_0_regwen;

   always_comb begin
     aon_com_pre_det_ctl_0_qs = 32'h0;
     aon_com_pre_det_ctl_0_qs = aon_com_pre_det_ctl_0_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_pre_det_ctl_0_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_det_ctl_0_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_pre_det_ctl_0_busy),
     .src_qs_o     (com_pre_det_ctl_0_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_det_ctl_0_qs),
     .dst_we_o     (aon_com_pre_det_ctl_0_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_det_ctl_0_regwen),
     .dst_wd_o     (aon_com_pre_det_ctl_0_wdata)
   );
   assign unused_aon_com_pre_det_ctl_0_wdata =
       ^aon_com_pre_det_ctl_0_wdata;

   logic [31:0]  aon_com_pre_det_ctl_1_qs_int;
   logic [31:0] aon_com_pre_det_ctl_1_qs;
   logic [31:0] aon_com_pre_det_ctl_1_wdata;
   logic aon_com_pre_det_ctl_1_we;
   logic unused_aon_com_pre_det_ctl_1_wdata;
   logic aon_com_pre_det_ctl_1_regwen;

   always_comb begin
     aon_com_pre_det_ctl_1_qs = 32'h0;
     aon_com_pre_det_ctl_1_qs = aon_com_pre_det_ctl_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_pre_det_ctl_1_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_det_ctl_1_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_pre_det_ctl_1_busy),
     .src_qs_o     (com_pre_det_ctl_1_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_det_ctl_1_qs),
     .dst_we_o     (aon_com_pre_det_ctl_1_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_det_ctl_1_regwen),
     .dst_wd_o     (aon_com_pre_det_ctl_1_wdata)
   );
   assign unused_aon_com_pre_det_ctl_1_wdata =
       ^aon_com_pre_det_ctl_1_wdata;

   logic [31:0]  aon_com_pre_det_ctl_2_qs_int;
   logic [31:0] aon_com_pre_det_ctl_2_qs;
   logic [31:0] aon_com_pre_det_ctl_2_wdata;
   logic aon_com_pre_det_ctl_2_we;
   logic unused_aon_com_pre_det_ctl_2_wdata;
   logic aon_com_pre_det_ctl_2_regwen;

   always_comb begin
     aon_com_pre_det_ctl_2_qs = 32'h0;
     aon_com_pre_det_ctl_2_qs = aon_com_pre_det_ctl_2_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_pre_det_ctl_2_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_det_ctl_2_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_pre_det_ctl_2_busy),
     .src_qs_o     (com_pre_det_ctl_2_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_det_ctl_2_qs),
     .dst_we_o     (aon_com_pre_det_ctl_2_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_det_ctl_2_regwen),
     .dst_wd_o     (aon_com_pre_det_ctl_2_wdata)
   );
   assign unused_aon_com_pre_det_ctl_2_wdata =
       ^aon_com_pre_det_ctl_2_wdata;

   logic [31:0]  aon_com_pre_det_ctl_3_qs_int;
   logic [31:0] aon_com_pre_det_ctl_3_qs;
   logic [31:0] aon_com_pre_det_ctl_3_wdata;
   logic aon_com_pre_det_ctl_3_we;
   logic unused_aon_com_pre_det_ctl_3_wdata;
   logic aon_com_pre_det_ctl_3_regwen;

   always_comb begin
     aon_com_pre_det_ctl_3_qs = 32'h0;
     aon_com_pre_det_ctl_3_qs = aon_com_pre_det_ctl_3_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_pre_det_ctl_3_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_pre_det_ctl_3_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_pre_det_ctl_3_busy),
     .src_qs_o     (com_pre_det_ctl_3_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_pre_det_ctl_3_qs),
     .dst_we_o     (aon_com_pre_det_ctl_3_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_pre_det_ctl_3_regwen),
     .dst_wd_o     (aon_com_pre_det_ctl_3_wdata)
   );
   assign unused_aon_com_pre_det_ctl_3_wdata =
       ^aon_com_pre_det_ctl_3_wdata;

   logic  aon_com_sel_ctl_0_key0_in_sel_0_qs_int;
   logic  aon_com_sel_ctl_0_key1_in_sel_0_qs_int;
   logic  aon_com_sel_ctl_0_key2_in_sel_0_qs_int;
   logic  aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int;
   logic  aon_com_sel_ctl_0_ac_present_sel_0_qs_int;
   logic [4:0] aon_com_sel_ctl_0_qs;
   logic [4:0] aon_com_sel_ctl_0_wdata;
   logic aon_com_sel_ctl_0_we;
   logic unused_aon_com_sel_ctl_0_wdata;
   logic aon_com_sel_ctl_0_regwen;

   always_comb begin
     aon_com_sel_ctl_0_qs = 5'h0;
     aon_com_sel_ctl_0_qs[0] = aon_com_sel_ctl_0_key0_in_sel_0_qs_int;
     aon_com_sel_ctl_0_qs[1] = aon_com_sel_ctl_0_key1_in_sel_0_qs_int;
     aon_com_sel_ctl_0_qs[2] = aon_com_sel_ctl_0_key2_in_sel_0_qs_int;
     aon_com_sel_ctl_0_qs[3] = aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int;
     aon_com_sel_ctl_0_qs[4] = aon_com_sel_ctl_0_ac_present_sel_0_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_sel_ctl_0_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_sel_ctl_0_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_sel_ctl_0_busy),
     .src_qs_o     (com_sel_ctl_0_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_sel_ctl_0_qs),
     .dst_we_o     (aon_com_sel_ctl_0_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_sel_ctl_0_regwen),
     .dst_wd_o     (aon_com_sel_ctl_0_wdata)
   );
   assign unused_aon_com_sel_ctl_0_wdata =
       ^aon_com_sel_ctl_0_wdata;

   logic  aon_com_sel_ctl_1_key0_in_sel_1_qs_int;
   logic  aon_com_sel_ctl_1_key1_in_sel_1_qs_int;
   logic  aon_com_sel_ctl_1_key2_in_sel_1_qs_int;
   logic  aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int;
   logic  aon_com_sel_ctl_1_ac_present_sel_1_qs_int;
   logic [4:0] aon_com_sel_ctl_1_qs;
   logic [4:0] aon_com_sel_ctl_1_wdata;
   logic aon_com_sel_ctl_1_we;
   logic unused_aon_com_sel_ctl_1_wdata;
   logic aon_com_sel_ctl_1_regwen;

   always_comb begin
     aon_com_sel_ctl_1_qs = 5'h0;
     aon_com_sel_ctl_1_qs[0] = aon_com_sel_ctl_1_key0_in_sel_1_qs_int;
     aon_com_sel_ctl_1_qs[1] = aon_com_sel_ctl_1_key1_in_sel_1_qs_int;
     aon_com_sel_ctl_1_qs[2] = aon_com_sel_ctl_1_key2_in_sel_1_qs_int;
     aon_com_sel_ctl_1_qs[3] = aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int;
     aon_com_sel_ctl_1_qs[4] = aon_com_sel_ctl_1_ac_present_sel_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_sel_ctl_1_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_sel_ctl_1_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_sel_ctl_1_busy),
     .src_qs_o     (com_sel_ctl_1_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_sel_ctl_1_qs),
     .dst_we_o     (aon_com_sel_ctl_1_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_sel_ctl_1_regwen),
     .dst_wd_o     (aon_com_sel_ctl_1_wdata)
   );
   assign unused_aon_com_sel_ctl_1_wdata =
       ^aon_com_sel_ctl_1_wdata;

   logic  aon_com_sel_ctl_2_key0_in_sel_2_qs_int;
   logic  aon_com_sel_ctl_2_key1_in_sel_2_qs_int;
   logic  aon_com_sel_ctl_2_key2_in_sel_2_qs_int;
   logic  aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int;
   logic  aon_com_sel_ctl_2_ac_present_sel_2_qs_int;
   logic [4:0] aon_com_sel_ctl_2_qs;
   logic [4:0] aon_com_sel_ctl_2_wdata;
   logic aon_com_sel_ctl_2_we;
   logic unused_aon_com_sel_ctl_2_wdata;
   logic aon_com_sel_ctl_2_regwen;

   always_comb begin
     aon_com_sel_ctl_2_qs = 5'h0;
     aon_com_sel_ctl_2_qs[0] = aon_com_sel_ctl_2_key0_in_sel_2_qs_int;
     aon_com_sel_ctl_2_qs[1] = aon_com_sel_ctl_2_key1_in_sel_2_qs_int;
     aon_com_sel_ctl_2_qs[2] = aon_com_sel_ctl_2_key2_in_sel_2_qs_int;
     aon_com_sel_ctl_2_qs[3] = aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int;
     aon_com_sel_ctl_2_qs[4] = aon_com_sel_ctl_2_ac_present_sel_2_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_sel_ctl_2_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_sel_ctl_2_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_sel_ctl_2_busy),
     .src_qs_o     (com_sel_ctl_2_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_sel_ctl_2_qs),
     .dst_we_o     (aon_com_sel_ctl_2_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_sel_ctl_2_regwen),
     .dst_wd_o     (aon_com_sel_ctl_2_wdata)
   );
   assign unused_aon_com_sel_ctl_2_wdata =
       ^aon_com_sel_ctl_2_wdata;

   logic  aon_com_sel_ctl_3_key0_in_sel_3_qs_int;
   logic  aon_com_sel_ctl_3_key1_in_sel_3_qs_int;
   logic  aon_com_sel_ctl_3_key2_in_sel_3_qs_int;
   logic  aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int;
   logic  aon_com_sel_ctl_3_ac_present_sel_3_qs_int;
   logic [4:0] aon_com_sel_ctl_3_qs;
   logic [4:0] aon_com_sel_ctl_3_wdata;
   logic aon_com_sel_ctl_3_we;
   logic unused_aon_com_sel_ctl_3_wdata;
   logic aon_com_sel_ctl_3_regwen;

   always_comb begin
     aon_com_sel_ctl_3_qs = 5'h0;
     aon_com_sel_ctl_3_qs[0] = aon_com_sel_ctl_3_key0_in_sel_3_qs_int;
     aon_com_sel_ctl_3_qs[1] = aon_com_sel_ctl_3_key1_in_sel_3_qs_int;
     aon_com_sel_ctl_3_qs[2] = aon_com_sel_ctl_3_key2_in_sel_3_qs_int;
     aon_com_sel_ctl_3_qs[3] = aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int;
     aon_com_sel_ctl_3_qs[4] = aon_com_sel_ctl_3_ac_present_sel_3_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(5),
     .ResetVal(5'h0),
     .BitMask(5'h1f),
     .DstWrReq(0)
   ) u_com_sel_ctl_3_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_sel_ctl_3_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[4:0]),
     .src_busy_o   (com_sel_ctl_3_busy),
     .src_qs_o     (com_sel_ctl_3_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_sel_ctl_3_qs),
     .dst_we_o     (aon_com_sel_ctl_3_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_sel_ctl_3_regwen),
     .dst_wd_o     (aon_com_sel_ctl_3_wdata)
   );
   assign unused_aon_com_sel_ctl_3_wdata =
       ^aon_com_sel_ctl_3_wdata;

   logic [31:0]  aon_com_det_ctl_0_qs_int;
   logic [31:0] aon_com_det_ctl_0_qs;
   logic [31:0] aon_com_det_ctl_0_wdata;
   logic aon_com_det_ctl_0_we;
   logic unused_aon_com_det_ctl_0_wdata;
   logic aon_com_det_ctl_0_regwen;

   always_comb begin
     aon_com_det_ctl_0_qs = 32'h0;
     aon_com_det_ctl_0_qs = aon_com_det_ctl_0_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_det_ctl_0_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_det_ctl_0_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_det_ctl_0_busy),
     .src_qs_o     (com_det_ctl_0_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_det_ctl_0_qs),
     .dst_we_o     (aon_com_det_ctl_0_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_det_ctl_0_regwen),
     .dst_wd_o     (aon_com_det_ctl_0_wdata)
   );
   assign unused_aon_com_det_ctl_0_wdata =
       ^aon_com_det_ctl_0_wdata;

   logic [31:0]  aon_com_det_ctl_1_qs_int;
   logic [31:0] aon_com_det_ctl_1_qs;
   logic [31:0] aon_com_det_ctl_1_wdata;
   logic aon_com_det_ctl_1_we;
   logic unused_aon_com_det_ctl_1_wdata;
   logic aon_com_det_ctl_1_regwen;

   always_comb begin
     aon_com_det_ctl_1_qs = 32'h0;
     aon_com_det_ctl_1_qs = aon_com_det_ctl_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_det_ctl_1_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_det_ctl_1_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_det_ctl_1_busy),
     .src_qs_o     (com_det_ctl_1_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_det_ctl_1_qs),
     .dst_we_o     (aon_com_det_ctl_1_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_det_ctl_1_regwen),
     .dst_wd_o     (aon_com_det_ctl_1_wdata)
   );
   assign unused_aon_com_det_ctl_1_wdata =
       ^aon_com_det_ctl_1_wdata;

   logic [31:0]  aon_com_det_ctl_2_qs_int;
   logic [31:0] aon_com_det_ctl_2_qs;
   logic [31:0] aon_com_det_ctl_2_wdata;
   logic aon_com_det_ctl_2_we;
   logic unused_aon_com_det_ctl_2_wdata;
   logic aon_com_det_ctl_2_regwen;

   always_comb begin
     aon_com_det_ctl_2_qs = 32'h0;
     aon_com_det_ctl_2_qs = aon_com_det_ctl_2_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_det_ctl_2_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_det_ctl_2_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_det_ctl_2_busy),
     .src_qs_o     (com_det_ctl_2_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_det_ctl_2_qs),
     .dst_we_o     (aon_com_det_ctl_2_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_det_ctl_2_regwen),
     .dst_wd_o     (aon_com_det_ctl_2_wdata)
   );
   assign unused_aon_com_det_ctl_2_wdata =
       ^aon_com_det_ctl_2_wdata;

   logic [31:0]  aon_com_det_ctl_3_qs_int;
   logic [31:0] aon_com_det_ctl_3_qs;
   logic [31:0] aon_com_det_ctl_3_wdata;
   logic aon_com_det_ctl_3_we;
   logic unused_aon_com_det_ctl_3_wdata;
   logic aon_com_det_ctl_3_regwen;

   always_comb begin
     aon_com_det_ctl_3_qs = 32'h0;
     aon_com_det_ctl_3_qs = aon_com_det_ctl_3_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(32),
     .ResetVal(32'h0),
     .BitMask(32'hffffffff),
     .DstWrReq(0)
   ) u_com_det_ctl_3_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_det_ctl_3_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[31:0]),
     .src_busy_o   (com_det_ctl_3_busy),
     .src_qs_o     (com_det_ctl_3_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_det_ctl_3_qs),
     .dst_we_o     (aon_com_det_ctl_3_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_det_ctl_3_regwen),
     .dst_wd_o     (aon_com_det_ctl_3_wdata)
   );
   assign unused_aon_com_det_ctl_3_wdata =
       ^aon_com_det_ctl_3_wdata;

   logic  aon_com_out_ctl_0_bat_disable_0_qs_int;
   logic  aon_com_out_ctl_0_interrupt_0_qs_int;
   logic  aon_com_out_ctl_0_ec_rst_0_qs_int;
   logic  aon_com_out_ctl_0_rst_req_0_qs_int;
   logic [3:0] aon_com_out_ctl_0_qs;
   logic [3:0] aon_com_out_ctl_0_wdata;
   logic aon_com_out_ctl_0_we;
   logic unused_aon_com_out_ctl_0_wdata;
   logic aon_com_out_ctl_0_regwen;

   always_comb begin
     aon_com_out_ctl_0_qs = 4'h0;
     aon_com_out_ctl_0_qs[0] = aon_com_out_ctl_0_bat_disable_0_qs_int;
     aon_com_out_ctl_0_qs[1] = aon_com_out_ctl_0_interrupt_0_qs_int;
     aon_com_out_ctl_0_qs[2] = aon_com_out_ctl_0_ec_rst_0_qs_int;
     aon_com_out_ctl_0_qs[3] = aon_com_out_ctl_0_rst_req_0_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(4),
     .ResetVal(4'h0),
     .BitMask(4'hf),
     .DstWrReq(0)
   ) u_com_out_ctl_0_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_out_ctl_0_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[3:0]),
     .src_busy_o   (com_out_ctl_0_busy),
     .src_qs_o     (com_out_ctl_0_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_out_ctl_0_qs),
     .dst_we_o     (aon_com_out_ctl_0_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_out_ctl_0_regwen),
     .dst_wd_o     (aon_com_out_ctl_0_wdata)
   );
   assign unused_aon_com_out_ctl_0_wdata =
       ^aon_com_out_ctl_0_wdata;

   logic  aon_com_out_ctl_1_bat_disable_1_qs_int;
   logic  aon_com_out_ctl_1_interrupt_1_qs_int;
   logic  aon_com_out_ctl_1_ec_rst_1_qs_int;
   logic  aon_com_out_ctl_1_rst_req_1_qs_int;
   logic [3:0] aon_com_out_ctl_1_qs;
   logic [3:0] aon_com_out_ctl_1_wdata;
   logic aon_com_out_ctl_1_we;
   logic unused_aon_com_out_ctl_1_wdata;
   logic aon_com_out_ctl_1_regwen;

   always_comb begin
     aon_com_out_ctl_1_qs = 4'h0;
     aon_com_out_ctl_1_qs[0] = aon_com_out_ctl_1_bat_disable_1_qs_int;
     aon_com_out_ctl_1_qs[1] = aon_com_out_ctl_1_interrupt_1_qs_int;
     aon_com_out_ctl_1_qs[2] = aon_com_out_ctl_1_ec_rst_1_qs_int;
     aon_com_out_ctl_1_qs[3] = aon_com_out_ctl_1_rst_req_1_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(4),
     .ResetVal(4'h0),
     .BitMask(4'hf),
     .DstWrReq(0)
   ) u_com_out_ctl_1_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_out_ctl_1_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[3:0]),
     .src_busy_o   (com_out_ctl_1_busy),
     .src_qs_o     (com_out_ctl_1_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_out_ctl_1_qs),
     .dst_we_o     (aon_com_out_ctl_1_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_out_ctl_1_regwen),
     .dst_wd_o     (aon_com_out_ctl_1_wdata)
   );
   assign unused_aon_com_out_ctl_1_wdata =
       ^aon_com_out_ctl_1_wdata;

   logic  aon_com_out_ctl_2_bat_disable_2_qs_int;
   logic  aon_com_out_ctl_2_interrupt_2_qs_int;
   logic  aon_com_out_ctl_2_ec_rst_2_qs_int;
   logic  aon_com_out_ctl_2_rst_req_2_qs_int;
   logic [3:0] aon_com_out_ctl_2_qs;
   logic [3:0] aon_com_out_ctl_2_wdata;
   logic aon_com_out_ctl_2_we;
   logic unused_aon_com_out_ctl_2_wdata;
   logic aon_com_out_ctl_2_regwen;

   always_comb begin
     aon_com_out_ctl_2_qs = 4'h0;
     aon_com_out_ctl_2_qs[0] = aon_com_out_ctl_2_bat_disable_2_qs_int;
     aon_com_out_ctl_2_qs[1] = aon_com_out_ctl_2_interrupt_2_qs_int;
     aon_com_out_ctl_2_qs[2] = aon_com_out_ctl_2_ec_rst_2_qs_int;
     aon_com_out_ctl_2_qs[3] = aon_com_out_ctl_2_rst_req_2_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(4),
     .ResetVal(4'h0),
     .BitMask(4'hf),
     .DstWrReq(0)
   ) u_com_out_ctl_2_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_out_ctl_2_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[3:0]),
     .src_busy_o   (com_out_ctl_2_busy),
     .src_qs_o     (com_out_ctl_2_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_out_ctl_2_qs),
     .dst_we_o     (aon_com_out_ctl_2_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_out_ctl_2_regwen),
     .dst_wd_o     (aon_com_out_ctl_2_wdata)
   );
   assign unused_aon_com_out_ctl_2_wdata =
       ^aon_com_out_ctl_2_wdata;

   logic  aon_com_out_ctl_3_bat_disable_3_qs_int;
   logic  aon_com_out_ctl_3_interrupt_3_qs_int;
   logic  aon_com_out_ctl_3_ec_rst_3_qs_int;
   logic  aon_com_out_ctl_3_rst_req_3_qs_int;
   logic [3:0] aon_com_out_ctl_3_qs;
   logic [3:0] aon_com_out_ctl_3_wdata;
   logic aon_com_out_ctl_3_we;
   logic unused_aon_com_out_ctl_3_wdata;
   logic aon_com_out_ctl_3_regwen;

   always_comb begin
     aon_com_out_ctl_3_qs = 4'h0;
     aon_com_out_ctl_3_qs[0] = aon_com_out_ctl_3_bat_disable_3_qs_int;
     aon_com_out_ctl_3_qs[1] = aon_com_out_ctl_3_interrupt_3_qs_int;
     aon_com_out_ctl_3_qs[2] = aon_com_out_ctl_3_ec_rst_3_qs_int;
     aon_com_out_ctl_3_qs[3] = aon_com_out_ctl_3_rst_req_3_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(4),
     .ResetVal(4'h0),
     .BitMask(4'hf),
     .DstWrReq(0)
   ) u_com_out_ctl_3_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i (regwen_qs),
     .src_we_i     (com_out_ctl_3_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[3:0]),
     .src_busy_o   (com_out_ctl_3_busy),
     .src_qs_o     (com_out_ctl_3_qs), // for software read back
     .dst_update_i ('0),
     .dst_ds_i     ('0),
     .dst_qs_i     (aon_com_out_ctl_3_qs),
     .dst_we_o     (aon_com_out_ctl_3_we),
     .dst_re_o     (),
     .dst_regwen_o (aon_com_out_ctl_3_regwen),
     .dst_wd_o     (aon_com_out_ctl_3_wdata)
   );
   assign unused_aon_com_out_ctl_3_wdata =
       ^aon_com_out_ctl_3_wdata;

   logic  aon_combo_intr_status_combo0_h2l_ds_int;
   logic  aon_combo_intr_status_combo0_h2l_qs_int;
   logic  aon_combo_intr_status_combo1_h2l_ds_int;
   logic  aon_combo_intr_status_combo1_h2l_qs_int;
   logic  aon_combo_intr_status_combo2_h2l_ds_int;
   logic  aon_combo_intr_status_combo2_h2l_qs_int;
   logic  aon_combo_intr_status_combo3_h2l_ds_int;
   logic  aon_combo_intr_status_combo3_h2l_qs_int;
   logic [3:0] aon_combo_intr_status_ds;
   logic aon_combo_intr_status_qe;
   logic [3:0] aon_combo_intr_status_qs;
   logic [3:0] aon_combo_intr_status_wdata;
   logic aon_combo_intr_status_we;
   logic unused_aon_combo_intr_status_wdata;

   always_comb begin
     aon_combo_intr_status_qs = 4'h0;
     aon_combo_intr_status_ds = 4'h0;
     aon_combo_intr_status_ds[0] = aon_combo_intr_status_combo0_h2l_ds_int;
     aon_combo_intr_status_qs[0] = aon_combo_intr_status_combo0_h2l_qs_int;
     aon_combo_intr_status_ds[1] = aon_combo_intr_status_combo1_h2l_ds_int;
     aon_combo_intr_status_qs[1] = aon_combo_intr_status_combo1_h2l_qs_int;
     aon_combo_intr_status_ds[2] = aon_combo_intr_status_combo2_h2l_ds_int;
     aon_combo_intr_status_qs[2] = aon_combo_intr_status_combo2_h2l_qs_int;
     aon_combo_intr_status_ds[3] = aon_combo_intr_status_combo3_h2l_ds_int;
     aon_combo_intr_status_qs[3] = aon_combo_intr_status_combo3_h2l_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(4),
     .ResetVal(4'h0),
     .BitMask(4'hf),
     .DstWrReq(1)
   ) u_combo_intr_status_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (combo_intr_status_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[3:0]),
     .src_busy_o   (combo_intr_status_busy),
     .src_qs_o     (combo_intr_status_qs), // for software read back
     .dst_update_i (aon_combo_intr_status_qe),
     .dst_ds_i     (aon_combo_intr_status_ds),
     .dst_qs_i     (aon_combo_intr_status_qs),
     .dst_we_o     (aon_combo_intr_status_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_combo_intr_status_wdata)
   );
   assign unused_aon_combo_intr_status_wdata =
       ^aon_combo_intr_status_wdata;

   logic  aon_key_intr_status_pwrb_h2l_ds_int;
   logic  aon_key_intr_status_pwrb_h2l_qs_int;
   logic  aon_key_intr_status_key0_in_h2l_ds_int;
   logic  aon_key_intr_status_key0_in_h2l_qs_int;
   logic  aon_key_intr_status_key1_in_h2l_ds_int;
   logic  aon_key_intr_status_key1_in_h2l_qs_int;
   logic  aon_key_intr_status_key2_in_h2l_ds_int;
   logic  aon_key_intr_status_key2_in_h2l_qs_int;
   logic  aon_key_intr_status_ac_present_h2l_ds_int;
   logic  aon_key_intr_status_ac_present_h2l_qs_int;
   logic  aon_key_intr_status_ec_rst_l_h2l_ds_int;
   logic  aon_key_intr_status_ec_rst_l_h2l_qs_int;
   logic  aon_key_intr_status_flash_wp_l_h2l_ds_int;
   logic  aon_key_intr_status_flash_wp_l_h2l_qs_int;
   logic  aon_key_intr_status_pwrb_l2h_ds_int;
   logic  aon_key_intr_status_pwrb_l2h_qs_int;
   logic  aon_key_intr_status_key0_in_l2h_ds_int;
   logic  aon_key_intr_status_key0_in_l2h_qs_int;
   logic  aon_key_intr_status_key1_in_l2h_ds_int;
   logic  aon_key_intr_status_key1_in_l2h_qs_int;
   logic  aon_key_intr_status_key2_in_l2h_ds_int;
   logic  aon_key_intr_status_key2_in_l2h_qs_int;
   logic  aon_key_intr_status_ac_present_l2h_ds_int;
   logic  aon_key_intr_status_ac_present_l2h_qs_int;
   logic  aon_key_intr_status_ec_rst_l_l2h_ds_int;
   logic  aon_key_intr_status_ec_rst_l_l2h_qs_int;
   logic  aon_key_intr_status_flash_wp_l_l2h_ds_int;
   logic  aon_key_intr_status_flash_wp_l_l2h_qs_int;
   logic [13:0] aon_key_intr_status_ds;
   logic aon_key_intr_status_qe;
   logic [13:0] aon_key_intr_status_qs;
   logic [13:0] aon_key_intr_status_wdata;
   logic aon_key_intr_status_we;
   logic unused_aon_key_intr_status_wdata;

   always_comb begin
     aon_key_intr_status_qs = 14'h0;
     aon_key_intr_status_ds = 14'h0;
     aon_key_intr_status_ds[0] = aon_key_intr_status_pwrb_h2l_ds_int;
     aon_key_intr_status_qs[0] = aon_key_intr_status_pwrb_h2l_qs_int;
     aon_key_intr_status_ds[1] = aon_key_intr_status_key0_in_h2l_ds_int;
     aon_key_intr_status_qs[1] = aon_key_intr_status_key0_in_h2l_qs_int;
     aon_key_intr_status_ds[2] = aon_key_intr_status_key1_in_h2l_ds_int;
     aon_key_intr_status_qs[2] = aon_key_intr_status_key1_in_h2l_qs_int;
     aon_key_intr_status_ds[3] = aon_key_intr_status_key2_in_h2l_ds_int;
     aon_key_intr_status_qs[3] = aon_key_intr_status_key2_in_h2l_qs_int;
     aon_key_intr_status_ds[4] = aon_key_intr_status_ac_present_h2l_ds_int;
     aon_key_intr_status_qs[4] = aon_key_intr_status_ac_present_h2l_qs_int;
     aon_key_intr_status_ds[5] = aon_key_intr_status_ec_rst_l_h2l_ds_int;
     aon_key_intr_status_qs[5] = aon_key_intr_status_ec_rst_l_h2l_qs_int;
     aon_key_intr_status_ds[6] = aon_key_intr_status_flash_wp_l_h2l_ds_int;
     aon_key_intr_status_qs[6] = aon_key_intr_status_flash_wp_l_h2l_qs_int;
     aon_key_intr_status_ds[7] = aon_key_intr_status_pwrb_l2h_ds_int;
     aon_key_intr_status_qs[7] = aon_key_intr_status_pwrb_l2h_qs_int;
     aon_key_intr_status_ds[8] = aon_key_intr_status_key0_in_l2h_ds_int;
     aon_key_intr_status_qs[8] = aon_key_intr_status_key0_in_l2h_qs_int;
     aon_key_intr_status_ds[9] = aon_key_intr_status_key1_in_l2h_ds_int;
     aon_key_intr_status_qs[9] = aon_key_intr_status_key1_in_l2h_qs_int;
     aon_key_intr_status_ds[10] = aon_key_intr_status_key2_in_l2h_ds_int;
     aon_key_intr_status_qs[10] = aon_key_intr_status_key2_in_l2h_qs_int;
     aon_key_intr_status_ds[11] = aon_key_intr_status_ac_present_l2h_ds_int;
     aon_key_intr_status_qs[11] = aon_key_intr_status_ac_present_l2h_qs_int;
     aon_key_intr_status_ds[12] = aon_key_intr_status_ec_rst_l_l2h_ds_int;
     aon_key_intr_status_qs[12] = aon_key_intr_status_ec_rst_l_l2h_qs_int;
     aon_key_intr_status_ds[13] = aon_key_intr_status_flash_wp_l_l2h_ds_int;
     aon_key_intr_status_qs[13] = aon_key_intr_status_flash_wp_l_l2h_qs_int;
   end

   prim_reg_cdc #(
     .DataWidth(14),
     .ResetVal(14'h0),
     .BitMask(14'h3fff),
     .DstWrReq(1)
   ) u_key_intr_status_cdc (
     .clk_src_i    (clk_i),
     .rst_src_ni   (rst_ni),
     .clk_dst_i    (clk_aon_i),
     .rst_dst_ni   (rst_aon_ni),
     .src_regwen_i ('0),
     .src_we_i     (key_intr_status_we),
     .src_re_i     ('0),
     .src_wd_i     (reg_wdata[13:0]),
     .src_busy_o   (key_intr_status_busy),
     .src_qs_o     (key_intr_status_qs), // for software read back
     .dst_update_i (aon_key_intr_status_qe),
     .dst_ds_i     (aon_key_intr_status_ds),
     .dst_qs_i     (aon_key_intr_status_qs),
     .dst_we_o     (aon_key_intr_status_we),
     .dst_re_o     (),
     .dst_regwen_o (),
     .dst_wd_o     (aon_key_intr_status_wdata)
   );
   assign unused_aon_key_intr_status_wdata =
       ^aon_key_intr_status_wdata;

   // Register instances
   // R[intr_state]: V(False)
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_intr_state (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (intr_state_we),
     .wd     (intr_state_wd),

     // from internal hardware
     .de     (hw2reg.intr_state.de),
     .d      (hw2reg.intr_state.d),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.intr_state.q),
     .ds     (),

     // to register interface (read)
     .qs     (intr_state_qs)
   );


   // R[intr_enable]: V(False)
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_intr_enable (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (intr_enable_we),
     .wd     (intr_enable_wd),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.intr_enable.q),
     .ds     (),

     // to register interface (read)
     .qs     (intr_enable_qs)
   );


   // R[intr_test]: V(True)
   logic intr_test_qe;
   logic [0:0] intr_test_flds_we;
   assign intr_test_qe = &intr_test_flds_we;
   prim_subreg_ext #(
     .DW    (1)
   ) u_intr_test (
     .re     (1'b0),
     .we     (intr_test_we),
     .wd     (intr_test_wd),
     .d      ('0),
     .qre    (),
     .qe     (intr_test_flds_we[0]),
     .q      (reg2hw.intr_test.q),
     .ds     (),
     .qs     ()
   );
   assign reg2hw.intr_test.qe = intr_test_qe;


   // R[alert_test]: V(True)
   logic alert_test_qe;
   logic [0:0] alert_test_flds_we;
   assign alert_test_qe = &alert_test_flds_we;
   prim_subreg_ext #(
     .DW    (1)
   ) u_alert_test (
     .re     (1'b0),
     .we     (alert_test_we),
     .wd     (alert_test_wd),
     .d      ('0),
     .qre    (),
     .qe     (alert_test_flds_we[0]),
     .q      (reg2hw.alert_test.q),
     .ds     (),
     .qs     ()
   );
   assign reg2hw.alert_test.qe = alert_test_qe;


   // R[regwen]: V(False)
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW0C),
     .RESVAL  (1'h1)
   ) u_regwen (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (regwen_we),
     .wd     (regwen_wd),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (regwen_qs)
   );


   // R[ec_rst_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_ec_rst_ctl_gated_we;
   assign aon_ec_rst_ctl_gated_we = aon_ec_rst_ctl_we & aon_ec_rst_ctl_regwen;
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h7d0)
   ) u_ec_rst_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ec_rst_ctl_gated_we),
     .wd     (aon_ec_rst_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.ec_rst_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_ec_rst_ctl_qs_int)
   );


   // R[ulp_ac_debounce_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_ulp_ac_debounce_ctl_gated_we;
   assign aon_ulp_ac_debounce_ctl_gated_we =
     aon_ulp_ac_debounce_ctl_we & aon_ulp_ac_debounce_ctl_regwen;
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h1f40)
   ) u_ulp_ac_debounce_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ulp_ac_debounce_ctl_gated_we),
     .wd     (aon_ulp_ac_debounce_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.ulp_ac_debounce_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_ulp_ac_debounce_ctl_qs_int)
   );


   // R[ulp_lid_debounce_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_ulp_lid_debounce_ctl_gated_we;
   assign aon_ulp_lid_debounce_ctl_gated_we =
     aon_ulp_lid_debounce_ctl_we & aon_ulp_lid_debounce_ctl_regwen;
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h1f40)
   ) u_ulp_lid_debounce_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ulp_lid_debounce_ctl_gated_we),
     .wd     (aon_ulp_lid_debounce_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.ulp_lid_debounce_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_ulp_lid_debounce_ctl_qs_int)
   );


   // R[ulp_pwrb_debounce_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_ulp_pwrb_debounce_ctl_gated_we;
   assign aon_ulp_pwrb_debounce_ctl_gated_we =
     aon_ulp_pwrb_debounce_ctl_we & aon_ulp_pwrb_debounce_ctl_regwen;
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h1f40)
   ) u_ulp_pwrb_debounce_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ulp_pwrb_debounce_ctl_gated_we),
     .wd     (aon_ulp_pwrb_debounce_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.ulp_pwrb_debounce_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_ulp_pwrb_debounce_ctl_qs_int)
   );


   // R[ulp_ctl]: V(False)
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_ulp_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ulp_ctl_we),
     .wd     (aon_ulp_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.ulp_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_ulp_ctl_qs_int)
   );


   // R[ulp_status]: V(False)
   logic [0:0] ulp_status_flds_we;
   assign aon_ulp_status_qe = |ulp_status_flds_we;
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_ulp_status (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_ulp_status_we),
     .wd     (aon_ulp_status_wdata[0]),

     // from internal hardware
     .de     (hw2reg.ulp_status.de),
     .d      (hw2reg.ulp_status.d),

     // to internal hardware
     .qe     (ulp_status_flds_we[0]),
     .q      (),
     .ds     (aon_ulp_status_ds_int),

     // to register interface (read)
     .qs     (aon_ulp_status_qs_int)
   );


   // R[wkup_status]: V(False)
   logic [0:0] wkup_status_flds_we;
   assign aon_wkup_status_qe = |wkup_status_flds_we;
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_wkup_status (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_wkup_status_we),
     .wd     (aon_wkup_status_wdata[0]),

     // from internal hardware
     .de     (hw2reg.wkup_status.de),
     .d      (hw2reg.wkup_status.d),

     // to internal hardware
     .qe     (wkup_status_flds_we[0]),
     .q      (reg2hw.wkup_status.q),
     .ds     (aon_wkup_status_ds_int),

     // to register interface (read)
     .qs     (aon_wkup_status_qs_int)
   );


   // R[key_invert_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_key_invert_ctl_gated_we;
   assign aon_key_invert_ctl_gated_we = aon_key_invert_ctl_we & aon_key_invert_ctl_regwen;
   //   F[key0_in]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key0_in (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key0_in.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key0_in_qs_int)
   );

   //   F[key0_out]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key0_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key0_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key0_out_qs_int)
   );

   //   F[key1_in]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key1_in (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key1_in.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key1_in_qs_int)
   );

   //   F[key1_out]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key1_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key1_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key1_out_qs_int)
   );

   //   F[key2_in]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key2_in (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key2_in.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key2_in_qs_int)
   );

   //   F[key2_out]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_key2_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.key2_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_key2_out_qs_int)
   );

   //   F[pwrb_in]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_pwrb_in (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.pwrb_in.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_pwrb_in_qs_int)
   );

   //   F[pwrb_out]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_pwrb_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[7]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.pwrb_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_pwrb_out_qs_int)
   );

   //   F[ac_present]: 8:8
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_ac_present (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[8]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.ac_present.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_ac_present_qs_int)
   );

   //   F[bat_disable]: 9:9
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_bat_disable (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[9]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_bat_disable_qs_int)
   );

   //   F[lid_open]: 10:10
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_lid_open (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[10]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.lid_open.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_lid_open_qs_int)
   );

   //   F[z3_wakeup]: 11:11
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_invert_ctl_z3_wakeup (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_invert_ctl_gated_we),
     .wd     (aon_key_invert_ctl_wdata[11]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_invert_ctl.z3_wakeup.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_invert_ctl_z3_wakeup_qs_int)
   );


   // R[pin_allowed_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_pin_allowed_ctl_gated_we;
   assign aon_pin_allowed_ctl_gated_we = aon_pin_allowed_ctl_we & aon_pin_allowed_ctl_regwen;
   //   F[bat_disable_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_bat_disable_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.bat_disable_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_bat_disable_0_qs_int)
   );

   //   F[ec_rst_l_0]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_pin_allowed_ctl_ec_rst_l_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.ec_rst_l_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_ec_rst_l_0_qs_int)
   );

   //   F[pwrb_out_0]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_pwrb_out_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.pwrb_out_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_pwrb_out_0_qs_int)
   );

   //   F[key0_out_0]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key0_out_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key0_out_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key0_out_0_qs_int)
   );

   //   F[key1_out_0]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key1_out_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key1_out_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key1_out_0_qs_int)
   );

   //   F[key2_out_0]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key2_out_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key2_out_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key2_out_0_qs_int)
   );

   //   F[z3_wakeup_0]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_z3_wakeup_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.z3_wakeup_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_z3_wakeup_0_qs_int)
   );

   //   F[flash_wp_l_0]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_pin_allowed_ctl_flash_wp_l_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[7]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.flash_wp_l_0.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_flash_wp_l_0_qs_int)
   );

   //   F[bat_disable_1]: 8:8
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_bat_disable_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[8]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.bat_disable_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_bat_disable_1_qs_int)
   );

   //   F[ec_rst_l_1]: 9:9
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_ec_rst_l_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[9]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.ec_rst_l_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_ec_rst_l_1_qs_int)
   );

   //   F[pwrb_out_1]: 10:10
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_pwrb_out_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[10]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.pwrb_out_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_pwrb_out_1_qs_int)
   );

   //   F[key0_out_1]: 11:11
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key0_out_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[11]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key0_out_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key0_out_1_qs_int)
   );

   //   F[key1_out_1]: 12:12
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key1_out_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[12]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key1_out_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key1_out_1_qs_int)
   );

   //   F[key2_out_1]: 13:13
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_key2_out_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[13]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.key2_out_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_key2_out_1_qs_int)
   );

   //   F[z3_wakeup_1]: 14:14
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_z3_wakeup_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[14]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.z3_wakeup_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_z3_wakeup_1_qs_int)
   );

   //   F[flash_wp_l_1]: 15:15
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_allowed_ctl_flash_wp_l_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_allowed_ctl_gated_we),
     .wd     (aon_pin_allowed_ctl_wdata[15]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_allowed_ctl.flash_wp_l_1.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_allowed_ctl_flash_wp_l_1_qs_int)
   );


   // R[pin_out_ctl]: V(False)
   //   F[bat_disable]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_bat_disable (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_bat_disable_qs_int)
   );

   //   F[ec_rst_l]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_pin_out_ctl_ec_rst_l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.ec_rst_l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_ec_rst_l_qs_int)
   );

   //   F[pwrb_out]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_pwrb_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.pwrb_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_pwrb_out_qs_int)
   );

   //   F[key0_out]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_key0_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.key0_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_key0_out_qs_int)
   );

   //   F[key1_out]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_key1_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.key1_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_key1_out_qs_int)
   );

   //   F[key2_out]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_key2_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.key2_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_key2_out_qs_int)
   );

   //   F[z3_wakeup]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_ctl_z3_wakeup (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.z3_wakeup.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_z3_wakeup_qs_int)
   );

   //   F[flash_wp_l]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h1)
   ) u_pin_out_ctl_flash_wp_l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_ctl_we),
     .wd     (aon_pin_out_ctl_wdata[7]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_ctl.flash_wp_l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_ctl_flash_wp_l_qs_int)
   );


   // R[pin_out_value]: V(False)
   //   F[bat_disable]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_bat_disable (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_bat_disable_qs_int)
   );

   //   F[ec_rst_l]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_ec_rst_l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.ec_rst_l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_ec_rst_l_qs_int)
   );

   //   F[pwrb_out]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_pwrb_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.pwrb_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_pwrb_out_qs_int)
   );

   //   F[key0_out]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_key0_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.key0_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_key0_out_qs_int)
   );

   //   F[key1_out]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_key1_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.key1_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_key1_out_qs_int)
   );

   //   F[key2_out]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_key2_out (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.key2_out.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_key2_out_qs_int)
   );

   //   F[z3_wakeup]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_z3_wakeup (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.z3_wakeup.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_z3_wakeup_qs_int)
   );

   //   F[flash_wp_l]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_pin_out_value_flash_wp_l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_pin_out_value_we),
     .wd     (aon_pin_out_value_wdata[7]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.pin_out_value.flash_wp_l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_pin_out_value_flash_wp_l_qs_int)
   );


   // R[pin_in_value]: V(False)
   //   F[pwrb_in]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_pwrb_in (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.pwrb_in.de),
     .d      (hw2reg.pin_in_value.pwrb_in.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_pwrb_in_qs)
   );

   //   F[key0_in]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_key0_in (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.key0_in.de),
     .d      (hw2reg.pin_in_value.key0_in.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_key0_in_qs)
   );

   //   F[key1_in]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_key1_in (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.key1_in.de),
     .d      (hw2reg.pin_in_value.key1_in.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_key1_in_qs)
   );

   //   F[key2_in]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_key2_in (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.key2_in.de),
     .d      (hw2reg.pin_in_value.key2_in.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_key2_in_qs)
   );

   //   F[lid_open]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_lid_open (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.lid_open.de),
     .d      (hw2reg.pin_in_value.lid_open.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_lid_open_qs)
   );

   //   F[ac_present]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_ac_present (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.ac_present.de),
     .d      (hw2reg.pin_in_value.ac_present.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_ac_present_qs)
   );

   //   F[ec_rst_l]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_ec_rst_l (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.ec_rst_l.de),
     .d      (hw2reg.pin_in_value.ec_rst_l.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_ec_rst_l_qs)
   );

   //   F[flash_wp_l]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRO),
     .RESVAL  (1'h0)
   ) u_pin_in_value_flash_wp_l (
     .clk_i   (clk_i),
     .rst_ni  (rst_ni),

     // from register interface
     .we     (1'b0),
     .wd     ('0),

     // from internal hardware
     .de     (hw2reg.pin_in_value.flash_wp_l.de),
     .d      (hw2reg.pin_in_value.flash_wp_l.d),

     // to internal hardware
     .qe     (),
     .q      (),
     .ds     (),

     // to register interface (read)
     .qs     (pin_in_value_flash_wp_l_qs)
   );


   // R[key_intr_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_key_intr_ctl_gated_we;
   assign aon_key_intr_ctl_gated_we = aon_key_intr_ctl_we & aon_key_intr_ctl_regwen;
   //   F[pwrb_in_h2l]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_pwrb_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.pwrb_in_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_pwrb_in_h2l_qs_int)
   );

   //   F[key0_in_h2l]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key0_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key0_in_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key0_in_h2l_qs_int)
   );

   //   F[key1_in_h2l]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key1_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key1_in_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key1_in_h2l_qs_int)
   );

   //   F[key2_in_h2l]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key2_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key2_in_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key2_in_h2l_qs_int)
   );

   //   F[ac_present_h2l]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_ac_present_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.ac_present_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_ac_present_h2l_qs_int)
   );

   //   F[ec_rst_l_h2l]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_ec_rst_l_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.ec_rst_l_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_ec_rst_l_h2l_qs_int)
   );

   //   F[flash_wp_l_h2l]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_flash_wp_l_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.flash_wp_l_h2l.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_flash_wp_l_h2l_qs_int)
   );

   //   F[pwrb_in_l2h]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_pwrb_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[7]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.pwrb_in_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_pwrb_in_l2h_qs_int)
   );

   //   F[key0_in_l2h]: 8:8
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key0_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[8]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key0_in_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key0_in_l2h_qs_int)
   );

   //   F[key1_in_l2h]: 9:9
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key1_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[9]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key1_in_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key1_in_l2h_qs_int)
   );

   //   F[key2_in_l2h]: 10:10
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_key2_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[10]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.key2_in_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_key2_in_l2h_qs_int)
   );

   //   F[ac_present_l2h]: 11:11
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_ac_present_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[11]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.ac_present_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_ac_present_l2h_qs_int)
   );

   //   F[ec_rst_l_l2h]: 12:12
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_ec_rst_l_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[12]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.ec_rst_l_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_ec_rst_l_l2h_qs_int)
   );

   //   F[flash_wp_l_l2h]: 13:13
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_key_intr_ctl_flash_wp_l_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_ctl_gated_we),
     .wd     (aon_key_intr_ctl_wdata[13]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_ctl.flash_wp_l_l2h.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_ctl_flash_wp_l_l2h_qs_int)
   );


   // R[key_intr_debounce_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_key_intr_debounce_ctl_gated_we;
   assign aon_key_intr_debounce_ctl_gated_we =
     aon_key_intr_debounce_ctl_we & aon_key_intr_debounce_ctl_regwen;
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h7d0)
   ) u_key_intr_debounce_ctl (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_debounce_ctl_gated_we),
     .wd     (aon_key_intr_debounce_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.key_intr_debounce_ctl.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_key_intr_debounce_ctl_qs_int)
   );


   // R[auto_block_debounce_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_auto_block_debounce_ctl_gated_we;
   assign aon_auto_block_debounce_ctl_gated_we =
     aon_auto_block_debounce_ctl_we & aon_auto_block_debounce_ctl_regwen;
   //   F[debounce_timer]: 15:0
   prim_subreg #(
     .DW      (16),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (16'h7d0)
   ) u_auto_block_debounce_ctl_debounce_timer (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_debounce_ctl_gated_we),
     .wd     (aon_auto_block_debounce_ctl_wdata[15:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_debounce_ctl.debounce_timer.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_debounce_ctl_debounce_timer_qs_int)
   );

   //   F[auto_block_enable]: 16:16
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_debounce_ctl_auto_block_enable (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_debounce_ctl_gated_we),
     .wd     (aon_auto_block_debounce_ctl_wdata[16]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_debounce_ctl.auto_block_enable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_debounce_ctl_auto_block_enable_qs_int)
   );


   // R[auto_block_out_ctl]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_auto_block_out_ctl_gated_we;
   assign aon_auto_block_out_ctl_gated_we =
     aon_auto_block_out_ctl_we & aon_auto_block_out_ctl_regwen;
   //   F[key0_out_sel]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key0_out_sel (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key0_out_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key0_out_sel_qs_int)
   );

   //   F[key1_out_sel]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key1_out_sel (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key1_out_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key1_out_sel_qs_int)
   );

   //   F[key2_out_sel]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key2_out_sel (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key2_out_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key2_out_sel_qs_int)
   );

   //   F[key0_out_value]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key0_out_value (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key0_out_value.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key0_out_value_qs_int)
   );

   //   F[key1_out_value]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key1_out_value (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[5]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key1_out_value.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key1_out_value_qs_int)
   );

   //   F[key2_out_value]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_auto_block_out_ctl_key2_out_value (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_auto_block_out_ctl_gated_we),
     .wd     (aon_auto_block_out_ctl_wdata[6]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.auto_block_out_ctl.key2_out_value.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_auto_block_out_ctl_key2_out_value_qs_int)
   );


   // Subregister 0 of Multireg com_pre_sel_ctl
   // R[com_pre_sel_ctl_0]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_sel_ctl_0_gated_we;
   assign aon_com_pre_sel_ctl_0_gated_we = aon_com_pre_sel_ctl_0_we & aon_com_pre_sel_ctl_0_regwen;
   //   F[key0_in_sel_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_0_key0_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_0_gated_we),
     .wd     (aon_com_pre_sel_ctl_0_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[0].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_0_key0_in_sel_0_qs_int)
   );

   //   F[key1_in_sel_0]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_0_key1_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_0_gated_we),
     .wd     (aon_com_pre_sel_ctl_0_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[0].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_0_key1_in_sel_0_qs_int)
   );

   //   F[key2_in_sel_0]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_0_key2_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_0_gated_we),
     .wd     (aon_com_pre_sel_ctl_0_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[0].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_0_key2_in_sel_0_qs_int)
   );

   //   F[pwrb_in_sel_0]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_0_pwrb_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_0_gated_we),
     .wd     (aon_com_pre_sel_ctl_0_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[0].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_0_pwrb_in_sel_0_qs_int)
   );

   //   F[ac_present_sel_0]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_0_ac_present_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_0_gated_we),
     .wd     (aon_com_pre_sel_ctl_0_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[0].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_0_ac_present_sel_0_qs_int)
   );


   // Subregister 1 of Multireg com_pre_sel_ctl
   // R[com_pre_sel_ctl_1]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_sel_ctl_1_gated_we;
   assign aon_com_pre_sel_ctl_1_gated_we = aon_com_pre_sel_ctl_1_we & aon_com_pre_sel_ctl_1_regwen;
   //   F[key0_in_sel_1]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_1_key0_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_1_gated_we),
     .wd     (aon_com_pre_sel_ctl_1_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[1].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_1_key0_in_sel_1_qs_int)
   );

   //   F[key1_in_sel_1]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_1_key1_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_1_gated_we),
     .wd     (aon_com_pre_sel_ctl_1_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[1].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_1_key1_in_sel_1_qs_int)
   );

   //   F[key2_in_sel_1]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_1_key2_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_1_gated_we),
     .wd     (aon_com_pre_sel_ctl_1_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[1].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_1_key2_in_sel_1_qs_int)
   );

   //   F[pwrb_in_sel_1]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_1_pwrb_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_1_gated_we),
     .wd     (aon_com_pre_sel_ctl_1_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[1].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_1_pwrb_in_sel_1_qs_int)
   );

   //   F[ac_present_sel_1]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_1_ac_present_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_1_gated_we),
     .wd     (aon_com_pre_sel_ctl_1_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[1].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_1_ac_present_sel_1_qs_int)
   );


   // Subregister 2 of Multireg com_pre_sel_ctl
   // R[com_pre_sel_ctl_2]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_sel_ctl_2_gated_we;
   assign aon_com_pre_sel_ctl_2_gated_we = aon_com_pre_sel_ctl_2_we & aon_com_pre_sel_ctl_2_regwen;
   //   F[key0_in_sel_2]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_2_key0_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_2_gated_we),
     .wd     (aon_com_pre_sel_ctl_2_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[2].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_2_key0_in_sel_2_qs_int)
   );

   //   F[key1_in_sel_2]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_2_key1_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_2_gated_we),
     .wd     (aon_com_pre_sel_ctl_2_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[2].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_2_key1_in_sel_2_qs_int)
   );

   //   F[key2_in_sel_2]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_2_key2_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_2_gated_we),
     .wd     (aon_com_pre_sel_ctl_2_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[2].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_2_key2_in_sel_2_qs_int)
   );

   //   F[pwrb_in_sel_2]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_2_pwrb_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_2_gated_we),
     .wd     (aon_com_pre_sel_ctl_2_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[2].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_2_pwrb_in_sel_2_qs_int)
   );

   //   F[ac_present_sel_2]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_2_ac_present_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_2_gated_we),
     .wd     (aon_com_pre_sel_ctl_2_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[2].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_2_ac_present_sel_2_qs_int)
   );


   // Subregister 3 of Multireg com_pre_sel_ctl
   // R[com_pre_sel_ctl_3]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_sel_ctl_3_gated_we;
   assign aon_com_pre_sel_ctl_3_gated_we = aon_com_pre_sel_ctl_3_we & aon_com_pre_sel_ctl_3_regwen;
   //   F[key0_in_sel_3]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_3_key0_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_3_gated_we),
     .wd     (aon_com_pre_sel_ctl_3_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[3].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_3_key0_in_sel_3_qs_int)
   );

   //   F[key1_in_sel_3]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_3_key1_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_3_gated_we),
     .wd     (aon_com_pre_sel_ctl_3_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[3].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_3_key1_in_sel_3_qs_int)
   );

   //   F[key2_in_sel_3]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_3_key2_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_3_gated_we),
     .wd     (aon_com_pre_sel_ctl_3_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[3].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_3_key2_in_sel_3_qs_int)
   );

   //   F[pwrb_in_sel_3]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_3_pwrb_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_3_gated_we),
     .wd     (aon_com_pre_sel_ctl_3_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[3].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_3_pwrb_in_sel_3_qs_int)
   );

   //   F[ac_present_sel_3]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_pre_sel_ctl_3_ac_present_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_sel_ctl_3_gated_we),
     .wd     (aon_com_pre_sel_ctl_3_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_sel_ctl[3].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_sel_ctl_3_ac_present_sel_3_qs_int)
   );


   // Subregister 0 of Multireg com_pre_det_ctl
   // R[com_pre_det_ctl_0]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_det_ctl_0_gated_we;
   assign aon_com_pre_det_ctl_0_gated_we = aon_com_pre_det_ctl_0_we & aon_com_pre_det_ctl_0_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_pre_det_ctl_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_det_ctl_0_gated_we),
     .wd     (aon_com_pre_det_ctl_0_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_det_ctl[0].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_det_ctl_0_qs_int)
   );


   // Subregister 1 of Multireg com_pre_det_ctl
   // R[com_pre_det_ctl_1]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_det_ctl_1_gated_we;
   assign aon_com_pre_det_ctl_1_gated_we = aon_com_pre_det_ctl_1_we & aon_com_pre_det_ctl_1_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_pre_det_ctl_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_det_ctl_1_gated_we),
     .wd     (aon_com_pre_det_ctl_1_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_det_ctl[1].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_det_ctl_1_qs_int)
   );


   // Subregister 2 of Multireg com_pre_det_ctl
   // R[com_pre_det_ctl_2]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_det_ctl_2_gated_we;
   assign aon_com_pre_det_ctl_2_gated_we = aon_com_pre_det_ctl_2_we & aon_com_pre_det_ctl_2_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_pre_det_ctl_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_det_ctl_2_gated_we),
     .wd     (aon_com_pre_det_ctl_2_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_det_ctl[2].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_det_ctl_2_qs_int)
   );


   // Subregister 3 of Multireg com_pre_det_ctl
   // R[com_pre_det_ctl_3]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_pre_det_ctl_3_gated_we;
   assign aon_com_pre_det_ctl_3_gated_we = aon_com_pre_det_ctl_3_we & aon_com_pre_det_ctl_3_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_pre_det_ctl_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_pre_det_ctl_3_gated_we),
     .wd     (aon_com_pre_det_ctl_3_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_pre_det_ctl[3].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_pre_det_ctl_3_qs_int)
   );


   // Subregister 0 of Multireg com_sel_ctl
   // R[com_sel_ctl_0]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_sel_ctl_0_gated_we;
   assign aon_com_sel_ctl_0_gated_we = aon_com_sel_ctl_0_we & aon_com_sel_ctl_0_regwen;
   //   F[key0_in_sel_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_0_key0_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_0_gated_we),
     .wd     (aon_com_sel_ctl_0_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[0].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_0_key0_in_sel_0_qs_int)
   );

   //   F[key1_in_sel_0]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_0_key1_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_0_gated_we),
     .wd     (aon_com_sel_ctl_0_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[0].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_0_key1_in_sel_0_qs_int)
   );

   //   F[key2_in_sel_0]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_0_key2_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_0_gated_we),
     .wd     (aon_com_sel_ctl_0_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[0].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_0_key2_in_sel_0_qs_int)
   );

   //   F[pwrb_in_sel_0]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_0_pwrb_in_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_0_gated_we),
     .wd     (aon_com_sel_ctl_0_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[0].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_0_pwrb_in_sel_0_qs_int)
   );

   //   F[ac_present_sel_0]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_0_ac_present_sel_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_0_gated_we),
     .wd     (aon_com_sel_ctl_0_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[0].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_0_ac_present_sel_0_qs_int)
   );


   // Subregister 1 of Multireg com_sel_ctl
   // R[com_sel_ctl_1]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_sel_ctl_1_gated_we;
   assign aon_com_sel_ctl_1_gated_we = aon_com_sel_ctl_1_we & aon_com_sel_ctl_1_regwen;
   //   F[key0_in_sel_1]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_1_key0_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_1_gated_we),
     .wd     (aon_com_sel_ctl_1_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[1].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_1_key0_in_sel_1_qs_int)
   );

   //   F[key1_in_sel_1]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_1_key1_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_1_gated_we),
     .wd     (aon_com_sel_ctl_1_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[1].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_1_key1_in_sel_1_qs_int)
   );

   //   F[key2_in_sel_1]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_1_key2_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_1_gated_we),
     .wd     (aon_com_sel_ctl_1_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[1].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_1_key2_in_sel_1_qs_int)
   );

   //   F[pwrb_in_sel_1]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_1_pwrb_in_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_1_gated_we),
     .wd     (aon_com_sel_ctl_1_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[1].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_1_pwrb_in_sel_1_qs_int)
   );

   //   F[ac_present_sel_1]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_1_ac_present_sel_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_1_gated_we),
     .wd     (aon_com_sel_ctl_1_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[1].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_1_ac_present_sel_1_qs_int)
   );


   // Subregister 2 of Multireg com_sel_ctl
   // R[com_sel_ctl_2]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_sel_ctl_2_gated_we;
   assign aon_com_sel_ctl_2_gated_we = aon_com_sel_ctl_2_we & aon_com_sel_ctl_2_regwen;
   //   F[key0_in_sel_2]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_2_key0_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_2_gated_we),
     .wd     (aon_com_sel_ctl_2_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[2].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_2_key0_in_sel_2_qs_int)
   );

   //   F[key1_in_sel_2]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_2_key1_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_2_gated_we),
     .wd     (aon_com_sel_ctl_2_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[2].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_2_key1_in_sel_2_qs_int)
   );

   //   F[key2_in_sel_2]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_2_key2_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_2_gated_we),
     .wd     (aon_com_sel_ctl_2_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[2].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_2_key2_in_sel_2_qs_int)
   );

   //   F[pwrb_in_sel_2]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_2_pwrb_in_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_2_gated_we),
     .wd     (aon_com_sel_ctl_2_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[2].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_2_pwrb_in_sel_2_qs_int)
   );

   //   F[ac_present_sel_2]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_2_ac_present_sel_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_2_gated_we),
     .wd     (aon_com_sel_ctl_2_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[2].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_2_ac_present_sel_2_qs_int)
   );


   // Subregister 3 of Multireg com_sel_ctl
   // R[com_sel_ctl_3]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_sel_ctl_3_gated_we;
   assign aon_com_sel_ctl_3_gated_we = aon_com_sel_ctl_3_we & aon_com_sel_ctl_3_regwen;
   //   F[key0_in_sel_3]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_3_key0_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_3_gated_we),
     .wd     (aon_com_sel_ctl_3_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[3].key0_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_3_key0_in_sel_3_qs_int)
   );

   //   F[key1_in_sel_3]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_3_key1_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_3_gated_we),
     .wd     (aon_com_sel_ctl_3_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[3].key1_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_3_key1_in_sel_3_qs_int)
   );

   //   F[key2_in_sel_3]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_3_key2_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_3_gated_we),
     .wd     (aon_com_sel_ctl_3_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[3].key2_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_3_key2_in_sel_3_qs_int)
   );

   //   F[pwrb_in_sel_3]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_3_pwrb_in_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_3_gated_we),
     .wd     (aon_com_sel_ctl_3_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[3].pwrb_in_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_3_pwrb_in_sel_3_qs_int)
   );

   //   F[ac_present_sel_3]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_sel_ctl_3_ac_present_sel_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_sel_ctl_3_gated_we),
     .wd     (aon_com_sel_ctl_3_wdata[4]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_sel_ctl[3].ac_present_sel.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_sel_ctl_3_ac_present_sel_3_qs_int)
   );


   // Subregister 0 of Multireg com_det_ctl
   // R[com_det_ctl_0]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_det_ctl_0_gated_we;
   assign aon_com_det_ctl_0_gated_we = aon_com_det_ctl_0_we & aon_com_det_ctl_0_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_det_ctl_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_det_ctl_0_gated_we),
     .wd     (aon_com_det_ctl_0_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_det_ctl[0].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_det_ctl_0_qs_int)
   );


   // Subregister 1 of Multireg com_det_ctl
   // R[com_det_ctl_1]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_det_ctl_1_gated_we;
   assign aon_com_det_ctl_1_gated_we = aon_com_det_ctl_1_we & aon_com_det_ctl_1_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_det_ctl_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_det_ctl_1_gated_we),
     .wd     (aon_com_det_ctl_1_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_det_ctl[1].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_det_ctl_1_qs_int)
   );


   // Subregister 2 of Multireg com_det_ctl
   // R[com_det_ctl_2]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_det_ctl_2_gated_we;
   assign aon_com_det_ctl_2_gated_we = aon_com_det_ctl_2_we & aon_com_det_ctl_2_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_det_ctl_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_det_ctl_2_gated_we),
     .wd     (aon_com_det_ctl_2_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_det_ctl[2].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_det_ctl_2_qs_int)
   );


   // Subregister 3 of Multireg com_det_ctl
   // R[com_det_ctl_3]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_det_ctl_3_gated_we;
   assign aon_com_det_ctl_3_gated_we = aon_com_det_ctl_3_we & aon_com_det_ctl_3_regwen;
   prim_subreg #(
     .DW      (32),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (32'h0)
   ) u_com_det_ctl_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_det_ctl_3_gated_we),
     .wd     (aon_com_det_ctl_3_wdata[31:0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_det_ctl[3].q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_det_ctl_3_qs_int)
   );


   // Subregister 0 of Multireg com_out_ctl
   // R[com_out_ctl_0]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_out_ctl_0_gated_we;
   assign aon_com_out_ctl_0_gated_we = aon_com_out_ctl_0_we & aon_com_out_ctl_0_regwen;
   //   F[bat_disable_0]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_0_bat_disable_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_0_gated_we),
     .wd     (aon_com_out_ctl_0_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[0].bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_0_bat_disable_0_qs_int)
   );

   //   F[interrupt_0]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_0_interrupt_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_0_gated_we),
     .wd     (aon_com_out_ctl_0_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[0].interrupt.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_0_interrupt_0_qs_int)
   );

   //   F[ec_rst_0]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_0_ec_rst_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_0_gated_we),
     .wd     (aon_com_out_ctl_0_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[0].ec_rst.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_0_ec_rst_0_qs_int)
   );

   //   F[rst_req_0]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_0_rst_req_0 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_0_gated_we),
     .wd     (aon_com_out_ctl_0_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[0].rst_req.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_0_rst_req_0_qs_int)
   );


   // Subregister 1 of Multireg com_out_ctl
   // R[com_out_ctl_1]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_out_ctl_1_gated_we;
   assign aon_com_out_ctl_1_gated_we = aon_com_out_ctl_1_we & aon_com_out_ctl_1_regwen;
   //   F[bat_disable_1]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_1_bat_disable_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_1_gated_we),
     .wd     (aon_com_out_ctl_1_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[1].bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_1_bat_disable_1_qs_int)
   );

   //   F[interrupt_1]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_1_interrupt_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_1_gated_we),
     .wd     (aon_com_out_ctl_1_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[1].interrupt.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_1_interrupt_1_qs_int)
   );

   //   F[ec_rst_1]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_1_ec_rst_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_1_gated_we),
     .wd     (aon_com_out_ctl_1_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[1].ec_rst.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_1_ec_rst_1_qs_int)
   );

   //   F[rst_req_1]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_1_rst_req_1 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_1_gated_we),
     .wd     (aon_com_out_ctl_1_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[1].rst_req.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_1_rst_req_1_qs_int)
   );


   // Subregister 2 of Multireg com_out_ctl
   // R[com_out_ctl_2]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_out_ctl_2_gated_we;
   assign aon_com_out_ctl_2_gated_we = aon_com_out_ctl_2_we & aon_com_out_ctl_2_regwen;
   //   F[bat_disable_2]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_2_bat_disable_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_2_gated_we),
     .wd     (aon_com_out_ctl_2_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[2].bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_2_bat_disable_2_qs_int)
   );

   //   F[interrupt_2]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_2_interrupt_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_2_gated_we),
     .wd     (aon_com_out_ctl_2_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[2].interrupt.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_2_interrupt_2_qs_int)
   );

   //   F[ec_rst_2]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_2_ec_rst_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_2_gated_we),
     .wd     (aon_com_out_ctl_2_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[2].ec_rst.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_2_ec_rst_2_qs_int)
   );

   //   F[rst_req_2]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_2_rst_req_2 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_2_gated_we),
     .wd     (aon_com_out_ctl_2_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[2].rst_req.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_2_rst_req_2_qs_int)
   );


   // Subregister 3 of Multireg com_out_ctl
   // R[com_out_ctl_3]: V(False)
   // Create REGWEN-gated WE signal
   logic aon_com_out_ctl_3_gated_we;
   assign aon_com_out_ctl_3_gated_we = aon_com_out_ctl_3_we & aon_com_out_ctl_3_regwen;
   //   F[bat_disable_3]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_3_bat_disable_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_3_gated_we),
     .wd     (aon_com_out_ctl_3_wdata[0]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[3].bat_disable.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_3_bat_disable_3_qs_int)
   );

   //   F[interrupt_3]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_3_interrupt_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_3_gated_we),
     .wd     (aon_com_out_ctl_3_wdata[1]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[3].interrupt.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_3_interrupt_3_qs_int)
   );

   //   F[ec_rst_3]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_3_ec_rst_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_3_gated_we),
     .wd     (aon_com_out_ctl_3_wdata[2]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[3].ec_rst.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_3_ec_rst_3_qs_int)
   );

   //   F[rst_req_3]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessRW),
     .RESVAL  (1'h0)
   ) u_com_out_ctl_3_rst_req_3 (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_com_out_ctl_3_gated_we),
     .wd     (aon_com_out_ctl_3_wdata[3]),

     // from internal hardware
     .de     (1'b0),
     .d      ('0),

     // to internal hardware
     .qe     (),
     .q      (reg2hw.com_out_ctl[3].rst_req.q),
     .ds     (),

     // to register interface (read)
     .qs     (aon_com_out_ctl_3_rst_req_3_qs_int)
   );


   // R[combo_intr_status]: V(False)
   logic [3:0] combo_intr_status_flds_we;
   assign aon_combo_intr_status_qe = |combo_intr_status_flds_we;
   //   F[combo0_h2l]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_combo_intr_status_combo0_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_combo_intr_status_we),
     .wd     (aon_combo_intr_status_wdata[0]),

     // from internal hardware
     .de     (hw2reg.combo_intr_status.combo0_h2l.de),
     .d      (hw2reg.combo_intr_status.combo0_h2l.d),

     // to internal hardware
     .qe     (combo_intr_status_flds_we[0]),
     .q      (),
     .ds     (aon_combo_intr_status_combo0_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_combo_intr_status_combo0_h2l_qs_int)
   );

   //   F[combo1_h2l]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_combo_intr_status_combo1_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_combo_intr_status_we),
     .wd     (aon_combo_intr_status_wdata[1]),

     // from internal hardware
     .de     (hw2reg.combo_intr_status.combo1_h2l.de),
     .d      (hw2reg.combo_intr_status.combo1_h2l.d),

     // to internal hardware
     .qe     (combo_intr_status_flds_we[1]),
     .q      (),
     .ds     (aon_combo_intr_status_combo1_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_combo_intr_status_combo1_h2l_qs_int)
   );

   //   F[combo2_h2l]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_combo_intr_status_combo2_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_combo_intr_status_we),
     .wd     (aon_combo_intr_status_wdata[2]),

     // from internal hardware
     .de     (hw2reg.combo_intr_status.combo2_h2l.de),
     .d      (hw2reg.combo_intr_status.combo2_h2l.d),

     // to internal hardware
     .qe     (combo_intr_status_flds_we[2]),
     .q      (),
     .ds     (aon_combo_intr_status_combo2_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_combo_intr_status_combo2_h2l_qs_int)
   );

   //   F[combo3_h2l]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_combo_intr_status_combo3_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_combo_intr_status_we),
     .wd     (aon_combo_intr_status_wdata[3]),

     // from internal hardware
     .de     (hw2reg.combo_intr_status.combo3_h2l.de),
     .d      (hw2reg.combo_intr_status.combo3_h2l.d),

     // to internal hardware
     .qe     (combo_intr_status_flds_we[3]),
     .q      (),
     .ds     (aon_combo_intr_status_combo3_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_combo_intr_status_combo3_h2l_qs_int)
   );


   // R[key_intr_status]: V(False)
   logic [13:0] key_intr_status_flds_we;
   assign aon_key_intr_status_qe = |key_intr_status_flds_we;
   //   F[pwrb_h2l]: 0:0
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_pwrb_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[0]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.pwrb_h2l.de),
     .d      (hw2reg.key_intr_status.pwrb_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[0]),
     .q      (),
     .ds     (aon_key_intr_status_pwrb_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_pwrb_h2l_qs_int)
   );

   //   F[key0_in_h2l]: 1:1
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key0_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[1]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key0_in_h2l.de),
     .d      (hw2reg.key_intr_status.key0_in_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[1]),
     .q      (),
     .ds     (aon_key_intr_status_key0_in_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key0_in_h2l_qs_int)
   );

   //   F[key1_in_h2l]: 2:2
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key1_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[2]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key1_in_h2l.de),
     .d      (hw2reg.key_intr_status.key1_in_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[2]),
     .q      (),
     .ds     (aon_key_intr_status_key1_in_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key1_in_h2l_qs_int)
   );

   //   F[key2_in_h2l]: 3:3
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key2_in_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[3]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key2_in_h2l.de),
     .d      (hw2reg.key_intr_status.key2_in_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[3]),
     .q      (),
     .ds     (aon_key_intr_status_key2_in_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key2_in_h2l_qs_int)
   );

   //   F[ac_present_h2l]: 4:4
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_ac_present_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[4]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.ac_present_h2l.de),
     .d      (hw2reg.key_intr_status.ac_present_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[4]),
     .q      (),
     .ds     (aon_key_intr_status_ac_present_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_ac_present_h2l_qs_int)
   );

   //   F[ec_rst_l_h2l]: 5:5
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_ec_rst_l_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[5]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.ec_rst_l_h2l.de),
     .d      (hw2reg.key_intr_status.ec_rst_l_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[5]),
     .q      (),
     .ds     (aon_key_intr_status_ec_rst_l_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_ec_rst_l_h2l_qs_int)
   );

   //   F[flash_wp_l_h2l]: 6:6
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_flash_wp_l_h2l (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[6]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.flash_wp_l_h2l.de),
     .d      (hw2reg.key_intr_status.flash_wp_l_h2l.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[6]),
     .q      (),
     .ds     (aon_key_intr_status_flash_wp_l_h2l_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_flash_wp_l_h2l_qs_int)
   );

   //   F[pwrb_l2h]: 7:7
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_pwrb_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[7]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.pwrb_l2h.de),
     .d      (hw2reg.key_intr_status.pwrb_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[7]),
     .q      (),
     .ds     (aon_key_intr_status_pwrb_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_pwrb_l2h_qs_int)
   );

   //   F[key0_in_l2h]: 8:8
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key0_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[8]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key0_in_l2h.de),
     .d      (hw2reg.key_intr_status.key0_in_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[8]),
     .q      (),
     .ds     (aon_key_intr_status_key0_in_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key0_in_l2h_qs_int)
   );

   //   F[key1_in_l2h]: 9:9
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key1_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[9]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key1_in_l2h.de),
     .d      (hw2reg.key_intr_status.key1_in_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[9]),
     .q      (),
     .ds     (aon_key_intr_status_key1_in_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key1_in_l2h_qs_int)
   );

   //   F[key2_in_l2h]: 10:10
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_key2_in_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[10]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.key2_in_l2h.de),
     .d      (hw2reg.key_intr_status.key2_in_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[10]),
     .q      (),
     .ds     (aon_key_intr_status_key2_in_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_key2_in_l2h_qs_int)
   );

   //   F[ac_present_l2h]: 11:11
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_ac_present_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[11]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.ac_present_l2h.de),
     .d      (hw2reg.key_intr_status.ac_present_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[11]),
     .q      (),
     .ds     (aon_key_intr_status_ac_present_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_ac_present_l2h_qs_int)
   );

   //   F[ec_rst_l_l2h]: 12:12
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_ec_rst_l_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[12]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.ec_rst_l_l2h.de),
     .d      (hw2reg.key_intr_status.ec_rst_l_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[12]),
     .q      (),
     .ds     (aon_key_intr_status_ec_rst_l_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_ec_rst_l_l2h_qs_int)
   );

   //   F[flash_wp_l_l2h]: 13:13
   prim_subreg #(
     .DW      (1),
     .SwAccess(prim_subreg_pkg::SwAccessW1C),
     .RESVAL  (1'h0)
   ) u_key_intr_status_flash_wp_l_l2h (
     .clk_i   (clk_aon_i),
     .rst_ni  (rst_aon_ni),

     // from register interface
     .we     (aon_key_intr_status_we),
     .wd     (aon_key_intr_status_wdata[13]),

     // from internal hardware
     .de     (hw2reg.key_intr_status.flash_wp_l_l2h.de),
     .d      (hw2reg.key_intr_status.flash_wp_l_l2h.d),

     // to internal hardware
     .qe     (key_intr_status_flds_we[13]),
     .q      (),
     .ds     (aon_key_intr_status_flash_wp_l_l2h_ds_int),

     // to register interface (read)
     .qs     (aon_key_intr_status_flash_wp_l_l2h_qs_int)
   );


   logic [42:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[ 0] = (reg_addr == SYSRST_CTRL_INTR_STATE_OFFSET);
     addr_hit[ 1] = (reg_addr == SYSRST_CTRL_INTR_ENABLE_OFFSET);
     addr_hit[ 2] = (reg_addr == SYSRST_CTRL_INTR_TEST_OFFSET);
     addr_hit[ 3] = (reg_addr == SYSRST_CTRL_ALERT_TEST_OFFSET);
     addr_hit[ 4] = (reg_addr == SYSRST_CTRL_REGWEN_OFFSET);
     addr_hit[ 5] = (reg_addr == SYSRST_CTRL_EC_RST_CTL_OFFSET);
     addr_hit[ 6] = (reg_addr == SYSRST_CTRL_ULP_AC_DEBOUNCE_CTL_OFFSET);
     addr_hit[ 7] = (reg_addr == SYSRST_CTRL_ULP_LID_DEBOUNCE_CTL_OFFSET);
     addr_hit[ 8] = (reg_addr == SYSRST_CTRL_ULP_PWRB_DEBOUNCE_CTL_OFFSET);
     addr_hit[ 9] = (reg_addr == SYSRST_CTRL_ULP_CTL_OFFSET);
     addr_hit[10] = (reg_addr == SYSRST_CTRL_ULP_STATUS_OFFSET);
     addr_hit[11] = (reg_addr == SYSRST_CTRL_WKUP_STATUS_OFFSET);
     addr_hit[12] = (reg_addr == SYSRST_CTRL_KEY_INVERT_CTL_OFFSET);
     addr_hit[13] = (reg_addr == SYSRST_CTRL_PIN_ALLOWED_CTL_OFFSET);
     addr_hit[14] = (reg_addr == SYSRST_CTRL_PIN_OUT_CTL_OFFSET);
     addr_hit[15] = (reg_addr == SYSRST_CTRL_PIN_OUT_VALUE_OFFSET);
     addr_hit[16] = (reg_addr == SYSRST_CTRL_PIN_IN_VALUE_OFFSET);
     addr_hit[17] = (reg_addr == SYSRST_CTRL_KEY_INTR_CTL_OFFSET);
     addr_hit[18] = (reg_addr == SYSRST_CTRL_KEY_INTR_DEBOUNCE_CTL_OFFSET);
     addr_hit[19] = (reg_addr == SYSRST_CTRL_AUTO_BLOCK_DEBOUNCE_CTL_OFFSET);
     addr_hit[20] = (reg_addr == SYSRST_CTRL_AUTO_BLOCK_OUT_CTL_OFFSET);
     addr_hit[21] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_0_OFFSET);
     addr_hit[22] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_1_OFFSET);
     addr_hit[23] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_2_OFFSET);
     addr_hit[24] = (reg_addr == SYSRST_CTRL_COM_PRE_SEL_CTL_3_OFFSET);
     addr_hit[25] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_0_OFFSET);
     addr_hit[26] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_1_OFFSET);
     addr_hit[27] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_2_OFFSET);
     addr_hit[28] = (reg_addr == SYSRST_CTRL_COM_PRE_DET_CTL_3_OFFSET);
     addr_hit[29] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_0_OFFSET);
     addr_hit[30] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_1_OFFSET);
     addr_hit[31] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_2_OFFSET);
     addr_hit[32] = (reg_addr == SYSRST_CTRL_COM_SEL_CTL_3_OFFSET);
     addr_hit[33] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_0_OFFSET);
     addr_hit[34] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_1_OFFSET);
     addr_hit[35] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_2_OFFSET);
     addr_hit[36] = (reg_addr == SYSRST_CTRL_COM_DET_CTL_3_OFFSET);
     addr_hit[37] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_0_OFFSET);
     addr_hit[38] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_1_OFFSET);
     addr_hit[39] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_2_OFFSET);
     addr_hit[40] = (reg_addr == SYSRST_CTRL_COM_OUT_CTL_3_OFFSET);
     addr_hit[41] = (reg_addr == SYSRST_CTRL_COMBO_INTR_STATUS_OFFSET);
     addr_hit[42] = (reg_addr == SYSRST_CTRL_KEY_INTR_STATUS_OFFSET);
   end

   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;

   // Check sub-word write is permitted
   always_comb begin
     wr_err = (reg_we &
               ((addr_hit[ 0] & (|(SYSRST_CTRL_PERMIT[ 0] & ~reg_be))) |
                (addr_hit[ 1] & (|(SYSRST_CTRL_PERMIT[ 1] & ~reg_be))) |
                (addr_hit[ 2] & (|(SYSRST_CTRL_PERMIT[ 2] & ~reg_be))) |
                (addr_hit[ 3] & (|(SYSRST_CTRL_PERMIT[ 3] & ~reg_be))) |
                (addr_hit[ 4] & (|(SYSRST_CTRL_PERMIT[ 4] & ~reg_be))) |
                (addr_hit[ 5] & (|(SYSRST_CTRL_PERMIT[ 5] & ~reg_be))) |
                (addr_hit[ 6] & (|(SYSRST_CTRL_PERMIT[ 6] & ~reg_be))) |
                (addr_hit[ 7] & (|(SYSRST_CTRL_PERMIT[ 7] & ~reg_be))) |
                (addr_hit[ 8] & (|(SYSRST_CTRL_PERMIT[ 8] & ~reg_be))) |
                (addr_hit[ 9] & (|(SYSRST_CTRL_PERMIT[ 9] & ~reg_be))) |
                (addr_hit[10] & (|(SYSRST_CTRL_PERMIT[10] & ~reg_be))) |
                (addr_hit[11] & (|(SYSRST_CTRL_PERMIT[11] & ~reg_be))) |
                (addr_hit[12] & (|(SYSRST_CTRL_PERMIT[12] & ~reg_be))) |
                (addr_hit[13] & (|(SYSRST_CTRL_PERMIT[13] & ~reg_be))) |
                (addr_hit[14] & (|(SYSRST_CTRL_PERMIT[14] & ~reg_be))) |
                (addr_hit[15] & (|(SYSRST_CTRL_PERMIT[15] & ~reg_be))) |
                (addr_hit[16] & (|(SYSRST_CTRL_PERMIT[16] & ~reg_be))) |
                (addr_hit[17] & (|(SYSRST_CTRL_PERMIT[17] & ~reg_be))) |
                (addr_hit[18] & (|(SYSRST_CTRL_PERMIT[18] & ~reg_be))) |
                (addr_hit[19] & (|(SYSRST_CTRL_PERMIT[19] & ~reg_be))) |
                (addr_hit[20] & (|(SYSRST_CTRL_PERMIT[20] & ~reg_be))) |
                (addr_hit[21] & (|(SYSRST_CTRL_PERMIT[21] & ~reg_be))) |
                (addr_hit[22] & (|(SYSRST_CTRL_PERMIT[22] & ~reg_be))) |
                (addr_hit[23] & (|(SYSRST_CTRL_PERMIT[23] & ~reg_be))) |
                (addr_hit[24] & (|(SYSRST_CTRL_PERMIT[24] & ~reg_be))) |
                (addr_hit[25] & (|(SYSRST_CTRL_PERMIT[25] & ~reg_be))) |
                (addr_hit[26] & (|(SYSRST_CTRL_PERMIT[26] & ~reg_be))) |
                (addr_hit[27] & (|(SYSRST_CTRL_PERMIT[27] & ~reg_be))) |
                (addr_hit[28] & (|(SYSRST_CTRL_PERMIT[28] & ~reg_be))) |
                (addr_hit[29] & (|(SYSRST_CTRL_PERMIT[29] & ~reg_be))) |
                (addr_hit[30] & (|(SYSRST_CTRL_PERMIT[30] & ~reg_be))) |
                (addr_hit[31] & (|(SYSRST_CTRL_PERMIT[31] & ~reg_be))) |
                (addr_hit[32] & (|(SYSRST_CTRL_PERMIT[32] & ~reg_be))) |
                (addr_hit[33] & (|(SYSRST_CTRL_PERMIT[33] & ~reg_be))) |
                (addr_hit[34] & (|(SYSRST_CTRL_PERMIT[34] & ~reg_be))) |
                (addr_hit[35] & (|(SYSRST_CTRL_PERMIT[35] & ~reg_be))) |
                (addr_hit[36] & (|(SYSRST_CTRL_PERMIT[36] & ~reg_be))) |
                (addr_hit[37] & (|(SYSRST_CTRL_PERMIT[37] & ~reg_be))) |
                (addr_hit[38] & (|(SYSRST_CTRL_PERMIT[38] & ~reg_be))) |
                (addr_hit[39] & (|(SYSRST_CTRL_PERMIT[39] & ~reg_be))) |
                (addr_hit[40] & (|(SYSRST_CTRL_PERMIT[40] & ~reg_be))) |
                (addr_hit[41] & (|(SYSRST_CTRL_PERMIT[41] & ~reg_be))) |
                (addr_hit[42] & (|(SYSRST_CTRL_PERMIT[42] & ~reg_be)))));
   end

   // Generate write-enables
   assign intr_state_we = addr_hit[0] & reg_we & !reg_error;

   assign intr_state_wd = reg_wdata[0];
   assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;

   assign intr_enable_wd = reg_wdata[0];
   assign intr_test_we = addr_hit[2] & reg_we & !reg_error;

   assign intr_test_wd = reg_wdata[0];
   assign alert_test_we = addr_hit[3] & reg_we & !reg_error;

   assign alert_test_wd = reg_wdata[0];
   assign regwen_we = addr_hit[4] & reg_we & !reg_error;

   assign regwen_wd = reg_wdata[0];
   assign ec_rst_ctl_we = addr_hit[5] & reg_we & !reg_error;

   assign ulp_ac_debounce_ctl_we = addr_hit[6] & reg_we & !reg_error;

   assign ulp_lid_debounce_ctl_we = addr_hit[7] & reg_we & !reg_error;

   assign ulp_pwrb_debounce_ctl_we = addr_hit[8] & reg_we & !reg_error;

   assign ulp_ctl_we = addr_hit[9] & reg_we & !reg_error;

   assign ulp_status_we = addr_hit[10] & reg_we & !reg_error;

   assign wkup_status_we = addr_hit[11] & reg_we & !reg_error;

   assign key_invert_ctl_we = addr_hit[12] & reg_we & !reg_error;


   assign pin_allowed_ctl_we = addr_hit[13] & reg_we & !reg_error;


   assign pin_out_ctl_we = addr_hit[14] & reg_we & !reg_error;


   assign pin_out_value_we = addr_hit[15] & reg_we & !reg_error;


   assign key_intr_ctl_we = addr_hit[17] & reg_we & !reg_error;


   assign key_intr_debounce_ctl_we = addr_hit[18] & reg_we & !reg_error;

   assign auto_block_debounce_ctl_we = addr_hit[19] & reg_we & !reg_error;


   assign auto_block_out_ctl_we = addr_hit[20] & reg_we & !reg_error;


   assign com_pre_sel_ctl_0_we = addr_hit[21] & reg_we & !reg_error;


   assign com_pre_sel_ctl_1_we = addr_hit[22] & reg_we & !reg_error;


   assign com_pre_sel_ctl_2_we = addr_hit[23] & reg_we & !reg_error;


   assign com_pre_sel_ctl_3_we = addr_hit[24] & reg_we & !reg_error;


   assign com_pre_det_ctl_0_we = addr_hit[25] & reg_we & !reg_error;

   assign com_pre_det_ctl_1_we = addr_hit[26] & reg_we & !reg_error;

   assign com_pre_det_ctl_2_we = addr_hit[27] & reg_we & !reg_error;

   assign com_pre_det_ctl_3_we = addr_hit[28] & reg_we & !reg_error;

   assign com_sel_ctl_0_we = addr_hit[29] & reg_we & !reg_error;


   assign com_sel_ctl_1_we = addr_hit[30] & reg_we & !reg_error;


   assign com_sel_ctl_2_we = addr_hit[31] & reg_we & !reg_error;


   assign com_sel_ctl_3_we = addr_hit[32] & reg_we & !reg_error;


   assign com_det_ctl_0_we = addr_hit[33] & reg_we & !reg_error;

   assign com_det_ctl_1_we = addr_hit[34] & reg_we & !reg_error;

   assign com_det_ctl_2_we = addr_hit[35] & reg_we & !reg_error;

   assign com_det_ctl_3_we = addr_hit[36] & reg_we & !reg_error;

   assign com_out_ctl_0_we = addr_hit[37] & reg_we & !reg_error;


   assign com_out_ctl_1_we = addr_hit[38] & reg_we & !reg_error;


   assign com_out_ctl_2_we = addr_hit[39] & reg_we & !reg_error;


   assign com_out_ctl_3_we = addr_hit[40] & reg_we & !reg_error;


   assign combo_intr_status_we = addr_hit[41] & reg_we & !reg_error;


   assign key_intr_status_we = addr_hit[42] & reg_we & !reg_error;


   // Assign write-enables to checker logic vector.
   always_comb begin
     reg_we_check = '0;
     reg_we_check[0] = intr_state_we;
     reg_we_check[1] = intr_enable_we;
     reg_we_check[2] = intr_test_we;
     reg_we_check[3] = alert_test_we;
     reg_we_check[4] = regwen_we;
     reg_we_check[5] = ec_rst_ctl_we;
     reg_we_check[6] = ulp_ac_debounce_ctl_we;
     reg_we_check[7] = ulp_lid_debounce_ctl_we;
     reg_we_check[8] = ulp_pwrb_debounce_ctl_we;
     reg_we_check[9] = ulp_ctl_we;
     reg_we_check[10] = ulp_status_we;
     reg_we_check[11] = wkup_status_we;
     reg_we_check[12] = key_invert_ctl_we;
     reg_we_check[13] = pin_allowed_ctl_we;
     reg_we_check[14] = pin_out_ctl_we;
     reg_we_check[15] = pin_out_value_we;
     reg_we_check[16] = 1'b0;
     reg_we_check[17] = key_intr_ctl_we;
     reg_we_check[18] = key_intr_debounce_ctl_we;
     reg_we_check[19] = auto_block_debounce_ctl_we;
     reg_we_check[20] = auto_block_out_ctl_we;
     reg_we_check[21] = com_pre_sel_ctl_0_we;
     reg_we_check[22] = com_pre_sel_ctl_1_we;
     reg_we_check[23] = com_pre_sel_ctl_2_we;
     reg_we_check[24] = com_pre_sel_ctl_3_we;
     reg_we_check[25] = com_pre_det_ctl_0_we;
     reg_we_check[26] = com_pre_det_ctl_1_we;
     reg_we_check[27] = com_pre_det_ctl_2_we;
     reg_we_check[28] = com_pre_det_ctl_3_we;
     reg_we_check[29] = com_sel_ctl_0_we;
     reg_we_check[30] = com_sel_ctl_1_we;
     reg_we_check[31] = com_sel_ctl_2_we;
     reg_we_check[32] = com_sel_ctl_3_we;
     reg_we_check[33] = com_det_ctl_0_we;
     reg_we_check[34] = com_det_ctl_1_we;
     reg_we_check[35] = com_det_ctl_2_we;
     reg_we_check[36] = com_det_ctl_3_we;
     reg_we_check[37] = com_out_ctl_0_we;
     reg_we_check[38] = com_out_ctl_1_we;
     reg_we_check[39] = com_out_ctl_2_we;
     reg_we_check[40] = com_out_ctl_3_we;
     reg_we_check[41] = combo_intr_status_we;
     reg_we_check[42] = key_intr_status_we;
   end

   // Read data return
   always_comb begin
     reg_rdata_next = '0;
     unique case (1'b1)
       addr_hit[0]: begin
         reg_rdata_next[0] = intr_state_qs;
       end

       addr_hit[1]: begin
         reg_rdata_next[0] = intr_enable_qs;
       end

       addr_hit[2]: begin
         reg_rdata_next[0] = '0;
       end

       addr_hit[3]: begin
         reg_rdata_next[0] = '0;
       end

       addr_hit[4]: begin
         reg_rdata_next[0] = regwen_qs;
       end

       addr_hit[5]: begin
         reg_rdata_next = DW'(ec_rst_ctl_qs);
       end
       addr_hit[6]: begin
         reg_rdata_next = DW'(ulp_ac_debounce_ctl_qs);
       end
       addr_hit[7]: begin
         reg_rdata_next = DW'(ulp_lid_debounce_ctl_qs);
       end
       addr_hit[8]: begin
         reg_rdata_next = DW'(ulp_pwrb_debounce_ctl_qs);
       end
       addr_hit[9]: begin
         reg_rdata_next = DW'(ulp_ctl_qs);
       end
       addr_hit[10]: begin
         reg_rdata_next = DW'(ulp_status_qs);
       end
       addr_hit[11]: begin
         reg_rdata_next = DW'(wkup_status_qs);
       end
       addr_hit[12]: begin
         reg_rdata_next = DW'(key_invert_ctl_qs);
       end
       addr_hit[13]: begin
         reg_rdata_next = DW'(pin_allowed_ctl_qs);
       end
       addr_hit[14]: begin
         reg_rdata_next = DW'(pin_out_ctl_qs);
       end
       addr_hit[15]: begin
         reg_rdata_next = DW'(pin_out_value_qs);
       end
       addr_hit[16]: begin
         reg_rdata_next[0] = pin_in_value_pwrb_in_qs;
         reg_rdata_next[1] = pin_in_value_key0_in_qs;
         reg_rdata_next[2] = pin_in_value_key1_in_qs;
         reg_rdata_next[3] = pin_in_value_key2_in_qs;
         reg_rdata_next[4] = pin_in_value_lid_open_qs;
         reg_rdata_next[5] = pin_in_value_ac_present_qs;
         reg_rdata_next[6] = pin_in_value_ec_rst_l_qs;
         reg_rdata_next[7] = pin_in_value_flash_wp_l_qs;
       end

       addr_hit[17]: begin
         reg_rdata_next = DW'(key_intr_ctl_qs);
       end
       addr_hit[18]: begin
         reg_rdata_next = DW'(key_intr_debounce_ctl_qs);
       end
       addr_hit[19]: begin
         reg_rdata_next = DW'(auto_block_debounce_ctl_qs);
       end
       addr_hit[20]: begin
         reg_rdata_next = DW'(auto_block_out_ctl_qs);
       end
       addr_hit[21]: begin
         reg_rdata_next = DW'(com_pre_sel_ctl_0_qs);
       end
       addr_hit[22]: begin
         reg_rdata_next = DW'(com_pre_sel_ctl_1_qs);
       end
       addr_hit[23]: begin
         reg_rdata_next = DW'(com_pre_sel_ctl_2_qs);
       end
       addr_hit[24]: begin
         reg_rdata_next = DW'(com_pre_sel_ctl_3_qs);
       end
       addr_hit[25]: begin
         reg_rdata_next = DW'(com_pre_det_ctl_0_qs);
       end
       addr_hit[26]: begin
         reg_rdata_next = DW'(com_pre_det_ctl_1_qs);
       end
       addr_hit[27]: begin
         reg_rdata_next = DW'(com_pre_det_ctl_2_qs);
       end
       addr_hit[28]: begin
         reg_rdata_next = DW'(com_pre_det_ctl_3_qs);
       end
       addr_hit[29]: begin
         reg_rdata_next = DW'(com_sel_ctl_0_qs);
       end
       addr_hit[30]: begin
         reg_rdata_next = DW'(com_sel_ctl_1_qs);
       end
       addr_hit[31]: begin
         reg_rdata_next = DW'(com_sel_ctl_2_qs);
       end
       addr_hit[32]: begin
         reg_rdata_next = DW'(com_sel_ctl_3_qs);
       end
       addr_hit[33]: begin
         reg_rdata_next = DW'(com_det_ctl_0_qs);
       end
       addr_hit[34]: begin
         reg_rdata_next = DW'(com_det_ctl_1_qs);
       end
       addr_hit[35]: begin
         reg_rdata_next = DW'(com_det_ctl_2_qs);
       end
       addr_hit[36]: begin
         reg_rdata_next = DW'(com_det_ctl_3_qs);
       end
       addr_hit[37]: begin
         reg_rdata_next = DW'(com_out_ctl_0_qs);
       end
       addr_hit[38]: begin
         reg_rdata_next = DW'(com_out_ctl_1_qs);
       end
       addr_hit[39]: begin
         reg_rdata_next = DW'(com_out_ctl_2_qs);
       end
       addr_hit[40]: begin
         reg_rdata_next = DW'(com_out_ctl_3_qs);
       end
       addr_hit[41]: begin
         reg_rdata_next = DW'(combo_intr_status_qs);
       end
       addr_hit[42]: begin
         reg_rdata_next = DW'(key_intr_status_qs);
       end
       default: begin
         reg_rdata_next = '1;
       end
     endcase
   end

   // shadow busy
   logic shadow_busy;
   assign shadow_busy = 1'b0;

   // register busy
   logic reg_busy_sel;
   assign reg_busy = reg_busy_sel | shadow_busy;
   always_comb begin
     reg_busy_sel = '0;
     unique case (1'b1)
       addr_hit[5]: begin
         reg_busy_sel = ec_rst_ctl_busy;
       end
       addr_hit[6]: begin
         reg_busy_sel = ulp_ac_debounce_ctl_busy;
       end
       addr_hit[7]: begin
         reg_busy_sel = ulp_lid_debounce_ctl_busy;
       end
       addr_hit[8]: begin
         reg_busy_sel = ulp_pwrb_debounce_ctl_busy;
       end
       addr_hit[9]: begin
         reg_busy_sel = ulp_ctl_busy;
       end
       addr_hit[10]: begin
         reg_busy_sel = ulp_status_busy;
       end
       addr_hit[11]: begin
         reg_busy_sel = wkup_status_busy;
       end
       addr_hit[12]: begin
         reg_busy_sel = key_invert_ctl_busy;
       end
       addr_hit[13]: begin
         reg_busy_sel = pin_allowed_ctl_busy;
       end
       addr_hit[14]: begin
         reg_busy_sel = pin_out_ctl_busy;
       end
       addr_hit[15]: begin
         reg_busy_sel = pin_out_value_busy;
       end
       addr_hit[17]: begin
         reg_busy_sel = key_intr_ctl_busy;
       end
       addr_hit[18]: begin
         reg_busy_sel = key_intr_debounce_ctl_busy;
       end
       addr_hit[19]: begin
         reg_busy_sel = auto_block_debounce_ctl_busy;
       end
       addr_hit[20]: begin
         reg_busy_sel = auto_block_out_ctl_busy;
       end
       addr_hit[21]: begin
         reg_busy_sel = com_pre_sel_ctl_0_busy;
       end
       addr_hit[22]: begin
         reg_busy_sel = com_pre_sel_ctl_1_busy;
       end
       addr_hit[23]: begin
         reg_busy_sel = com_pre_sel_ctl_2_busy;
       end
       addr_hit[24]: begin
         reg_busy_sel = com_pre_sel_ctl_3_busy;
       end
       addr_hit[25]: begin
         reg_busy_sel = com_pre_det_ctl_0_busy;
       end
       addr_hit[26]: begin
         reg_busy_sel = com_pre_det_ctl_1_busy;
       end
       addr_hit[27]: begin
         reg_busy_sel = com_pre_det_ctl_2_busy;
       end
       addr_hit[28]: begin
         reg_busy_sel = com_pre_det_ctl_3_busy;
       end
       addr_hit[29]: begin
         reg_busy_sel = com_sel_ctl_0_busy;
       end
       addr_hit[30]: begin
         reg_busy_sel = com_sel_ctl_1_busy;
       end
       addr_hit[31]: begin
         reg_busy_sel = com_sel_ctl_2_busy;
       end
       addr_hit[32]: begin
         reg_busy_sel = com_sel_ctl_3_busy;
       end
       addr_hit[33]: begin
         reg_busy_sel = com_det_ctl_0_busy;
       end
       addr_hit[34]: begin
         reg_busy_sel = com_det_ctl_1_busy;
       end
       addr_hit[35]: begin
         reg_busy_sel = com_det_ctl_2_busy;
       end
       addr_hit[36]: begin
         reg_busy_sel = com_det_ctl_3_busy;
       end
       addr_hit[37]: begin
         reg_busy_sel = com_out_ctl_0_busy;
       end
       addr_hit[38]: begin
         reg_busy_sel = com_out_ctl_1_busy;
       end
       addr_hit[39]: begin
         reg_busy_sel = com_out_ctl_2_busy;
       end
       addr_hit[40]: begin
         reg_busy_sel = com_out_ctl_3_busy;
       end
       addr_hit[41]: begin
         reg_busy_sel = combo_intr_status_busy;
       end
       addr_hit[42]: begin
         reg_busy_sel = key_intr_status_busy;
       end
       default: begin
         reg_busy_sel  = '0;
       end
     endcase
   end


   // Unused signal tieoff

   // wdata / byte enable are not always fully used
   // add a blanket unused statement to handle lint waivers
   logic unused_wdata;
   logic unused_be;
   assign unused_wdata = ^reg_wdata;
   assign unused_be = ^reg_be;

   // Assertions for Register Interface
   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)

   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni)

   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)

   // this is formulated as an assumption such that the FPV testbenches do disprove this
   // property by mistake
   //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis)

 endmodule