hw/ip/sysrst_ctrl/dv/sysrst_ctrl_sim_cfg.hjson

// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
  // Name of the sim cfg - typically same as the name of the DUT.
  name: sysrst_ctrl

  // Top level dut name (sv module).
  dut: sysrst_ctrl

  // Top level testbench name (sv module).
  tb: tb

  // Simulator used to sign off this block
  tool: vcs

  // Fusesoc core file used for building the file list.
  fusesoc_core: lowrisc:dv:sysrst_ctrl_sim:0.1

  // Testplan hjson file.
  testplan: "{proj_root}/hw/ip/sysrst_ctrl/data/sysrst_ctrl_testplan.hjson"

  // RAL spec - used to generate the RAL model.
  ral_spec: "{proj_root}/hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson"

  // Import additional common sim cfg files.
  // TODO: remove imported cfgs that do not apply.
  import_cfgs: [// Project wide common sim cfg file
                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
                // Common CIP test lists
                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]

  // Add additional tops for simulation.
  sim_tops: ["sysrst_ctrl_bind", "sysrst_ctrl_cov_bind", "sec_cm_prim_onehot_check_bind"]

  // Default iterations for all tests - each test entry can override this.
  reseed: 50

  // Add exclusion files.
  vcs_cov_excl_files: ["{proj_root}/hw/ip/sysrst_ctrl/dv/cov/sysrst_ctrl_cov_unr_excl.el"]

  // Default UVM test and seq class name.
  uvm_test: sysrst_ctrl_base_test
  uvm_test_seq: sysrst_ctrl_base_vseq

  // List of test specifications.
  tests: [
    {
      name: sysrst_ctrl_smoke
      uvm_test_seq: sysrst_ctrl_smoke_vseq
    }
    {
      name: sysrst_ctrl_in_out_inverted
      uvm_test_seq: sysrst_ctrl_in_out_inverted_vseq
    }
    {
      name: sysrst_ctrl_combo_detect_ec_rst
      uvm_test_seq: sysrst_ctrl_combo_detect_ec_rst_vseq
      // This is a directed test with very few random values.
      reseed: 5
    }
    {
      name: sysrst_ctrl_combo_detect_ec_rst_with_pre_cond
      uvm_test_seq: sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq
      // This is a directed test with very few random values.
      reseed: 5
    }
    {
      name: sysrst_ctrl_pin_access_test
      uvm_test_seq: sysrst_ctrl_pin_access_vseq
    }
    {
      name: sysrst_ctrl_pin_override_test
      uvm_test_seq: sysrst_ctrl_pin_override_vseq
    }
    {
      name: sysrst_ctrl_flash_wr_prot_out
      uvm_test_seq: sysrst_ctrl_flash_wr_prot_vseq
    }
    {
      name: sysrst_ctrl_ec_pwr_on_rst
      uvm_test_seq: sysrst_ctrl_ec_pwr_on_rst_vseq
      run_opts: ["+test_timeout_ns=10_000_000_000"]
    }
    {
      name: sysrst_ctrl_auto_blk_key_output
      uvm_test_seq: sysrst_ctrl_auto_blk_key_output_vseq
    }
    {
      name: sysrst_ctrl_ultra_low_pwr
      uvm_test_seq: sysrst_ctrl_ultra_low_pwr_vseq
      run_opts: ["+test_timeout_ns=10_000_000_000"]
    }
    {
      name: sysrst_ctrl_combo_detect
      uvm_test_seq: sysrst_ctrl_combo_detect_vseq
      run_opts: ["+test_timeout_ns=10_000_000_000"]
    }
    {
      name: sysrst_ctrl_edge_detect
      uvm_test_seq: sysrst_ctrl_edge_detect_vseq
      run_opts: ["+test_timeout_ns=10_000_000_000"]
    }
  ]

  // List of regressions.
  regressions: [
    {
      name: smoke
      tests: ["sysrst_ctrl_smoke"]
    }
  ]
}