)]}'
{
  "commit": "e267404cc35237a7a2a74bee233eb2660dbe2f0e",
  "tree": "9ba0190a8d2ee850aaecf54164f96e1c32fe274a",
  "parents": [
    "a5059f05ac7afade1ddaa88a0045d85811a6c293"
  ],
  "author": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Thu May 20 12:27:48 2021 +0200"
  },
  "committer": {
    "name": "Pirmin Vogel",
    "email": "vogelpi@lowrisc.org",
    "time": "Wed May 26 14:39:14 2021 +0200"
  },
  "message": "[fpga] Correct delays around first SPI Flash frame in cw_spiflash.py\n\nPreviously, the tool would use an extended delay before instead of after\nthe first SPI Flash frame which may corrupt the UART output. An\nextended delay after the first SPI Flash frame is needed because the\nfirst frame triggers a Flash erase procedure.\n\nSigned-off-by: Pirmin Vogel \u003cvogelpi@lowrisc.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "09fbae8a052636fe7bc71a7d52447bcacf79a72d",
      "old_mode": 33188,
      "old_path": "util/fpga/cw_spiflash.py",
      "new_id": "ee35d6d673258626be3f7962acf961958b370b9a",
      "new_mode": 33188,
      "new_path": "util/fpga/cw_spiflash.py"
    }
  ]
}