diff --git a/hw/ip/prim/rtl/prim_clock_meas.sv b/hw/ip/prim/rtl/prim_clock_meas.sv
index 613f173..346a1a8 100644
--- a/hw/ip/prim/rtl/prim_clock_meas.sv
+++ b/hw/ip/prim/rtl/prim_clock_meas.sv
@@ -65,7 +65,7 @@
     end else if (!ref_en && |ref_cnt) begin
       ref_cnt <= '0;
       ref_valid <= '0;
-    end else if (ref_en && (ref_cnt == RefCnt - 1)) begin
+    end else if (ref_en && (int'(ref_cnt) == RefCnt - 1)) begin
       // restart count and measure
       ref_cnt <= '0;
       ref_valid <= 1'b1;
diff --git a/hw/ip/prim/rtl/prim_clock_timeout.sv b/hw/ip/prim/rtl/prim_clock_timeout.sv
index df3b3ac..4b02ee3 100644
--- a/hw/ip/prim/rtl/prim_clock_timeout.sv
+++ b/hw/ip/prim/rtl/prim_clock_timeout.sv
@@ -27,7 +27,7 @@
   logic [CntWidth-1:0] cnt;
   logic ack;
   logic timeout;
-  assign timeout = cnt >= TimeOutCnt;
+  assign timeout = int'(cnt) >= TimeOutCnt;
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       cnt <= '0;