)]}'
{
  "commit": "de5efa04db21f9e1de9b1b8961017c83ee9a5dce",
  "tree": "4f7530cba9347d21999cab96f11fc04091872247",
  "parents": [
    "360e34cc2abcf41545f7d157fc6eea8b7b1d18e0"
  ],
  "author": {
    "name": "Srikrishna Iyer",
    "email": "sriyer@google.com",
    "time": "Fri Nov 20 23:17:11 2020 -0800"
  },
  "committer": {
    "name": "Srikrishna Iyer",
    "email": "46467186+sriyerg@users.noreply.github.com",
    "time": "Fri Nov 27 10:13:01 2020 -0800"
  },
  "message": "[dvsim] Replace `sw_test` with `sw_images`\n\nThis change is part 1/4 commit series that updates the way SW tests are\nbuild for chip level. For the chip level SW tests to pass, all 4 commits\nare needed.\n\nThis change reduces dependency on DVSim to process how SW images for\neach tests are set and built. The goal is to be able to supply an\narbitrary list of images to build, rather than assuming a fixes set (ROM\nand SW test). The need for this change arose from one more addition -\nOTBN that requires an image to be built. The processing is now handled\nby `sim.mk` and testbench code. All SW build steps (specific to DV) are\nintegrated into meson.\n\nSigned-off-by: Srikrishna Iyer \u003csriyer@google.com\u003e\n",
  "tree_diff": [
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}