diff --git a/hw/ip/spi_device/data/spi_device.hjson b/hw/ip/spi_device/data/spi_device.hjson
index 50ee822..5ec75fc 100644
--- a/hw/ip/spi_device/data/spi_device.hjson
+++ b/hw/ip/spi_device/data/spi_device.hjson
@@ -7,10 +7,11 @@
   available_input_list: [
     { name: "sck", desc: "SPI Clock" },
     { name: "csb", desc: "Chip Enable#" },
-    { name: "sdi", desc: "SPI Input" },
   ],
   available_output_list: [
-    { name: "sdo", desc: "SPI Output" },
+  ],
+  available_inout_list: [
+    { name: "sd", width: 4, desc: "SPI In/Out ports" },
   ],
   interrupt_list: [
     { name: "rxf",         desc: "RX SRAM FIFO Full" },
diff --git a/hw/ip/spi_device/dv/tb/tb.sv b/hw/ip/spi_device/dv/tb/tb.sv
index 6e5338d..1503af3 100644
--- a/hw/ip/spi_device/dv/tb/tb.sv
+++ b/hw/ip/spi_device/dv/tb/tb.sv
@@ -20,9 +20,9 @@
 
   wire sck;
   wire csb;
-  wire sdo_o;
-  wire sdo_en;
-  wire sdi_i;
+  wire [3:0] sd_out;
+  wire [3:0] sd_out_en;
+  wire [3:0] sd_in;
 
   wire intr_rxf;
   wire intr_rxlvl;
@@ -48,9 +48,9 @@
 
     .cio_sck_i      (sck       ),
     .cio_csb_i      (csb       ),
-    .cio_sdo_o      (sdo_o    ),
-    .cio_sdo_en_o   (sdo_en   ),
-    .cio_sdi_i      (sdi_i    ),
+    .cio_sd_o       (sd_out    ),
+    .cio_sd_en_o    (sd_out_en ),
+    .cio_sd_i       (sd_in     ),
 
     .intr_rxf_o     (intr_rxf  ),
     .intr_rxlvl_o   (intr_rxlvl),
@@ -63,8 +63,9 @@
 
   assign sck          = spi_if.sck;
   assign csb          = spi_if.csb;
-  assign sdi_i        = spi_if.sdi;
-  assign spi_if.sdo   = sdo_en ? sdo_o : 1'bz;
+  // TODO: quad SPI mode is currently not yet implemented
+  assign sd_in        = {3'b000, spi_if.sdi};
+  assign spi_if.sdo   = sd_out_en[1] ? sd_out[1] : 1'bz;
 
   assign interrupts[RxFifoFull]      = intr_rxf;
   assign interrupts[RxFifoGeLevel]   = intr_rxlvl;
diff --git a/hw/ip/spi_device/rtl/spi_device.sv b/hw/ip/spi_device/rtl/spi_device.sv
index bec6e68..5e8bfc5 100644
--- a/hw/ip/spi_device/rtl/spi_device.sv
+++ b/hw/ip/spi_device/rtl/spi_device.sv
@@ -18,9 +18,9 @@
   // SPI Interface
   input              cio_sck_i,
   input              cio_csb_i,
-  output logic       cio_sdo_o,
-  output logic       cio_sdo_en_o,
-  input              cio_sdi_i,
+  output logic [3:0] cio_sd_o,
+  output logic [3:0] cio_sd_en_o,
+  input        [3:0] cio_sd_i,
 
   // Interrupts
   output logic intr_rxf_o,         // RX FIFO Full
@@ -417,16 +417,13 @@
   ////////////////////////////
   // SPI Serial to Parallel //
   ////////////////////////////
-  // TODO: Make full SPI interface
-  // Currently only one line is connected
-  logic [3:0] s2p_si;
-  assign s2p_si = {3'b 0, cio_sdi_i};
+
   spi_s2p u_s2p (
     .clk_i        (clk_spi_in_buf),
     .rst_ni       (rst_spi_n),
 
     // SPI interface
-    .s_i          (s2p_si),
+    .s_i          (cio_sd_i),
 
     .data_valid_o (s2p_data_valid),
     .data_o       (s2p_data      ),
@@ -437,13 +434,6 @@
     .io_mode_i    (io_mode)
   );
 
-
-  // TODO: make full SPI
-  logic [3:0] p2s_so;
-  logic [3:0] p2s_s_en;
-  assign cio_sdo_o = p2s_so[1];
-  assign cio_sdo_en_o = p2s_s_en[1];
-
   spi_p2s u_p2s (
     .clk_i        (clk_spi_out_buf),
     .rst_ni       (rst_spi_n),
@@ -453,13 +443,12 @@
     .data_sent_o  (p2s_sent),
 
     .csb_i        (cio_csb_i),
-    .s_en_o       (p2s_s_en),
-    .s_o          (p2s_so),
+    .s_en_o       (cio_sd_en_o),
+    .s_o          (cio_sd_o),
 
     .cpha_i       (cpha),
     .order_i      (txorder),
     .io_mode_i    (io_mode)
-
   );
 
   /////////////
@@ -490,7 +479,6 @@
     .tx_wvalid_o (p2s_valid),
     .tx_data_o   (p2s_data),
     .tx_wready_i (p2s_sent)
-
   );
 
   // FIFO: Connecting FwMode to SRAM CTRLs
@@ -706,7 +694,7 @@
 
   // make sure scanmode_i is never X (including during reset)
   `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
-  `ASSERT_KNOWN(CioSdoEnOKnown, cio_sdo_en_o)
+  `ASSERT_KNOWN(CioSdoEnOKnown, cio_sd_en_o)
 
   `ASSERT_KNOWN(IntrRxfOKnown,         intr_rxf_o        )
   `ASSERT_KNOWN(IntrRxlvlOKnown,       intr_rxlvl_o      )
diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv
index f2a8d9b..fdd89dd 100644
--- a/hw/ip/spi_host/rtl/spi_host.sv
+++ b/hw/ip/spi_host/rtl/spi_host.sv
@@ -12,7 +12,7 @@
   input clk_i,
   input rst_ni,
 
-  input scanmode_i,
+  input lc_ctrl_pkg::lc_tx_t scanmode_i,
 
   // Register interface
   input  tlul_pkg::tl_h2d_t tl_i,
@@ -59,7 +59,7 @@
   assign cio_csb_en_o = reg2hw.control.csb.q;
 
   logic unused_sigs;
-  assign unused_sigs = scanmode_i;
+  assign unused_sigs = ^scanmode_i;
 
   // Tie offs
   assign hw2reg.control.dir.d  = 1'b0;
diff --git a/hw/ip/spi_host/spi_host.core b/hw/ip/spi_host/spi_host.core
index 472be46..ad3a539 100644
--- a/hw/ip/spi_host/spi_host.core
+++ b/hw/ip/spi_host/spi_host.core
@@ -10,6 +10,8 @@
     depend:
       - lowrisc:ip:tlul
       - lowrisc:prim:all
+      - lowrisc:ip:lc_ctrl_pkg
+      - lowrisc:prim:lc_sync
     files:
       - rtl/spi_host_reg_pkg.sv
       - rtl/spi_host_reg_top.sv
diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
index 4896249..c3705fc 100644
--- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
+++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
@@ -338,6 +338,30 @@
         sw: 1
       }
       {
+        name: spi_host0
+        gen: true
+        type: top
+        domains:
+        [
+          "0"
+        ]
+        parent: sys_src
+        clk: io_div2
+        sw: 1
+      }
+      {
+        name: spi_host1
+        gen: true
+        type: top
+        domains:
+        [
+          "0"
+        ]
+        parent: sys_src
+        clk: io_div2
+        sw: 1
+      }
+      {
         name: usb
         gen: true
         type: top
@@ -1180,21 +1204,16 @@
           width: 1
           type: input
         }
-        {
-          name: sdi
-          width: 1
-          type: input
-        }
       ]
-      available_output_list:
+      available_output_list: []
+      available_inout_list:
       [
         {
-          name: sdo
-          width: 1
-          type: output
+          name: sd
+          width: 4
+          type: inout
         }
       ]
-      available_inout_list: []
       param_list: []
       interrupt_list:
       [
@@ -1294,6 +1313,140 @@
       ]
     }
     {
+      name: spi_host0
+      type: spi_host
+      clock_srcs:
+      {
+        clk_i: io_div4
+      }
+      clock_group: peri
+      reset_connections:
+      {
+        rst_ni: rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel]
+      }
+      base_addr: 0x40060000
+      clock_connections:
+      {
+        clk_i: clkmgr_aon_clocks.clk_io_div4_peri
+      }
+      domain: "0"
+      size: 0x1000
+      bus_device: tlul
+      bus_host: none
+      available_input_list: []
+      available_output_list:
+      [
+        {
+          name: sck
+          width: 1
+          type: output
+        }
+        {
+          name: csb
+          width: 1
+          type: output
+        }
+      ]
+      available_inout_list:
+      [
+        {
+          name: sd
+          width: 4
+          type: inout
+        }
+      ]
+      param_list: []
+      interrupt_list: []
+      alert_list: []
+      wakeup_list: []
+      reset_request_list: []
+      scan: "true"
+      scan_reset: "false"
+      inter_signal_list:
+      [
+        {
+          struct: tl
+          package: tlul_pkg
+          type: req_rsp
+          act: rsp
+          name: tl
+          inst_name: spi_host0
+          width: 1
+          default: ""
+          end_idx: -1
+          top_signame: spi_host0_tl
+          index: -1
+        }
+      ]
+    }
+    {
+      name: spi_host1
+      type: spi_host
+      clock_srcs:
+      {
+        clk_i: io_div4
+      }
+      clock_group: peri
+      reset_connections:
+      {
+        rst_ni: rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel]
+      }
+      base_addr: 0x40070000
+      clock_connections:
+      {
+        clk_i: clkmgr_aon_clocks.clk_io_div4_peri
+      }
+      domain: "0"
+      size: 0x1000
+      bus_device: tlul
+      bus_host: none
+      available_input_list: []
+      available_output_list:
+      [
+        {
+          name: sck
+          width: 1
+          type: output
+        }
+        {
+          name: csb
+          width: 1
+          type: output
+        }
+      ]
+      available_inout_list:
+      [
+        {
+          name: sd
+          width: 4
+          type: inout
+        }
+      ]
+      param_list: []
+      interrupt_list: []
+      alert_list: []
+      wakeup_list: []
+      reset_request_list: []
+      scan: "true"
+      scan_reset: "false"
+      inter_signal_list:
+      [
+        {
+          struct: tl
+          package: tlul_pkg
+          type: req_rsp
+          act: rsp
+          name: tl
+          inst_name: spi_host1
+          width: 1
+          default: ""
+          end_idx: -1
+          top_signame: spi_host1_tl
+          index: -1
+        }
+      ]
+    }
+    {
       name: i2c0
       type: i2c
       clock_srcs:
@@ -7580,6 +7733,14 @@
       [
         peri.tl_spi_device
       ]
+      spi_host0.tl:
+      [
+        peri.tl_spi_host0
+      ]
+      spi_host1.tl:
+      [
+        peri.tl_spi_host1
+      ]
       rv_timer.tl:
       [
         peri.tl_rv_timer
@@ -8362,6 +8523,8 @@
           pattgen
           gpio
           spi_device
+          spi_host0
+          spi_host1
           rv_timer
           usbdev
           pwrmgr_aon
@@ -8373,9 +8536,9 @@
           lc_ctrl
           sensor_ctrl_aon
           alert_handler
-          nmi_gen
           ast_wrapper
           sram_ctrl_ret_aon
+          nmi_gen
         ]
       }
       nodes:
@@ -8572,6 +8735,42 @@
           pipeline_byp: "true"
         }
         {
+          name: spi_host0
+          type: device
+          clock: clk_peri_i
+          reset: rst_peri_ni
+          pipeline: "false"
+          inst_type: spi_host
+          addr_range:
+          [
+            {
+              base_addr: 0x40060000
+              size_byte: 0x1000
+            }
+          ]
+          xbar: false
+          stub: false
+          pipeline_byp: "true"
+        }
+        {
+          name: spi_host1
+          type: device
+          clock: clk_peri_i
+          reset: rst_peri_ni
+          pipeline: "false"
+          inst_type: spi_host
+          addr_range:
+          [
+            {
+              base_addr: 0x40070000
+              size_byte: 0x1000
+            }
+          ]
+          xbar: false
+          stub: false
+          pipeline_byp: "true"
+        }
+        {
           name: rv_timer
           type: device
           clock: clk_peri_i
@@ -8962,6 +9161,30 @@
         {
           struct: tl
           type: req_rsp
+          name: tl_spi_host0
+          act: req
+          package: tlul_pkg
+          inst_name: peri
+          width: 1
+          default: ""
+          top_signame: spi_host0_tl
+          index: -1
+        }
+        {
+          struct: tl
+          type: req_rsp
+          name: tl_spi_host1
+          act: req
+          package: tlul_pkg
+          inst_name: peri
+          width: 1
+          default: ""
+          top_signame: spi_host1_tl
+          index: -1
+        }
+        {
+          struct: tl
+          type: req_rsp
           name: tl_rv_timer
           act: req
           package: tlul_pkg
@@ -11343,27 +11566,28 @@
         name: spi_device
         pad:
         [
-          ChB[0..3]
+          ChC[0..5]
         ]
       }
       {
-        name: uart0
+        name: spi_host0
         pad:
         [
-          ChA[0..1]
+          ChB[0..5]
         ]
       }
       {
         name: usbdev
         pad:
         [
-          ChC[0..8]
+          ChA[0..8]
         ]
       }
     ]
     mio_modules:
     [
       gpio
+      uart0
       uart1
       uart2
       uart3
@@ -11371,6 +11595,7 @@
       i2c1
       i2c2
       pattgen
+      spi_host1
     ]
     nc_modules:
     [
@@ -11389,7 +11614,7 @@
         pad:
         [
           {
-            name: ChB
+            name: ChC
             index: 0
           }
         ]
@@ -11402,60 +11627,84 @@
         pad:
         [
           {
+            name: ChC
+            index: 1
+          }
+        ]
+      }
+      {
+        name: spi_device_sd
+        width: 4
+        type: inout
+        module_name: spi_device
+        pad:
+        [
+          {
+            name: ChC
+            index: 2
+          }
+          {
+            name: ChC
+            index: 3
+          }
+          {
+            name: ChC
+            index: 4
+          }
+          {
+            name: ChC
+            index: 5
+          }
+        ]
+      }
+      {
+        name: spi_host0_sck
+        width: 1
+        type: output
+        module_name: spi_host0
+        pad:
+        [
+          {
+            name: ChB
+            index: 0
+          }
+        ]
+      }
+      {
+        name: spi_host0_csb
+        width: 1
+        type: output
+        module_name: spi_host0
+        pad:
+        [
+          {
             name: ChB
             index: 1
           }
         ]
       }
       {
-        name: spi_device_sdi
-        width: 1
-        type: input
-        module_name: spi_device
+        name: spi_host0_sd
+        width: 4
+        type: inout
+        module_name: spi_host0
         pad:
         [
           {
             name: ChB
             index: 2
           }
-        ]
-      }
-      {
-        name: spi_device_sdo
-        width: 1
-        type: output
-        module_name: spi_device
-        pad:
-        [
           {
             name: ChB
             index: 3
           }
-        ]
-      }
-      {
-        name: uart0_rx
-        width: 1
-        type: input
-        module_name: uart0
-        pad:
-        [
           {
-            name: ChA
-            index: 0
+            name: ChB
+            index: 4
           }
-        ]
-      }
-      {
-        name: uart0_tx
-        width: 1
-        type: output
-        module_name: uart0
-        pad:
-        [
           {
-            name: ChA
-            index: 1
+            name: ChB
+            index: 5
           }
         ]
       }
@@ -11467,7 +11716,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 0
           }
         ]
@@ -11480,7 +11729,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 1
           }
         ]
@@ -11493,7 +11742,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 2
           }
         ]
@@ -11506,7 +11755,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 3
           }
         ]
@@ -11519,7 +11768,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 4
           }
         ]
@@ -11532,7 +11781,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 5
           }
         ]
@@ -11545,7 +11794,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 6
           }
         ]
@@ -11558,7 +11807,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 7
           }
         ]
@@ -11571,7 +11820,7 @@
         pad:
         [
           {
-            name: ChC
+            name: ChA
             index: 8
           }
         ]
@@ -11580,6 +11829,12 @@
     inputs:
     [
       {
+        name: uart0_rx
+        width: 1
+        type: input
+        module_name: uart0
+      }
+      {
         name: uart1_rx
         width: 1
         type: input
@@ -11601,6 +11856,12 @@
     outputs:
     [
       {
+        name: uart0_tx
+        width: 1
+        type: output
+        module_name: uart0
+      }
+      {
         name: uart1_tx
         width: 1
         type: output
@@ -11642,6 +11903,18 @@
         type: output
         module_name: pattgen
       }
+      {
+        name: spi_host1_sck
+        width: 1
+        type: output
+        module_name: spi_host1
+      }
+      {
+        name: spi_host1_csb
+        width: 1
+        type: output
+        module_name: spi_host1
+      }
     ]
     inouts:
     [
@@ -11687,6 +11960,12 @@
         type: inout
         module_name: i2c2
       }
+      {
+        name: spi_host1_sd
+        width: 4
+        type: inout
+        module_name: spi_host1
+      }
     ]
   }
   padctrl:
@@ -11807,6 +12086,8 @@
     sys_io_div4: rstmgr_aon_resets.rst_sys_io_div4_n
     sys_aon: rstmgr_aon_resets.rst_sys_aon_n
     spi_device: rstmgr_aon_resets.rst_spi_device_n
+    spi_host0: rstmgr_aon_resets.rst_spi_host0_n
+    spi_host1: rstmgr_aon_resets.rst_spi_host1_n
     usb: rstmgr_aon_resets.rst_usb_n
     i2c0: rstmgr_aon_resets.rst_i2c0_n
     i2c1: rstmgr_aon_resets.rst_i2c1_n
@@ -11900,6 +12181,32 @@
         type: req_rsp
         act: rsp
         name: tl
+        inst_name: spi_host0
+        width: 1
+        default: ""
+        end_idx: -1
+        top_signame: spi_host0_tl
+        index: -1
+      }
+      {
+        struct: tl
+        package: tlul_pkg
+        type: req_rsp
+        act: rsp
+        name: tl
+        inst_name: spi_host1
+        width: 1
+        default: ""
+        end_idx: -1
+        top_signame: spi_host1_tl
+        index: -1
+      }
+      {
+        struct: tl
+        package: tlul_pkg
+        type: req_rsp
+        act: rsp
+        name: tl
         inst_name: i2c0
         width: 1
         default: ""
@@ -14749,6 +15056,30 @@
       {
         struct: tl
         type: req_rsp
+        name: tl_spi_host0
+        act: req
+        package: tlul_pkg
+        inst_name: peri
+        width: 1
+        default: ""
+        top_signame: spi_host0_tl
+        index: -1
+      }
+      {
+        struct: tl
+        type: req_rsp
+        name: tl_spi_host1
+        act: req
+        package: tlul_pkg
+        inst_name: peri
+        width: 1
+        default: ""
+        top_signame: spi_host1_tl
+        index: -1
+      }
+      {
+        struct: tl
+        type: req_rsp
         name: tl_rv_timer
         act: req
         package: tlul_pkg
@@ -16636,6 +16967,50 @@
       {
         package: tlul_pkg
         struct: tl_h2d
+        signame: spi_host0_tl_req
+        width: 1
+        type: req_rsp
+        end_idx: -1
+        act: rsp
+        suffix: req
+        default: ""
+      }
+      {
+        package: tlul_pkg
+        struct: tl_d2h
+        signame: spi_host0_tl_rsp
+        width: 1
+        type: req_rsp
+        end_idx: -1
+        act: rsp
+        suffix: rsp
+        default: ""
+      }
+      {
+        package: tlul_pkg
+        struct: tl_h2d
+        signame: spi_host1_tl_req
+        width: 1
+        type: req_rsp
+        end_idx: -1
+        act: rsp
+        suffix: req
+        default: ""
+      }
+      {
+        package: tlul_pkg
+        struct: tl_d2h
+        signame: spi_host1_tl_rsp
+        width: 1
+        type: req_rsp
+        end_idx: -1
+        act: rsp
+        suffix: rsp
+        default: ""
+      }
+      {
+        package: tlul_pkg
+        struct: tl_h2d
         signame: rv_timer_tl_req
         width: 1
         type: req_rsp
diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson
index a5595cf..bc4adb6 100644
--- a/hw/top_earlgrey/data/top_earlgrey.hjson
+++ b/hw/top_earlgrey/data/top_earlgrey.hjson
@@ -155,6 +155,8 @@
       { name: "sys_io_div4", gen: true,  type: "top", domains: ["Aon", "0"], parent: "sys_src", clk: "io_div4" }
       { name: "sys_aon",     gen: true,  type: "top", domains: ["Aon", "0"], parent: "sys_src", clk: "aon"     }
       { name: "spi_device",  gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "io_div2", sw: 1 }
+      { name: "spi_host0",   gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "io_div2", sw: 1 }
+      { name: "spi_host1",   gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "io_div2", sw: 1 }
       { name: "usb",         gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "usb",     sw: 1 }
       { name: "i2c0",        gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "io_div2", sw: 1 },
       { name: "i2c1",        gen: true,  type: "top", domains: [       "0"], parent: "sys_src", clk: "io_div2", sw: 1 },
@@ -278,6 +280,20 @@
       reset_connections: {rst_ni: "spi_device"},
       base_addr: "0x40050000",
     },
+    { name: "spi_host0",
+      type: "spi_host",
+      clock_srcs: {clk_i: "io_div4"},
+      clock_group: "peri",
+      reset_connections: {rst_ni: "spi_host0"},
+      base_addr: "0x40060000",
+    },
+    { name: "spi_host1",
+      type: "spi_host",
+      clock_srcs: {clk_i: "io_div4"},
+      clock_group: "peri",
+      reset_connections: {rst_ni: "spi_host1"},
+      base_addr: "0x40070000",
+    },
     { name: "i2c0",
       type: "i2c",
       clock_srcs: {clk_i: "io_div4"},
@@ -869,11 +885,9 @@
     // Dedicated IO modules. The in/out ports of the modules below are connected
     //  to TOP IO port through PADS directly. It bypasses PINMUX multiplexers
     dio_modules: [
-      { name: "spi_device", pad: ["ChB[0..3]"] },
-      //{ name: "uart.tx", pad: ["ChA[0]"]},
-      { name: "uart0", pad: ["ChA[0..1]"]},
-      // { name: "dio_module.signal_input", pad: ["ChA[31]"] }
-      { name: "usbdev", pad: ["ChC[0..8]"]},
+      { name: "spi_device", pad: ["ChC[0..5]"] },
+      { name: "spi_host0",  pad: ["ChB[0..5]"] },
+      { name: "usbdev",     pad: ["ChA[0..8]"] },
     ],
 
     // Multiplexing IO modules. The in/out ports of the modules below are
@@ -881,8 +895,8 @@
     //  between the modules and the IO PADS.
     //  If `mio_modules` aren't defined, it uses all remaining modules from
     //  module list except defined in `dio_modules`.
-    mio_modules: ["gpio", "uart1", "uart2", "uart3",
-                  "i2c0", "i2c1", "i2c2", "pattgen"]
+    mio_modules: ["gpio", "uart0", "uart1", "uart2", "uart3",
+                  "i2c0", "i2c1", "i2c2", "pattgen", "spi_host1"]
 
     // If any module isn't defined in above two lists, its inputs will be tied
     //  to 0, and the output/OE signals will be floating (or connected to
diff --git a/hw/top_earlgrey/data/top_earlgrey.sv.tpl b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
index 779d5f4..a5f9ebb 100644
--- a/hw/top_earlgrey/data/top_earlgrey.sv.tpl
+++ b/hw/top_earlgrey/data/top_earlgrey.sv.tpl
@@ -733,32 +733,64 @@
 % if num_dio != 0:
   // Dedicated IO connections
   // Input-only DIOs have no d2p signals
-  assign dio_d2p = {
+  assign dio_d2p = {<% vector_idx = num_dio - 1 %>
   % for sig in top["pinmux"]["dio"]:
     % if sig["type"] in ["output", "inout"]:
-    cio_${sig["name"]}_d2p${"" if loop.last else ","} // DIO${num_dio - 1 - loop.index}
+      % if sig["width"] > 1:
+        % for i in range(sig["width"]-1,-1,-1):
+    cio_${sig["name"]}_d2p[${i}]${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
+        % endfor
+      % else:
+    cio_${sig["name"]}_d2p${"" if vector_idx == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
+      % endif
     % else:
-    ${sig["width"]}'b0${"" if loop.last else ","} // DIO${num_dio - 1 - loop.index}: cio_${sig["name"]}
+      % if sig["width"] > 1:
+    ${sig["width"]}'b0${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx} - DIO${vector_idx-sig["width"] + 1}: cio_${sig["name"]}<% vector_idx -= sig["width"] %>
+      % else:
+    ${sig["width"]}'b0${"" if vector_idx == 0 else ","} // DIO${vector_idx}: cio_${sig["name"]}<% vector_idx -= 1 %>
+      % endif
     % endif
   % endfor
   };
 
-  assign dio_d2p_en = {
+  assign dio_d2p_en = {<% vector_idx = num_dio - 1 %>
   % for sig in top["pinmux"]["dio"]:
     % if sig["type"] in ["output", "inout"]:
-    cio_${sig["name"]}_en_d2p${"" if loop.last else ","} // DIO${num_dio - 1 - loop.index}
+      % if sig["width"] > 1:
+        % for i in range(sig["width"]-1,-1,-1):
+    cio_${sig["name"]}_en_d2p[${i}]${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
+        % endfor
+      % else:
+    cio_${sig["name"]}_en_d2p${"" if vector_idx == 0 else ","} // DIO${vector_idx}<% vector_idx -= 1 %>
+      % endif
     % else:
-    ${sig["width"]}'b0${"" if loop.last else ","} // DIO${num_dio - 1 - loop.index}: cio_${sig["name"]}
+      % if sig["width"] > 1:
+    ${sig["width"]}'b0${"" if vector_idx - sig["width"] + 1 == 0 else ","} // DIO${vector_idx} - DIO${vector_idx-sig["width"] + 1}: cio_${sig["name"]}<% vector_idx -= sig["width"] %>
+      % else:
+    ${sig["width"]}'b0${"" if vector_idx == 0 else ","} // DIO${vector_idx}: cio_${sig["name"]}<% vector_idx -= 1 %>
+      % endif
     % endif
   % endfor
   };
 
-  // Output-only DIOs have no p2d signal
+  // Output-only DIOs have no p2d signal<% vector_idx = num_dio - 1 %>
   % for sig in top["pinmux"]["dio"]:
     % if sig["type"] in ["input", "inout"]:
-  assign cio_${sig["name"]}_p2d${" " * (max_diolength - len(sig["name"]))} = dio_p2d[${num_dio - 1 - loop.index}]; // DIO${num_dio - 1 - loop.index}
+      % if sig["width"] > 1:
+        % for i in range(sig["width"]-1,-1,-1):
+  assign cio_${sig["name"]}_p2d[${i}]${" " * (max_diolength - len(str(i)) - 2 - len(sig["name"]))} = dio_p2d[${vector_idx}]; // DIO${vector_idx}<% vector_idx -= 1 %>
+        % endfor
+      % else:
+  assign cio_${sig["name"]}_p2d${" " * (max_diolength - len(sig["name"]))} = dio_p2d[${vector_idx}]; // DIO${vector_idx}<% vector_idx -= 1 %>
+      % endif
     % else:
-  // DIO${num_dio - 1 - loop.index}: cio_${sig["name"]}
+      % if sig["width"] > 1:
+        % for i in range(sig["width"]-1,-1,-1):
+  // DIO${vector_idx}: cio_${sig["name"]}[${i}] // DIO${vector_idx}<% vector_idx -= 1 %>
+        % endfor
+      % else:
+  // DIO${vector_idx}: cio_${sig["name"]} // DIO${vector_idx}<% vector_idx -= 1 %>
+      % endif
     % endif
   % endfor
 % endif
diff --git a/hw/top_earlgrey/data/xbar_peri.hjson b/hw/top_earlgrey/data/xbar_peri.hjson
index ee57b0e..2141bae 100644
--- a/hw/top_earlgrey/data/xbar_peri.hjson
+++ b/hw/top_earlgrey/data/xbar_peri.hjson
@@ -75,6 +75,18 @@
       reset:     "rst_peri_ni",
       pipeline:  "false"
     },
+    { name:      "spi_host0",
+      type:      "device",
+      clock:     "clk_peri_i",
+      reset:     "rst_peri_ni",
+      pipeline:  "false"
+    },
+    { name:      "spi_host1",
+      type:      "device",
+      clock:     "clk_peri_i",
+      reset:     "rst_peri_ni",
+      pipeline:  "false"
+    },
     { name:      "rv_timer",
       type:      "device",
       clock:     "clk_peri_i",
@@ -172,8 +184,9 @@
   ],
   connections: {
     main:  ["uart0", "uart1", "uart2", "uart3", "i2c0", "i2c1", "i2c2", "pattgen",
-            "gpio", "spi_device", "rv_timer", "usbdev", "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon",
-            "pinmux_aon", "ram_ret_aon", "otp_ctrl", "lc_ctrl", "sensor_ctrl_aon",
-            "alert_handler", "nmi_gen", "ast_wrapper", "sram_ctrl_ret_aon"],
+            "gpio", "spi_device", "spi_host0", "spi_host1", "rv_timer", "usbdev",
+            "pwrmgr_aon", "rstmgr_aon", "clkmgr_aon", "pinmux_aon", "ram_ret_aon",
+            "otp_ctrl", "lc_ctrl", "sensor_ctrl_aon", "alert_handler", "ast_wrapper",
+            "sram_ctrl_ret_aon", "nmi_gen"],
   },
 }
diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
index 0b13a83..65fb56f 100644
--- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv
@@ -59,6 +59,8 @@
 tl_if pattgen_tl_if(clk_io_div4, rst_n);
 tl_if gpio_tl_if(clk_io_div4, rst_n);
 tl_if spi_device_tl_if(clk_io_div4, rst_n);
+tl_if spi_host0_tl_if(clk_io_div4, rst_n);
+tl_if spi_host1_tl_if(clk_io_div4, rst_n);
 tl_if rv_timer_tl_if(clk_io_div4, rst_n);
 tl_if usbdev_tl_if(clk_io_div4, rst_n);
 tl_if pwrmgr_aon_tl_if(clk_io_div4, rst_n);
@@ -127,6 +129,8 @@
     `DRIVE_CHIP_TL_DEVICE_IF(pattgen, pattgen, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(gpio, gpio, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(spi_device, spi_device, tl)
+    `DRIVE_CHIP_TL_DEVICE_IF(spi_host0, spi_host0, tl)
+    `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(rv_timer, rv_timer, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl)
     `DRIVE_CHIP_TL_DEVICE_IF(pwrmgr_aon, pwrmgr_aon, tl)
diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
index 1e345d4..e482a1b 100644
--- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv
@@ -85,6 +85,12 @@
     '{"spi_device", '{
         '{32'h40050000, 32'h40051fff}
     }},
+    '{"spi_host0", '{
+        '{32'h40060000, 32'h40060fff}
+    }},
+    '{"spi_host1", '{
+        '{32'h40070000, 32'h40070fff}
+    }},
     '{"rv_timer", '{
         '{32'h40100000, 32'h40100fff}
     }},
@@ -151,6 +157,8 @@
         "pattgen",
         "gpio",
         "spi_device",
+        "spi_host0",
+        "spi_host1",
         "rv_timer",
         "usbdev",
         "pwrmgr_aon",
@@ -162,9 +170,9 @@
         "lc_ctrl",
         "sensor_ctrl_aon",
         "alert_handler",
-        "nmi_gen",
         "ast_wrapper",
         "sram_ctrl_ret_aon",
+        "nmi_gen",
         "flash_ctrl",
         "aes",
         "entropy_src",
@@ -192,6 +200,8 @@
         "pattgen",
         "gpio",
         "spi_device",
+        "spi_host0",
+        "spi_host1",
         "rv_timer",
         "usbdev",
         "pwrmgr_aon",
@@ -203,9 +213,9 @@
         "lc_ctrl",
         "sensor_ctrl_aon",
         "alert_handler",
-        "nmi_gen",
         "ast_wrapper",
         "sram_ctrl_ret_aon",
+        "nmi_gen",
         "flash_ctrl",
         "aes",
         "entropy_src",
diff --git a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
index 180440b..2deb9c6 100644
--- a/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
+++ b/hw/top_earlgrey/ip/pinmux/data/autogen/pinmux.hjson
@@ -118,13 +118,13 @@
     { name: "NMioPeriphIn",
       desc: "Number of muxed peripheral inputs",
       type: "int",
-      default: "41",
+      default: "46",
       local: "true"
     },
     { name: "NMioPeriphOut",
       desc: "Number of muxed peripheral outputs",
       type: "int",
-      default: "45",
+      default: "52",
       local: "true"
     },
     { name: "NMioPads",
@@ -136,7 +136,7 @@
     { name: "NDioPads",
       desc: "Number of dedicated IO pads",
       type: "int",
-      default: "15",
+      default: "21",
       local: "true"
     },
     { name: "NWkupDetect",
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
index 6b2b7f5..6e9e567 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_pkg.sv
@@ -8,10 +8,10 @@
 
   // Param list
   parameter int AttrDw = 10;
-  parameter int NMioPeriphIn = 41;
-  parameter int NMioPeriphOut = 45;
+  parameter int NMioPeriphIn = 46;
+  parameter int NMioPeriphOut = 52;
   parameter int NMioPads = 32;
-  parameter int NDioPads = 15;
+  parameter int NDioPads = 21;
   parameter int NWkupDetect = 8;
   parameter int WkupCntWidth = 8;
   parameter int NUsbDevPads = 9;
@@ -126,16 +126,16 @@
   // Register to internal design logic //
   ///////////////////////////////////////
   typedef struct packed {
-    pinmux_reg2hw_mio_periph_insel_mreg_t [40:0] mio_periph_insel; // [1318:1073]
-    pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [1072:881]
-    pinmux_reg2hw_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [880:529]
-    pinmux_reg2hw_dio_pad_attr_mreg_t [14:0] dio_pad_attr; // [528:364]
-    pinmux_reg2hw_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [363:332]
-    pinmux_reg2hw_mio_pad_sleep_en_mreg_t [31:0] mio_pad_sleep_en; // [331:300]
-    pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [31:0] mio_pad_sleep_mode; // [299:236]
-    pinmux_reg2hw_dio_pad_sleep_status_mreg_t [14:0] dio_pad_sleep_status; // [235:221]
-    pinmux_reg2hw_dio_pad_sleep_en_mreg_t [14:0] dio_pad_sleep_en; // [220:206]
-    pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [14:0] dio_pad_sleep_mode; // [205:176]
+    pinmux_reg2hw_mio_periph_insel_mreg_t [45:0] mio_periph_insel; // [1438:1163]
+    pinmux_reg2hw_mio_outsel_mreg_t [31:0] mio_outsel; // [1162:971]
+    pinmux_reg2hw_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [970:619]
+    pinmux_reg2hw_dio_pad_attr_mreg_t [20:0] dio_pad_attr; // [618:388]
+    pinmux_reg2hw_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [387:356]
+    pinmux_reg2hw_mio_pad_sleep_en_mreg_t [31:0] mio_pad_sleep_en; // [355:324]
+    pinmux_reg2hw_mio_pad_sleep_mode_mreg_t [31:0] mio_pad_sleep_mode; // [323:260]
+    pinmux_reg2hw_dio_pad_sleep_status_mreg_t [20:0] dio_pad_sleep_status; // [259:239]
+    pinmux_reg2hw_dio_pad_sleep_en_mreg_t [20:0] dio_pad_sleep_en; // [238:218]
+    pinmux_reg2hw_dio_pad_sleep_mode_mreg_t [20:0] dio_pad_sleep_mode; // [217:176]
     pinmux_reg2hw_wkup_detector_en_mreg_t [7:0] wkup_detector_en; // [175:168]
     pinmux_reg2hw_wkup_detector_mreg_t [7:0] wkup_detector; // [167:128]
     pinmux_reg2hw_wkup_detector_cnt_th_mreg_t [7:0] wkup_detector_cnt_th; // [127:64]
@@ -147,10 +147,10 @@
   // Internal design logic to register //
   ///////////////////////////////////////
   typedef struct packed {
-    pinmux_hw2reg_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [571:252]
-    pinmux_hw2reg_dio_pad_attr_mreg_t [14:0] dio_pad_attr; // [251:102]
-    pinmux_hw2reg_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [101:38]
-    pinmux_hw2reg_dio_pad_sleep_status_mreg_t [14:0] dio_pad_sleep_status; // [37:8]
+    pinmux_hw2reg_mio_pad_attr_mreg_t [31:0] mio_pad_attr; // [643:324]
+    pinmux_hw2reg_dio_pad_attr_mreg_t [20:0] dio_pad_attr; // [323:114]
+    pinmux_hw2reg_mio_pad_sleep_status_mreg_t [31:0] mio_pad_sleep_status; // [113:50]
+    pinmux_hw2reg_dio_pad_sleep_status_mreg_t [20:0] dio_pad_sleep_status; // [49:8]
     pinmux_hw2reg_wkup_cause_mreg_t [7:0] wkup_cause; // [7:0]
   } pinmux_hw2reg_t;
 
@@ -196,389 +196,429 @@
   parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET = 11'h 98;
   parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET = 11'h 9c;
   parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET = 11'h a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 11'h b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 11'h b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 11'h bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 11'h c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 11'h c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 11'h c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 11'h cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 11'h d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 11'h d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 11'h d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 11'h dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 11'h e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 11'h e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 11'h e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 11'h ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 11'h f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 11'h f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 11'h f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 11'h fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 11'h 100;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 11'h 104;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 11'h 108;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 11'h 10c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 11'h 110;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 11'h 114;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 11'h 118;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 11'h 11c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 11'h 120;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 11'h 124;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 11'h 128;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 11'h 12c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 11'h 130;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 11'h 134;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 11'h 138;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 11'h 13c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 11'h 140;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 11'h 144;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 148;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 14c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 150;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 154;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 158;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 15c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 160;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 164;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 168;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 16c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 170;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 174;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 11'h 178;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 11'h 17c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 11'h 180;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 11'h 184;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 11'h 188;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 11'h 18c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 11'h 190;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 11'h 194;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 11'h 198;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 11'h 19c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 11'h 1a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 11'h 1a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 11'h 1a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 11'h 1ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 11'h 1b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 11'h 1b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 11'h 1b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 11'h 1bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 11'h 1c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 11'h 1c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 1c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 1cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 1d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 1d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 1d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 1dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 1e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 1e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 1e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 1ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 1f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 1f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 11'h 1f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 11'h 1fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 11'h 200;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 11'h 204;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 11'h 208;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 11'h 20c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 11'h 210;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 11'h 214;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 11'h 218;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 11'h 21c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 11'h 220;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 11'h 224;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 11'h 228;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 11'h 22c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 11'h 230;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 11'h 234;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 11'h 238;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 23c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 240;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 244;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 248;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 24c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 250;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 254;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 258;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 25c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 260;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 264;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 268;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 26c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 270;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 274;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 278;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 27c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 280;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 284;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 288;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 28c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 290;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 294;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 298;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 29c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 2a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 2a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 2a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 2ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 2b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 2b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 2b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 2bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 2c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 2c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 2c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 2cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 2d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 2d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 2d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 2dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 2e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 2e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 2e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 2ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 2f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 2f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 2f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 2fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 300;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 304;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 308;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 30c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 310;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 314;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 318;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 31c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 320;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 324;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 328;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 32c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 330;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 334;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 338;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 33c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 340;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 344;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 348;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 34c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 350;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 354;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 358;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 35c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 360;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 364;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 368;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 36c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 370;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 374;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 378;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 37c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 380;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 384;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 388;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 38c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 390;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 394;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 398;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 39c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 3a0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 3a4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 3a8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 3ac;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 3b0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 3b4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 3b8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 3bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 3c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 3c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 3c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 3cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 3d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 3d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 3d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 3dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 3e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 3e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 3e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 3ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 3f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 3f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 3f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 3fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 400;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 404;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 408;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 40c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 410;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 414;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 418;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 41c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 420;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 424;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 428;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 42c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 430;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 434;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 438;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 43c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 440;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 444;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 448;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 44c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 450;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 454;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 458;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 45c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 460;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 464;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 468;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 46c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 470;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 474;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 478;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 47c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 480;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 484;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 488;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 48c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 490;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 494;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 498;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 49c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 4a0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 4a4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 4a8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 4ac;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 4b0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 4b4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 4b8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 4bc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 4c0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 4c4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 4c8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 4cc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 4d0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 4d4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 4d8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 4dc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 4e0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 4e4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 4e8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 4ec;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 4f0;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 4f4;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 4f8;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 4fc;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 500;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 504;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 508;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 50c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 510;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 514;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 518;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 51c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 520;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 524;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 528;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 52c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 530;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 534;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 538;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 53c;
-  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 540;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 544;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 548;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 54c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 550;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 554;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 558;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 55c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 560;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 564;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 568;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 56c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 570;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 574;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 578;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 57c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 580;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 584;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 588;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 58c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 590;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 594;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 598;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 59c;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 5a0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 5a4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 5a8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 5ac;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 5b0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 5b4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 5b8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 5bc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 5c0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 5c4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 5c8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 5cc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 5d0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 5d4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 5d8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 5dc;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 5e0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 5e4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 5e8;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 5ec;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 5f0;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 5f4;
-  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 5f8;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 5fc;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 600;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 604;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 608;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 60c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 610;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 614;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 618;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 61c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 620;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 624;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 628;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 62c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 630;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 634;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 638;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 63c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 640;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 644;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 648;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 64c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 650;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 654;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 658;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 65c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 660;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 664;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 668;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 66c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 670;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 674;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 678;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 67c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 680;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 684;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 688;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 68c;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 690;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 694;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 698;
-  parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 69c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET = 11'h a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET = 11'h a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET = 11'h ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET = 11'h b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET = 11'h b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 11'h b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 11'h bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 11'h c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 11'h c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 11'h c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 11'h cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 11'h d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 11'h d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 11'h d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 11'h dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 11'h e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 11'h e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 11'h e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 11'h ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 11'h f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 11'h f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 11'h f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 11'h fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 11'h 100;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 11'h 104;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 11'h 108;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 11'h 10c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 11'h 110;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 11'h 114;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 11'h 118;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 11'h 11c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 11'h 120;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 11'h 124;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 11'h 128;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 11'h 12c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 11'h 130;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 11'h 134;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 11'h 138;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 11'h 13c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 11'h 140;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 11'h 144;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 11'h 148;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 11'h 14c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_38_OFFSET = 11'h 150;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_39_OFFSET = 11'h 154;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_40_OFFSET = 11'h 158;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_41_OFFSET = 11'h 15c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_42_OFFSET = 11'h 160;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_43_OFFSET = 11'h 164;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_44_OFFSET = 11'h 168;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_45_OFFSET = 11'h 16c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 11'h 170;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 11'h 174;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 11'h 178;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 11'h 17c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 11'h 180;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 11'h 184;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 11'h 188;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 11'h 18c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 11'h 190;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 11'h 194;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 11'h 198;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 11'h 19c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 11'h 1a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 11'h 1a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 11'h 1a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 11'h 1ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 11'h 1b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 11'h 1b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 11'h 1b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 11'h 1bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 11'h 1c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 11'h 1c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 11'h 1c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 11'h 1cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 11'h 1d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 11'h 1d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 11'h 1d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 11'h 1dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 11'h 1e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 11'h 1e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 11'h 1e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 11'h 1ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 11'h 1f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 11'h 1f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 11'h 1f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 11'h 1fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 11'h 200;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 11'h 204;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 11'h 208;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 11'h 20c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 11'h 210;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 11'h 214;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 11'h 218;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 11'h 21c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 11'h 220;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 11'h 224;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 11'h 228;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 11'h 22c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 11'h 230;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 11'h 234;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 11'h 238;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 11'h 23c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 11'h 240;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 11'h 244;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 11'h 248;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 11'h 24c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 11'h 250;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 11'h 254;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 11'h 258;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 11'h 25c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 11'h 260;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 11'h 264;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 11'h 268;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 11'h 26c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 270;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 274;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 278;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 27c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 280;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 284;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 288;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 28c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 290;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 294;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 298;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 29c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 2a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 2a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 2a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 2ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 2b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 2b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 2b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 2bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 2c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 11'h 2c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 11'h 2c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 11'h 2cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 11'h 2d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 11'h 2d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 11'h 2d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 11'h 2dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 11'h 2e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 11'h 2e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 11'h 2e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 11'h 2ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 11'h 2f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 11'h 2f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 11'h 2f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 11'h 2fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 11'h 300;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 11'h 304;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 11'h 308;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 11'h 30c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 11'h 310;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 11'h 314;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 11'h 318;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 11'h 31c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 11'h 320;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 11'h 324;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 11'h 328;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 11'h 32c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 11'h 330;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 11'h 334;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 11'h 338;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 11'h 33c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 11'h 340;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 11'h 344;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 11'h 348;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 11'h 34c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 11'h 350;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 11'h 354;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 11'h 358;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 11'h 35c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 11'h 360;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 11'h 364;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 11'h 368;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 11'h 36c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 11'h 370;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 11'h 374;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 11'h 378;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 11'h 37c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 11'h 380;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 11'h 384;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 11'h 388;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 11'h 38c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 11'h 390;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 11'h 394;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 11'h 398;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 11'h 39c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 11'h 3a0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 11'h 3a4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET = 11'h 3a8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET = 11'h 3ac;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET = 11'h 3b0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET = 11'h 3b4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET = 11'h 3b8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET = 11'h 3bc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET = 11'h 3c0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 11'h 3c4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 11'h 3c8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 11'h 3cc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 11'h 3d0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 11'h 3d4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 11'h 3d8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 11'h 3dc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 11'h 3e0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 11'h 3e4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 11'h 3e8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 11'h 3ec;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 11'h 3f0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 11'h 3f4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 11'h 3f8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_14_OFFSET = 11'h 3fc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_15_OFFSET = 11'h 400;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_16_OFFSET = 11'h 404;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_17_OFFSET = 11'h 408;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_18_OFFSET = 11'h 40c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_19_OFFSET = 11'h 410;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_20_OFFSET = 11'h 414;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET = 11'h 418;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 41c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 420;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 424;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 428;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 42c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 430;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 434;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 438;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 43c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 440;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 444;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 448;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 44c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 450;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 454;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 458;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 45c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 460;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 464;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 468;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 46c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 11'h 470;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 11'h 474;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 11'h 478;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 11'h 47c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 11'h 480;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 11'h 484;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 11'h 488;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 11'h 48c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 11'h 490;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 11'h 494;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 11'h 498;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 11'h 49c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 11'h 4a0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 11'h 4a4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 11'h 4a8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 11'h 4ac;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 11'h 4b0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 11'h 4b4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 11'h 4b8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 11'h 4bc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 11'h 4c0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 11'h 4c4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 11'h 4c8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 11'h 4cc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 11'h 4d0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 11'h 4d4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 11'h 4d8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 11'h 4dc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 11'h 4e0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 11'h 4e4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 11'h 4e8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 11'h 4ec;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 11'h 4f0;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 11'h 4f4;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 11'h 4f8;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 11'h 4fc;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 11'h 500;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 11'h 504;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 11'h 508;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 11'h 50c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 11'h 510;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 11'h 514;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 11'h 518;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 51c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 520;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 524;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 528;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 52c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 530;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 534;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 538;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 53c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 540;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 544;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 548;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 54c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 550;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 554;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 558;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 55c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 560;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 564;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 568;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 56c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 11'h 570;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 11'h 574;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 11'h 578;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 11'h 57c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 11'h 580;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 11'h 584;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 11'h 588;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 11'h 58c;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 11'h 590;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 11'h 594;
+  parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 11'h 598;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 11'h 59c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 11'h 5a0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 11'h 5a4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 11'h 5a8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 11'h 5ac;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 11'h 5b0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 11'h 5b4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 11'h 5b8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 11'h 5bc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 11'h 5c0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 11'h 5c4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 11'h 5c8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 11'h 5cc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 11'h 5d0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 11'h 5d4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET = 11'h 5d8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET = 11'h 5dc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET = 11'h 5e0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET = 11'h 5e4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET = 11'h 5e8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET = 11'h 5ec;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET = 11'h 5f0;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 11'h 5f4;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 11'h 5f8;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 11'h 5fc;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 11'h 600;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 11'h 604;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 11'h 608;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 11'h 60c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 11'h 610;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 11'h 614;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 11'h 618;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 11'h 61c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 11'h 620;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 11'h 624;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 11'h 628;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET = 11'h 62c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET = 11'h 630;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET = 11'h 634;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET = 11'h 638;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET = 11'h 63c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET = 11'h 640;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET = 11'h 644;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 11'h 648;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 11'h 64c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 11'h 650;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 11'h 654;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 11'h 658;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 11'h 65c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 11'h 660;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 11'h 664;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 11'h 668;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 11'h 66c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 11'h 670;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 11'h 674;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 11'h 678;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 11'h 67c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET = 11'h 680;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET = 11'h 684;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET = 11'h 688;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET = 11'h 68c;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET = 11'h 690;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET = 11'h 694;
+  parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET = 11'h 698;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 11'h 69c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 11'h 6a0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 11'h 6a4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 11'h 6a8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 11'h 6ac;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 11'h 6b0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 11'h 6b4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 11'h 6b8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 11'h 6bc;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 11'h 6c0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 11'h 6c4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 11'h 6c8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 11'h 6cc;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 11'h 6d0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 11'h 6d4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 11'h 6d8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 11'h 6dc;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 11'h 6e0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 11'h 6e4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 11'h 6e8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 11'h 6ec;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 11'h 6f0;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 11'h 6f4;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 11'h 6f8;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 11'h 6fc;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 11'h 700;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 11'h 704;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 11'h 708;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 11'h 70c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 11'h 710;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 11'h 714;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 11'h 718;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 11'h 71c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 11'h 720;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 11'h 724;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 11'h 728;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 11'h 72c;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 11'h 730;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 11'h 734;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 11'h 738;
+  parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 11'h 73c;
 
   // Reset values for hwext registers and their fields
   parameter logic [9:0] PINMUX_MIO_PAD_ATTR_0_RESVAL = 10'h 0;
@@ -675,6 +715,18 @@
   parameter logic [9:0] PINMUX_DIO_PAD_ATTR_13_ATTR_13_RESVAL = 10'h 0;
   parameter logic [9:0] PINMUX_DIO_PAD_ATTR_14_RESVAL = 10'h 0;
   parameter logic [9:0] PINMUX_DIO_PAD_ATTR_14_ATTR_14_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_15_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_15_ATTR_15_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_16_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_16_ATTR_16_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_17_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_17_ATTR_17_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_18_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_18_ATTR_18_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_19_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_19_ATTR_19_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_20_RESVAL = 10'h 0;
+  parameter logic [9:0] PINMUX_DIO_PAD_ATTR_20_ATTR_20_RESVAL = 10'h 0;
   parameter logic [7:0] PINMUX_WKUP_CAUSE_RESVAL = 8'h 0;
   parameter logic [0:0] PINMUX_WKUP_CAUSE_CAUSE_0_RESVAL = 1'h 0;
   parameter logic [0:0] PINMUX_WKUP_CAUSE_CAUSE_1_RESVAL = 1'h 0;
@@ -728,6 +780,11 @@
     PINMUX_MIO_PERIPH_INSEL_REGWEN_38,
     PINMUX_MIO_PERIPH_INSEL_REGWEN_39,
     PINMUX_MIO_PERIPH_INSEL_REGWEN_40,
+    PINMUX_MIO_PERIPH_INSEL_REGWEN_41,
+    PINMUX_MIO_PERIPH_INSEL_REGWEN_42,
+    PINMUX_MIO_PERIPH_INSEL_REGWEN_43,
+    PINMUX_MIO_PERIPH_INSEL_REGWEN_44,
+    PINMUX_MIO_PERIPH_INSEL_REGWEN_45,
     PINMUX_MIO_PERIPH_INSEL_0,
     PINMUX_MIO_PERIPH_INSEL_1,
     PINMUX_MIO_PERIPH_INSEL_2,
@@ -769,6 +826,11 @@
     PINMUX_MIO_PERIPH_INSEL_38,
     PINMUX_MIO_PERIPH_INSEL_39,
     PINMUX_MIO_PERIPH_INSEL_40,
+    PINMUX_MIO_PERIPH_INSEL_41,
+    PINMUX_MIO_PERIPH_INSEL_42,
+    PINMUX_MIO_PERIPH_INSEL_43,
+    PINMUX_MIO_PERIPH_INSEL_44,
+    PINMUX_MIO_PERIPH_INSEL_45,
     PINMUX_MIO_OUTSEL_REGWEN_0,
     PINMUX_MIO_OUTSEL_REGWEN_1,
     PINMUX_MIO_OUTSEL_REGWEN_2,
@@ -912,6 +974,12 @@
     PINMUX_DIO_PAD_ATTR_REGWEN_12,
     PINMUX_DIO_PAD_ATTR_REGWEN_13,
     PINMUX_DIO_PAD_ATTR_REGWEN_14,
+    PINMUX_DIO_PAD_ATTR_REGWEN_15,
+    PINMUX_DIO_PAD_ATTR_REGWEN_16,
+    PINMUX_DIO_PAD_ATTR_REGWEN_17,
+    PINMUX_DIO_PAD_ATTR_REGWEN_18,
+    PINMUX_DIO_PAD_ATTR_REGWEN_19,
+    PINMUX_DIO_PAD_ATTR_REGWEN_20,
     PINMUX_DIO_PAD_ATTR_0,
     PINMUX_DIO_PAD_ATTR_1,
     PINMUX_DIO_PAD_ATTR_2,
@@ -927,6 +995,12 @@
     PINMUX_DIO_PAD_ATTR_12,
     PINMUX_DIO_PAD_ATTR_13,
     PINMUX_DIO_PAD_ATTR_14,
+    PINMUX_DIO_PAD_ATTR_15,
+    PINMUX_DIO_PAD_ATTR_16,
+    PINMUX_DIO_PAD_ATTR_17,
+    PINMUX_DIO_PAD_ATTR_18,
+    PINMUX_DIO_PAD_ATTR_19,
+    PINMUX_DIO_PAD_ATTR_20,
     PINMUX_MIO_PAD_SLEEP_STATUS,
     PINMUX_MIO_PAD_SLEEP_REGWEN_0,
     PINMUX_MIO_PAD_SLEEP_REGWEN_1,
@@ -1040,6 +1114,12 @@
     PINMUX_DIO_PAD_SLEEP_REGWEN_12,
     PINMUX_DIO_PAD_SLEEP_REGWEN_13,
     PINMUX_DIO_PAD_SLEEP_REGWEN_14,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_15,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_16,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_17,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_18,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_19,
+    PINMUX_DIO_PAD_SLEEP_REGWEN_20,
     PINMUX_DIO_PAD_SLEEP_EN_0,
     PINMUX_DIO_PAD_SLEEP_EN_1,
     PINMUX_DIO_PAD_SLEEP_EN_2,
@@ -1055,6 +1135,12 @@
     PINMUX_DIO_PAD_SLEEP_EN_12,
     PINMUX_DIO_PAD_SLEEP_EN_13,
     PINMUX_DIO_PAD_SLEEP_EN_14,
+    PINMUX_DIO_PAD_SLEEP_EN_15,
+    PINMUX_DIO_PAD_SLEEP_EN_16,
+    PINMUX_DIO_PAD_SLEEP_EN_17,
+    PINMUX_DIO_PAD_SLEEP_EN_18,
+    PINMUX_DIO_PAD_SLEEP_EN_19,
+    PINMUX_DIO_PAD_SLEEP_EN_20,
     PINMUX_DIO_PAD_SLEEP_MODE_0,
     PINMUX_DIO_PAD_SLEEP_MODE_1,
     PINMUX_DIO_PAD_SLEEP_MODE_2,
@@ -1070,6 +1156,12 @@
     PINMUX_DIO_PAD_SLEEP_MODE_12,
     PINMUX_DIO_PAD_SLEEP_MODE_13,
     PINMUX_DIO_PAD_SLEEP_MODE_14,
+    PINMUX_DIO_PAD_SLEEP_MODE_15,
+    PINMUX_DIO_PAD_SLEEP_MODE_16,
+    PINMUX_DIO_PAD_SLEEP_MODE_17,
+    PINMUX_DIO_PAD_SLEEP_MODE_18,
+    PINMUX_DIO_PAD_SLEEP_MODE_19,
+    PINMUX_DIO_PAD_SLEEP_MODE_20,
     PINMUX_WKUP_DETECTOR_REGWEN_0,
     PINMUX_WKUP_DETECTOR_REGWEN_1,
     PINMUX_WKUP_DETECTOR_REGWEN_2,
@@ -1114,7 +1206,7 @@
   } pinmux_id_e;
 
   // Register width information to check illegal writes
-  parameter logic [3:0] PINMUX_PERMIT [424] = '{
+  parameter logic [3:0] PINMUX_PERMIT [464] = '{
     4'b 0001, // index[  0] PINMUX_MIO_PERIPH_INSEL_REGWEN_0
     4'b 0001, // index[  1] PINMUX_MIO_PERIPH_INSEL_REGWEN_1
     4'b 0001, // index[  2] PINMUX_MIO_PERIPH_INSEL_REGWEN_2
@@ -1156,389 +1248,429 @@
     4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_REGWEN_38
     4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_REGWEN_39
     4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_REGWEN_40
-    4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_0
-    4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_1
-    4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_2
-    4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_3
-    4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_4
-    4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_5
-    4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_6
-    4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_7
-    4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_8
-    4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_9
-    4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_10
-    4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_11
-    4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_12
-    4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_13
-    4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_14
-    4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_15
-    4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_16
-    4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_17
-    4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_18
-    4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_19
-    4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_20
-    4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_21
-    4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_22
-    4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_23
-    4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_24
-    4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_25
-    4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_26
-    4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_27
-    4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_28
-    4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_29
-    4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_30
-    4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_31
-    4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_32
-    4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_33
-    4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_34
-    4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_35
-    4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_36
-    4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_37
-    4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_38
-    4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_39
-    4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_40
-    4'b 0001, // index[ 82] PINMUX_MIO_OUTSEL_REGWEN_0
-    4'b 0001, // index[ 83] PINMUX_MIO_OUTSEL_REGWEN_1
-    4'b 0001, // index[ 84] PINMUX_MIO_OUTSEL_REGWEN_2
-    4'b 0001, // index[ 85] PINMUX_MIO_OUTSEL_REGWEN_3
-    4'b 0001, // index[ 86] PINMUX_MIO_OUTSEL_REGWEN_4
-    4'b 0001, // index[ 87] PINMUX_MIO_OUTSEL_REGWEN_5
-    4'b 0001, // index[ 88] PINMUX_MIO_OUTSEL_REGWEN_6
-    4'b 0001, // index[ 89] PINMUX_MIO_OUTSEL_REGWEN_7
-    4'b 0001, // index[ 90] PINMUX_MIO_OUTSEL_REGWEN_8
-    4'b 0001, // index[ 91] PINMUX_MIO_OUTSEL_REGWEN_9
-    4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_10
-    4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_11
-    4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_12
-    4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_13
-    4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_14
-    4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_15
-    4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_REGWEN_16
-    4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_REGWEN_17
-    4'b 0001, // index[100] PINMUX_MIO_OUTSEL_REGWEN_18
-    4'b 0001, // index[101] PINMUX_MIO_OUTSEL_REGWEN_19
-    4'b 0001, // index[102] PINMUX_MIO_OUTSEL_REGWEN_20
-    4'b 0001, // index[103] PINMUX_MIO_OUTSEL_REGWEN_21
-    4'b 0001, // index[104] PINMUX_MIO_OUTSEL_REGWEN_22
-    4'b 0001, // index[105] PINMUX_MIO_OUTSEL_REGWEN_23
-    4'b 0001, // index[106] PINMUX_MIO_OUTSEL_REGWEN_24
-    4'b 0001, // index[107] PINMUX_MIO_OUTSEL_REGWEN_25
-    4'b 0001, // index[108] PINMUX_MIO_OUTSEL_REGWEN_26
-    4'b 0001, // index[109] PINMUX_MIO_OUTSEL_REGWEN_27
-    4'b 0001, // index[110] PINMUX_MIO_OUTSEL_REGWEN_28
-    4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_29
-    4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_30
-    4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_31
-    4'b 0001, // index[114] PINMUX_MIO_OUTSEL_0
-    4'b 0001, // index[115] PINMUX_MIO_OUTSEL_1
-    4'b 0001, // index[116] PINMUX_MIO_OUTSEL_2
-    4'b 0001, // index[117] PINMUX_MIO_OUTSEL_3
-    4'b 0001, // index[118] PINMUX_MIO_OUTSEL_4
-    4'b 0001, // index[119] PINMUX_MIO_OUTSEL_5
-    4'b 0001, // index[120] PINMUX_MIO_OUTSEL_6
-    4'b 0001, // index[121] PINMUX_MIO_OUTSEL_7
-    4'b 0001, // index[122] PINMUX_MIO_OUTSEL_8
-    4'b 0001, // index[123] PINMUX_MIO_OUTSEL_9
-    4'b 0001, // index[124] PINMUX_MIO_OUTSEL_10
-    4'b 0001, // index[125] PINMUX_MIO_OUTSEL_11
-    4'b 0001, // index[126] PINMUX_MIO_OUTSEL_12
-    4'b 0001, // index[127] PINMUX_MIO_OUTSEL_13
-    4'b 0001, // index[128] PINMUX_MIO_OUTSEL_14
-    4'b 0001, // index[129] PINMUX_MIO_OUTSEL_15
-    4'b 0001, // index[130] PINMUX_MIO_OUTSEL_16
-    4'b 0001, // index[131] PINMUX_MIO_OUTSEL_17
-    4'b 0001, // index[132] PINMUX_MIO_OUTSEL_18
-    4'b 0001, // index[133] PINMUX_MIO_OUTSEL_19
-    4'b 0001, // index[134] PINMUX_MIO_OUTSEL_20
-    4'b 0001, // index[135] PINMUX_MIO_OUTSEL_21
-    4'b 0001, // index[136] PINMUX_MIO_OUTSEL_22
-    4'b 0001, // index[137] PINMUX_MIO_OUTSEL_23
-    4'b 0001, // index[138] PINMUX_MIO_OUTSEL_24
-    4'b 0001, // index[139] PINMUX_MIO_OUTSEL_25
-    4'b 0001, // index[140] PINMUX_MIO_OUTSEL_26
-    4'b 0001, // index[141] PINMUX_MIO_OUTSEL_27
-    4'b 0001, // index[142] PINMUX_MIO_OUTSEL_28
-    4'b 0001, // index[143] PINMUX_MIO_OUTSEL_29
-    4'b 0001, // index[144] PINMUX_MIO_OUTSEL_30
-    4'b 0001, // index[145] PINMUX_MIO_OUTSEL_31
-    4'b 0001, // index[146] PINMUX_MIO_PAD_ATTR_REGWEN_0
-    4'b 0001, // index[147] PINMUX_MIO_PAD_ATTR_REGWEN_1
-    4'b 0001, // index[148] PINMUX_MIO_PAD_ATTR_REGWEN_2
-    4'b 0001, // index[149] PINMUX_MIO_PAD_ATTR_REGWEN_3
-    4'b 0001, // index[150] PINMUX_MIO_PAD_ATTR_REGWEN_4
-    4'b 0001, // index[151] PINMUX_MIO_PAD_ATTR_REGWEN_5
-    4'b 0001, // index[152] PINMUX_MIO_PAD_ATTR_REGWEN_6
-    4'b 0001, // index[153] PINMUX_MIO_PAD_ATTR_REGWEN_7
-    4'b 0001, // index[154] PINMUX_MIO_PAD_ATTR_REGWEN_8
-    4'b 0001, // index[155] PINMUX_MIO_PAD_ATTR_REGWEN_9
-    4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_10
-    4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_11
-    4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_12
-    4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_13
-    4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_14
-    4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_15
-    4'b 0001, // index[162] PINMUX_MIO_PAD_ATTR_REGWEN_16
-    4'b 0001, // index[163] PINMUX_MIO_PAD_ATTR_REGWEN_17
-    4'b 0001, // index[164] PINMUX_MIO_PAD_ATTR_REGWEN_18
-    4'b 0001, // index[165] PINMUX_MIO_PAD_ATTR_REGWEN_19
-    4'b 0001, // index[166] PINMUX_MIO_PAD_ATTR_REGWEN_20
-    4'b 0001, // index[167] PINMUX_MIO_PAD_ATTR_REGWEN_21
-    4'b 0001, // index[168] PINMUX_MIO_PAD_ATTR_REGWEN_22
-    4'b 0001, // index[169] PINMUX_MIO_PAD_ATTR_REGWEN_23
-    4'b 0001, // index[170] PINMUX_MIO_PAD_ATTR_REGWEN_24
-    4'b 0001, // index[171] PINMUX_MIO_PAD_ATTR_REGWEN_25
-    4'b 0001, // index[172] PINMUX_MIO_PAD_ATTR_REGWEN_26
-    4'b 0001, // index[173] PINMUX_MIO_PAD_ATTR_REGWEN_27
-    4'b 0001, // index[174] PINMUX_MIO_PAD_ATTR_REGWEN_28
-    4'b 0001, // index[175] PINMUX_MIO_PAD_ATTR_REGWEN_29
-    4'b 0001, // index[176] PINMUX_MIO_PAD_ATTR_REGWEN_30
-    4'b 0001, // index[177] PINMUX_MIO_PAD_ATTR_REGWEN_31
-    4'b 0011, // index[178] PINMUX_MIO_PAD_ATTR_0
-    4'b 0011, // index[179] PINMUX_MIO_PAD_ATTR_1
-    4'b 0011, // index[180] PINMUX_MIO_PAD_ATTR_2
-    4'b 0011, // index[181] PINMUX_MIO_PAD_ATTR_3
-    4'b 0011, // index[182] PINMUX_MIO_PAD_ATTR_4
-    4'b 0011, // index[183] PINMUX_MIO_PAD_ATTR_5
-    4'b 0011, // index[184] PINMUX_MIO_PAD_ATTR_6
-    4'b 0011, // index[185] PINMUX_MIO_PAD_ATTR_7
-    4'b 0011, // index[186] PINMUX_MIO_PAD_ATTR_8
-    4'b 0011, // index[187] PINMUX_MIO_PAD_ATTR_9
-    4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_10
-    4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_11
-    4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_12
-    4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_13
-    4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_14
-    4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_15
-    4'b 0011, // index[194] PINMUX_MIO_PAD_ATTR_16
-    4'b 0011, // index[195] PINMUX_MIO_PAD_ATTR_17
-    4'b 0011, // index[196] PINMUX_MIO_PAD_ATTR_18
-    4'b 0011, // index[197] PINMUX_MIO_PAD_ATTR_19
-    4'b 0011, // index[198] PINMUX_MIO_PAD_ATTR_20
-    4'b 0011, // index[199] PINMUX_MIO_PAD_ATTR_21
-    4'b 0011, // index[200] PINMUX_MIO_PAD_ATTR_22
-    4'b 0011, // index[201] PINMUX_MIO_PAD_ATTR_23
-    4'b 0011, // index[202] PINMUX_MIO_PAD_ATTR_24
-    4'b 0011, // index[203] PINMUX_MIO_PAD_ATTR_25
-    4'b 0011, // index[204] PINMUX_MIO_PAD_ATTR_26
-    4'b 0011, // index[205] PINMUX_MIO_PAD_ATTR_27
-    4'b 0011, // index[206] PINMUX_MIO_PAD_ATTR_28
-    4'b 0011, // index[207] PINMUX_MIO_PAD_ATTR_29
-    4'b 0011, // index[208] PINMUX_MIO_PAD_ATTR_30
-    4'b 0011, // index[209] PINMUX_MIO_PAD_ATTR_31
-    4'b 0001, // index[210] PINMUX_DIO_PAD_ATTR_REGWEN_0
-    4'b 0001, // index[211] PINMUX_DIO_PAD_ATTR_REGWEN_1
-    4'b 0001, // index[212] PINMUX_DIO_PAD_ATTR_REGWEN_2
-    4'b 0001, // index[213] PINMUX_DIO_PAD_ATTR_REGWEN_3
-    4'b 0001, // index[214] PINMUX_DIO_PAD_ATTR_REGWEN_4
-    4'b 0001, // index[215] PINMUX_DIO_PAD_ATTR_REGWEN_5
-    4'b 0001, // index[216] PINMUX_DIO_PAD_ATTR_REGWEN_6
-    4'b 0001, // index[217] PINMUX_DIO_PAD_ATTR_REGWEN_7
-    4'b 0001, // index[218] PINMUX_DIO_PAD_ATTR_REGWEN_8
-    4'b 0001, // index[219] PINMUX_DIO_PAD_ATTR_REGWEN_9
-    4'b 0001, // index[220] PINMUX_DIO_PAD_ATTR_REGWEN_10
-    4'b 0001, // index[221] PINMUX_DIO_PAD_ATTR_REGWEN_11
-    4'b 0001, // index[222] PINMUX_DIO_PAD_ATTR_REGWEN_12
-    4'b 0001, // index[223] PINMUX_DIO_PAD_ATTR_REGWEN_13
-    4'b 0001, // index[224] PINMUX_DIO_PAD_ATTR_REGWEN_14
-    4'b 0011, // index[225] PINMUX_DIO_PAD_ATTR_0
-    4'b 0011, // index[226] PINMUX_DIO_PAD_ATTR_1
-    4'b 0011, // index[227] PINMUX_DIO_PAD_ATTR_2
-    4'b 0011, // index[228] PINMUX_DIO_PAD_ATTR_3
-    4'b 0011, // index[229] PINMUX_DIO_PAD_ATTR_4
-    4'b 0011, // index[230] PINMUX_DIO_PAD_ATTR_5
-    4'b 0011, // index[231] PINMUX_DIO_PAD_ATTR_6
-    4'b 0011, // index[232] PINMUX_DIO_PAD_ATTR_7
-    4'b 0011, // index[233] PINMUX_DIO_PAD_ATTR_8
-    4'b 0011, // index[234] PINMUX_DIO_PAD_ATTR_9
-    4'b 0011, // index[235] PINMUX_DIO_PAD_ATTR_10
-    4'b 0011, // index[236] PINMUX_DIO_PAD_ATTR_11
-    4'b 0011, // index[237] PINMUX_DIO_PAD_ATTR_12
-    4'b 0011, // index[238] PINMUX_DIO_PAD_ATTR_13
-    4'b 0011, // index[239] PINMUX_DIO_PAD_ATTR_14
-    4'b 1111, // index[240] PINMUX_MIO_PAD_SLEEP_STATUS
-    4'b 0001, // index[241] PINMUX_MIO_PAD_SLEEP_REGWEN_0
-    4'b 0001, // index[242] PINMUX_MIO_PAD_SLEEP_REGWEN_1
-    4'b 0001, // index[243] PINMUX_MIO_PAD_SLEEP_REGWEN_2
-    4'b 0001, // index[244] PINMUX_MIO_PAD_SLEEP_REGWEN_3
-    4'b 0001, // index[245] PINMUX_MIO_PAD_SLEEP_REGWEN_4
-    4'b 0001, // index[246] PINMUX_MIO_PAD_SLEEP_REGWEN_5
-    4'b 0001, // index[247] PINMUX_MIO_PAD_SLEEP_REGWEN_6
-    4'b 0001, // index[248] PINMUX_MIO_PAD_SLEEP_REGWEN_7
-    4'b 0001, // index[249] PINMUX_MIO_PAD_SLEEP_REGWEN_8
-    4'b 0001, // index[250] PINMUX_MIO_PAD_SLEEP_REGWEN_9
-    4'b 0001, // index[251] PINMUX_MIO_PAD_SLEEP_REGWEN_10
-    4'b 0001, // index[252] PINMUX_MIO_PAD_SLEEP_REGWEN_11
-    4'b 0001, // index[253] PINMUX_MIO_PAD_SLEEP_REGWEN_12
-    4'b 0001, // index[254] PINMUX_MIO_PAD_SLEEP_REGWEN_13
-    4'b 0001, // index[255] PINMUX_MIO_PAD_SLEEP_REGWEN_14
-    4'b 0001, // index[256] PINMUX_MIO_PAD_SLEEP_REGWEN_15
-    4'b 0001, // index[257] PINMUX_MIO_PAD_SLEEP_REGWEN_16
-    4'b 0001, // index[258] PINMUX_MIO_PAD_SLEEP_REGWEN_17
-    4'b 0001, // index[259] PINMUX_MIO_PAD_SLEEP_REGWEN_18
-    4'b 0001, // index[260] PINMUX_MIO_PAD_SLEEP_REGWEN_19
-    4'b 0001, // index[261] PINMUX_MIO_PAD_SLEEP_REGWEN_20
-    4'b 0001, // index[262] PINMUX_MIO_PAD_SLEEP_REGWEN_21
-    4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_REGWEN_22
-    4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_REGWEN_23
-    4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_REGWEN_24
-    4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_REGWEN_25
-    4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_REGWEN_26
-    4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_REGWEN_27
-    4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_REGWEN_28
-    4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_REGWEN_29
-    4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_REGWEN_30
-    4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_REGWEN_31
-    4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_EN_0
-    4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_EN_1
-    4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_EN_2
-    4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_EN_3
-    4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_EN_4
-    4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_EN_5
-    4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_EN_6
-    4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_EN_7
-    4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_EN_8
-    4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_EN_9
-    4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_EN_10
-    4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_EN_11
-    4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_EN_12
-    4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_EN_13
-    4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_EN_14
-    4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_EN_15
-    4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_EN_16
-    4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_EN_17
-    4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_EN_18
-    4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_EN_19
-    4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_EN_20
-    4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_EN_21
-    4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_EN_22
-    4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_EN_23
-    4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_EN_24
-    4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_EN_25
-    4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_EN_26
-    4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_EN_27
-    4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_EN_28
-    4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_EN_29
-    4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_EN_30
-    4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_EN_31
-    4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_MODE_0
-    4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_MODE_1
-    4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_MODE_2
-    4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_MODE_3
-    4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_MODE_4
-    4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_MODE_5
-    4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_MODE_6
-    4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_MODE_7
-    4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_MODE_8
-    4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_MODE_9
-    4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_MODE_10
-    4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_MODE_11
-    4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_MODE_12
-    4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_MODE_13
-    4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_MODE_14
-    4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_MODE_15
-    4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_MODE_16
-    4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_MODE_17
-    4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_MODE_18
-    4'b 0001, // index[324] PINMUX_MIO_PAD_SLEEP_MODE_19
-    4'b 0001, // index[325] PINMUX_MIO_PAD_SLEEP_MODE_20
-    4'b 0001, // index[326] PINMUX_MIO_PAD_SLEEP_MODE_21
-    4'b 0001, // index[327] PINMUX_MIO_PAD_SLEEP_MODE_22
-    4'b 0001, // index[328] PINMUX_MIO_PAD_SLEEP_MODE_23
-    4'b 0001, // index[329] PINMUX_MIO_PAD_SLEEP_MODE_24
-    4'b 0001, // index[330] PINMUX_MIO_PAD_SLEEP_MODE_25
-    4'b 0001, // index[331] PINMUX_MIO_PAD_SLEEP_MODE_26
-    4'b 0001, // index[332] PINMUX_MIO_PAD_SLEEP_MODE_27
-    4'b 0001, // index[333] PINMUX_MIO_PAD_SLEEP_MODE_28
-    4'b 0001, // index[334] PINMUX_MIO_PAD_SLEEP_MODE_29
-    4'b 0001, // index[335] PINMUX_MIO_PAD_SLEEP_MODE_30
-    4'b 0001, // index[336] PINMUX_MIO_PAD_SLEEP_MODE_31
-    4'b 0011, // index[337] PINMUX_DIO_PAD_SLEEP_STATUS
-    4'b 0001, // index[338] PINMUX_DIO_PAD_SLEEP_REGWEN_0
-    4'b 0001, // index[339] PINMUX_DIO_PAD_SLEEP_REGWEN_1
-    4'b 0001, // index[340] PINMUX_DIO_PAD_SLEEP_REGWEN_2
-    4'b 0001, // index[341] PINMUX_DIO_PAD_SLEEP_REGWEN_3
-    4'b 0001, // index[342] PINMUX_DIO_PAD_SLEEP_REGWEN_4
-    4'b 0001, // index[343] PINMUX_DIO_PAD_SLEEP_REGWEN_5
-    4'b 0001, // index[344] PINMUX_DIO_PAD_SLEEP_REGWEN_6
-    4'b 0001, // index[345] PINMUX_DIO_PAD_SLEEP_REGWEN_7
-    4'b 0001, // index[346] PINMUX_DIO_PAD_SLEEP_REGWEN_8
-    4'b 0001, // index[347] PINMUX_DIO_PAD_SLEEP_REGWEN_9
-    4'b 0001, // index[348] PINMUX_DIO_PAD_SLEEP_REGWEN_10
-    4'b 0001, // index[349] PINMUX_DIO_PAD_SLEEP_REGWEN_11
-    4'b 0001, // index[350] PINMUX_DIO_PAD_SLEEP_REGWEN_12
-    4'b 0001, // index[351] PINMUX_DIO_PAD_SLEEP_REGWEN_13
-    4'b 0001, // index[352] PINMUX_DIO_PAD_SLEEP_REGWEN_14
-    4'b 0001, // index[353] PINMUX_DIO_PAD_SLEEP_EN_0
-    4'b 0001, // index[354] PINMUX_DIO_PAD_SLEEP_EN_1
-    4'b 0001, // index[355] PINMUX_DIO_PAD_SLEEP_EN_2
-    4'b 0001, // index[356] PINMUX_DIO_PAD_SLEEP_EN_3
-    4'b 0001, // index[357] PINMUX_DIO_PAD_SLEEP_EN_4
-    4'b 0001, // index[358] PINMUX_DIO_PAD_SLEEP_EN_5
-    4'b 0001, // index[359] PINMUX_DIO_PAD_SLEEP_EN_6
-    4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_EN_7
-    4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_EN_8
-    4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_EN_9
-    4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_EN_10
-    4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_EN_11
-    4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_EN_12
-    4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_EN_13
-    4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_EN_14
-    4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_MODE_0
-    4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_MODE_1
-    4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_MODE_2
-    4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_MODE_3
-    4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_MODE_4
-    4'b 0001, // index[373] PINMUX_DIO_PAD_SLEEP_MODE_5
-    4'b 0001, // index[374] PINMUX_DIO_PAD_SLEEP_MODE_6
-    4'b 0001, // index[375] PINMUX_DIO_PAD_SLEEP_MODE_7
-    4'b 0001, // index[376] PINMUX_DIO_PAD_SLEEP_MODE_8
-    4'b 0001, // index[377] PINMUX_DIO_PAD_SLEEP_MODE_9
-    4'b 0001, // index[378] PINMUX_DIO_PAD_SLEEP_MODE_10
-    4'b 0001, // index[379] PINMUX_DIO_PAD_SLEEP_MODE_11
-    4'b 0001, // index[380] PINMUX_DIO_PAD_SLEEP_MODE_12
-    4'b 0001, // index[381] PINMUX_DIO_PAD_SLEEP_MODE_13
-    4'b 0001, // index[382] PINMUX_DIO_PAD_SLEEP_MODE_14
-    4'b 0001, // index[383] PINMUX_WKUP_DETECTOR_REGWEN_0
-    4'b 0001, // index[384] PINMUX_WKUP_DETECTOR_REGWEN_1
-    4'b 0001, // index[385] PINMUX_WKUP_DETECTOR_REGWEN_2
-    4'b 0001, // index[386] PINMUX_WKUP_DETECTOR_REGWEN_3
-    4'b 0001, // index[387] PINMUX_WKUP_DETECTOR_REGWEN_4
-    4'b 0001, // index[388] PINMUX_WKUP_DETECTOR_REGWEN_5
-    4'b 0001, // index[389] PINMUX_WKUP_DETECTOR_REGWEN_6
-    4'b 0001, // index[390] PINMUX_WKUP_DETECTOR_REGWEN_7
-    4'b 0001, // index[391] PINMUX_WKUP_DETECTOR_EN_0
-    4'b 0001, // index[392] PINMUX_WKUP_DETECTOR_EN_1
-    4'b 0001, // index[393] PINMUX_WKUP_DETECTOR_EN_2
-    4'b 0001, // index[394] PINMUX_WKUP_DETECTOR_EN_3
-    4'b 0001, // index[395] PINMUX_WKUP_DETECTOR_EN_4
-    4'b 0001, // index[396] PINMUX_WKUP_DETECTOR_EN_5
-    4'b 0001, // index[397] PINMUX_WKUP_DETECTOR_EN_6
-    4'b 0001, // index[398] PINMUX_WKUP_DETECTOR_EN_7
-    4'b 0001, // index[399] PINMUX_WKUP_DETECTOR_0
-    4'b 0001, // index[400] PINMUX_WKUP_DETECTOR_1
-    4'b 0001, // index[401] PINMUX_WKUP_DETECTOR_2
-    4'b 0001, // index[402] PINMUX_WKUP_DETECTOR_3
-    4'b 0001, // index[403] PINMUX_WKUP_DETECTOR_4
-    4'b 0001, // index[404] PINMUX_WKUP_DETECTOR_5
-    4'b 0001, // index[405] PINMUX_WKUP_DETECTOR_6
-    4'b 0001, // index[406] PINMUX_WKUP_DETECTOR_7
-    4'b 0001, // index[407] PINMUX_WKUP_DETECTOR_CNT_TH_0
-    4'b 0001, // index[408] PINMUX_WKUP_DETECTOR_CNT_TH_1
-    4'b 0001, // index[409] PINMUX_WKUP_DETECTOR_CNT_TH_2
-    4'b 0001, // index[410] PINMUX_WKUP_DETECTOR_CNT_TH_3
-    4'b 0001, // index[411] PINMUX_WKUP_DETECTOR_CNT_TH_4
-    4'b 0001, // index[412] PINMUX_WKUP_DETECTOR_CNT_TH_5
-    4'b 0001, // index[413] PINMUX_WKUP_DETECTOR_CNT_TH_6
-    4'b 0001, // index[414] PINMUX_WKUP_DETECTOR_CNT_TH_7
-    4'b 0001, // index[415] PINMUX_WKUP_DETECTOR_PADSEL_0
-    4'b 0001, // index[416] PINMUX_WKUP_DETECTOR_PADSEL_1
-    4'b 0001, // index[417] PINMUX_WKUP_DETECTOR_PADSEL_2
-    4'b 0001, // index[418] PINMUX_WKUP_DETECTOR_PADSEL_3
-    4'b 0001, // index[419] PINMUX_WKUP_DETECTOR_PADSEL_4
-    4'b 0001, // index[420] PINMUX_WKUP_DETECTOR_PADSEL_5
-    4'b 0001, // index[421] PINMUX_WKUP_DETECTOR_PADSEL_6
-    4'b 0001, // index[422] PINMUX_WKUP_DETECTOR_PADSEL_7
-    4'b 0001  // index[423] PINMUX_WKUP_CAUSE
+    4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_REGWEN_41
+    4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_REGWEN_42
+    4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_REGWEN_43
+    4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_REGWEN_44
+    4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_REGWEN_45
+    4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_0
+    4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_1
+    4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_2
+    4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_3
+    4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_4
+    4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_5
+    4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_6
+    4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_7
+    4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_8
+    4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_9
+    4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_10
+    4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_11
+    4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_12
+    4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_13
+    4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_14
+    4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_15
+    4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_16
+    4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_17
+    4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_18
+    4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_19
+    4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_20
+    4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_21
+    4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_22
+    4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_23
+    4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_24
+    4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_25
+    4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_26
+    4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_27
+    4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_28
+    4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_29
+    4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_30
+    4'b 0001, // index[ 77] PINMUX_MIO_PERIPH_INSEL_31
+    4'b 0001, // index[ 78] PINMUX_MIO_PERIPH_INSEL_32
+    4'b 0001, // index[ 79] PINMUX_MIO_PERIPH_INSEL_33
+    4'b 0001, // index[ 80] PINMUX_MIO_PERIPH_INSEL_34
+    4'b 0001, // index[ 81] PINMUX_MIO_PERIPH_INSEL_35
+    4'b 0001, // index[ 82] PINMUX_MIO_PERIPH_INSEL_36
+    4'b 0001, // index[ 83] PINMUX_MIO_PERIPH_INSEL_37
+    4'b 0001, // index[ 84] PINMUX_MIO_PERIPH_INSEL_38
+    4'b 0001, // index[ 85] PINMUX_MIO_PERIPH_INSEL_39
+    4'b 0001, // index[ 86] PINMUX_MIO_PERIPH_INSEL_40
+    4'b 0001, // index[ 87] PINMUX_MIO_PERIPH_INSEL_41
+    4'b 0001, // index[ 88] PINMUX_MIO_PERIPH_INSEL_42
+    4'b 0001, // index[ 89] PINMUX_MIO_PERIPH_INSEL_43
+    4'b 0001, // index[ 90] PINMUX_MIO_PERIPH_INSEL_44
+    4'b 0001, // index[ 91] PINMUX_MIO_PERIPH_INSEL_45
+    4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_0
+    4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_1
+    4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_2
+    4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_3
+    4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_4
+    4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_5
+    4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_REGWEN_6
+    4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_REGWEN_7
+    4'b 0001, // index[100] PINMUX_MIO_OUTSEL_REGWEN_8
+    4'b 0001, // index[101] PINMUX_MIO_OUTSEL_REGWEN_9
+    4'b 0001, // index[102] PINMUX_MIO_OUTSEL_REGWEN_10
+    4'b 0001, // index[103] PINMUX_MIO_OUTSEL_REGWEN_11
+    4'b 0001, // index[104] PINMUX_MIO_OUTSEL_REGWEN_12
+    4'b 0001, // index[105] PINMUX_MIO_OUTSEL_REGWEN_13
+    4'b 0001, // index[106] PINMUX_MIO_OUTSEL_REGWEN_14
+    4'b 0001, // index[107] PINMUX_MIO_OUTSEL_REGWEN_15
+    4'b 0001, // index[108] PINMUX_MIO_OUTSEL_REGWEN_16
+    4'b 0001, // index[109] PINMUX_MIO_OUTSEL_REGWEN_17
+    4'b 0001, // index[110] PINMUX_MIO_OUTSEL_REGWEN_18
+    4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_19
+    4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_20
+    4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_21
+    4'b 0001, // index[114] PINMUX_MIO_OUTSEL_REGWEN_22
+    4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_23
+    4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_24
+    4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_25
+    4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_26
+    4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_27
+    4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_28
+    4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_29
+    4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_30
+    4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_31
+    4'b 0001, // index[124] PINMUX_MIO_OUTSEL_0
+    4'b 0001, // index[125] PINMUX_MIO_OUTSEL_1
+    4'b 0001, // index[126] PINMUX_MIO_OUTSEL_2
+    4'b 0001, // index[127] PINMUX_MIO_OUTSEL_3
+    4'b 0001, // index[128] PINMUX_MIO_OUTSEL_4
+    4'b 0001, // index[129] PINMUX_MIO_OUTSEL_5
+    4'b 0001, // index[130] PINMUX_MIO_OUTSEL_6
+    4'b 0001, // index[131] PINMUX_MIO_OUTSEL_7
+    4'b 0001, // index[132] PINMUX_MIO_OUTSEL_8
+    4'b 0001, // index[133] PINMUX_MIO_OUTSEL_9
+    4'b 0001, // index[134] PINMUX_MIO_OUTSEL_10
+    4'b 0001, // index[135] PINMUX_MIO_OUTSEL_11
+    4'b 0001, // index[136] PINMUX_MIO_OUTSEL_12
+    4'b 0001, // index[137] PINMUX_MIO_OUTSEL_13
+    4'b 0001, // index[138] PINMUX_MIO_OUTSEL_14
+    4'b 0001, // index[139] PINMUX_MIO_OUTSEL_15
+    4'b 0001, // index[140] PINMUX_MIO_OUTSEL_16
+    4'b 0001, // index[141] PINMUX_MIO_OUTSEL_17
+    4'b 0001, // index[142] PINMUX_MIO_OUTSEL_18
+    4'b 0001, // index[143] PINMUX_MIO_OUTSEL_19
+    4'b 0001, // index[144] PINMUX_MIO_OUTSEL_20
+    4'b 0001, // index[145] PINMUX_MIO_OUTSEL_21
+    4'b 0001, // index[146] PINMUX_MIO_OUTSEL_22
+    4'b 0001, // index[147] PINMUX_MIO_OUTSEL_23
+    4'b 0001, // index[148] PINMUX_MIO_OUTSEL_24
+    4'b 0001, // index[149] PINMUX_MIO_OUTSEL_25
+    4'b 0001, // index[150] PINMUX_MIO_OUTSEL_26
+    4'b 0001, // index[151] PINMUX_MIO_OUTSEL_27
+    4'b 0001, // index[152] PINMUX_MIO_OUTSEL_28
+    4'b 0001, // index[153] PINMUX_MIO_OUTSEL_29
+    4'b 0001, // index[154] PINMUX_MIO_OUTSEL_30
+    4'b 0001, // index[155] PINMUX_MIO_OUTSEL_31
+    4'b 0001, // index[156] PINMUX_MIO_PAD_ATTR_REGWEN_0
+    4'b 0001, // index[157] PINMUX_MIO_PAD_ATTR_REGWEN_1
+    4'b 0001, // index[158] PINMUX_MIO_PAD_ATTR_REGWEN_2
+    4'b 0001, // index[159] PINMUX_MIO_PAD_ATTR_REGWEN_3
+    4'b 0001, // index[160] PINMUX_MIO_PAD_ATTR_REGWEN_4
+    4'b 0001, // index[161] PINMUX_MIO_PAD_ATTR_REGWEN_5
+    4'b 0001, // index[162] PINMUX_MIO_PAD_ATTR_REGWEN_6
+    4'b 0001, // index[163] PINMUX_MIO_PAD_ATTR_REGWEN_7
+    4'b 0001, // index[164] PINMUX_MIO_PAD_ATTR_REGWEN_8
+    4'b 0001, // index[165] PINMUX_MIO_PAD_ATTR_REGWEN_9
+    4'b 0001, // index[166] PINMUX_MIO_PAD_ATTR_REGWEN_10
+    4'b 0001, // index[167] PINMUX_MIO_PAD_ATTR_REGWEN_11
+    4'b 0001, // index[168] PINMUX_MIO_PAD_ATTR_REGWEN_12
+    4'b 0001, // index[169] PINMUX_MIO_PAD_ATTR_REGWEN_13
+    4'b 0001, // index[170] PINMUX_MIO_PAD_ATTR_REGWEN_14
+    4'b 0001, // index[171] PINMUX_MIO_PAD_ATTR_REGWEN_15
+    4'b 0001, // index[172] PINMUX_MIO_PAD_ATTR_REGWEN_16
+    4'b 0001, // index[173] PINMUX_MIO_PAD_ATTR_REGWEN_17
+    4'b 0001, // index[174] PINMUX_MIO_PAD_ATTR_REGWEN_18
+    4'b 0001, // index[175] PINMUX_MIO_PAD_ATTR_REGWEN_19
+    4'b 0001, // index[176] PINMUX_MIO_PAD_ATTR_REGWEN_20
+    4'b 0001, // index[177] PINMUX_MIO_PAD_ATTR_REGWEN_21
+    4'b 0001, // index[178] PINMUX_MIO_PAD_ATTR_REGWEN_22
+    4'b 0001, // index[179] PINMUX_MIO_PAD_ATTR_REGWEN_23
+    4'b 0001, // index[180] PINMUX_MIO_PAD_ATTR_REGWEN_24
+    4'b 0001, // index[181] PINMUX_MIO_PAD_ATTR_REGWEN_25
+    4'b 0001, // index[182] PINMUX_MIO_PAD_ATTR_REGWEN_26
+    4'b 0001, // index[183] PINMUX_MIO_PAD_ATTR_REGWEN_27
+    4'b 0001, // index[184] PINMUX_MIO_PAD_ATTR_REGWEN_28
+    4'b 0001, // index[185] PINMUX_MIO_PAD_ATTR_REGWEN_29
+    4'b 0001, // index[186] PINMUX_MIO_PAD_ATTR_REGWEN_30
+    4'b 0001, // index[187] PINMUX_MIO_PAD_ATTR_REGWEN_31
+    4'b 0011, // index[188] PINMUX_MIO_PAD_ATTR_0
+    4'b 0011, // index[189] PINMUX_MIO_PAD_ATTR_1
+    4'b 0011, // index[190] PINMUX_MIO_PAD_ATTR_2
+    4'b 0011, // index[191] PINMUX_MIO_PAD_ATTR_3
+    4'b 0011, // index[192] PINMUX_MIO_PAD_ATTR_4
+    4'b 0011, // index[193] PINMUX_MIO_PAD_ATTR_5
+    4'b 0011, // index[194] PINMUX_MIO_PAD_ATTR_6
+    4'b 0011, // index[195] PINMUX_MIO_PAD_ATTR_7
+    4'b 0011, // index[196] PINMUX_MIO_PAD_ATTR_8
+    4'b 0011, // index[197] PINMUX_MIO_PAD_ATTR_9
+    4'b 0011, // index[198] PINMUX_MIO_PAD_ATTR_10
+    4'b 0011, // index[199] PINMUX_MIO_PAD_ATTR_11
+    4'b 0011, // index[200] PINMUX_MIO_PAD_ATTR_12
+    4'b 0011, // index[201] PINMUX_MIO_PAD_ATTR_13
+    4'b 0011, // index[202] PINMUX_MIO_PAD_ATTR_14
+    4'b 0011, // index[203] PINMUX_MIO_PAD_ATTR_15
+    4'b 0011, // index[204] PINMUX_MIO_PAD_ATTR_16
+    4'b 0011, // index[205] PINMUX_MIO_PAD_ATTR_17
+    4'b 0011, // index[206] PINMUX_MIO_PAD_ATTR_18
+    4'b 0011, // index[207] PINMUX_MIO_PAD_ATTR_19
+    4'b 0011, // index[208] PINMUX_MIO_PAD_ATTR_20
+    4'b 0011, // index[209] PINMUX_MIO_PAD_ATTR_21
+    4'b 0011, // index[210] PINMUX_MIO_PAD_ATTR_22
+    4'b 0011, // index[211] PINMUX_MIO_PAD_ATTR_23
+    4'b 0011, // index[212] PINMUX_MIO_PAD_ATTR_24
+    4'b 0011, // index[213] PINMUX_MIO_PAD_ATTR_25
+    4'b 0011, // index[214] PINMUX_MIO_PAD_ATTR_26
+    4'b 0011, // index[215] PINMUX_MIO_PAD_ATTR_27
+    4'b 0011, // index[216] PINMUX_MIO_PAD_ATTR_28
+    4'b 0011, // index[217] PINMUX_MIO_PAD_ATTR_29
+    4'b 0011, // index[218] PINMUX_MIO_PAD_ATTR_30
+    4'b 0011, // index[219] PINMUX_MIO_PAD_ATTR_31
+    4'b 0001, // index[220] PINMUX_DIO_PAD_ATTR_REGWEN_0
+    4'b 0001, // index[221] PINMUX_DIO_PAD_ATTR_REGWEN_1
+    4'b 0001, // index[222] PINMUX_DIO_PAD_ATTR_REGWEN_2
+    4'b 0001, // index[223] PINMUX_DIO_PAD_ATTR_REGWEN_3
+    4'b 0001, // index[224] PINMUX_DIO_PAD_ATTR_REGWEN_4
+    4'b 0001, // index[225] PINMUX_DIO_PAD_ATTR_REGWEN_5
+    4'b 0001, // index[226] PINMUX_DIO_PAD_ATTR_REGWEN_6
+    4'b 0001, // index[227] PINMUX_DIO_PAD_ATTR_REGWEN_7
+    4'b 0001, // index[228] PINMUX_DIO_PAD_ATTR_REGWEN_8
+    4'b 0001, // index[229] PINMUX_DIO_PAD_ATTR_REGWEN_9
+    4'b 0001, // index[230] PINMUX_DIO_PAD_ATTR_REGWEN_10
+    4'b 0001, // index[231] PINMUX_DIO_PAD_ATTR_REGWEN_11
+    4'b 0001, // index[232] PINMUX_DIO_PAD_ATTR_REGWEN_12
+    4'b 0001, // index[233] PINMUX_DIO_PAD_ATTR_REGWEN_13
+    4'b 0001, // index[234] PINMUX_DIO_PAD_ATTR_REGWEN_14
+    4'b 0001, // index[235] PINMUX_DIO_PAD_ATTR_REGWEN_15
+    4'b 0001, // index[236] PINMUX_DIO_PAD_ATTR_REGWEN_16
+    4'b 0001, // index[237] PINMUX_DIO_PAD_ATTR_REGWEN_17
+    4'b 0001, // index[238] PINMUX_DIO_PAD_ATTR_REGWEN_18
+    4'b 0001, // index[239] PINMUX_DIO_PAD_ATTR_REGWEN_19
+    4'b 0001, // index[240] PINMUX_DIO_PAD_ATTR_REGWEN_20
+    4'b 0011, // index[241] PINMUX_DIO_PAD_ATTR_0
+    4'b 0011, // index[242] PINMUX_DIO_PAD_ATTR_1
+    4'b 0011, // index[243] PINMUX_DIO_PAD_ATTR_2
+    4'b 0011, // index[244] PINMUX_DIO_PAD_ATTR_3
+    4'b 0011, // index[245] PINMUX_DIO_PAD_ATTR_4
+    4'b 0011, // index[246] PINMUX_DIO_PAD_ATTR_5
+    4'b 0011, // index[247] PINMUX_DIO_PAD_ATTR_6
+    4'b 0011, // index[248] PINMUX_DIO_PAD_ATTR_7
+    4'b 0011, // index[249] PINMUX_DIO_PAD_ATTR_8
+    4'b 0011, // index[250] PINMUX_DIO_PAD_ATTR_9
+    4'b 0011, // index[251] PINMUX_DIO_PAD_ATTR_10
+    4'b 0011, // index[252] PINMUX_DIO_PAD_ATTR_11
+    4'b 0011, // index[253] PINMUX_DIO_PAD_ATTR_12
+    4'b 0011, // index[254] PINMUX_DIO_PAD_ATTR_13
+    4'b 0011, // index[255] PINMUX_DIO_PAD_ATTR_14
+    4'b 0011, // index[256] PINMUX_DIO_PAD_ATTR_15
+    4'b 0011, // index[257] PINMUX_DIO_PAD_ATTR_16
+    4'b 0011, // index[258] PINMUX_DIO_PAD_ATTR_17
+    4'b 0011, // index[259] PINMUX_DIO_PAD_ATTR_18
+    4'b 0011, // index[260] PINMUX_DIO_PAD_ATTR_19
+    4'b 0011, // index[261] PINMUX_DIO_PAD_ATTR_20
+    4'b 1111, // index[262] PINMUX_MIO_PAD_SLEEP_STATUS
+    4'b 0001, // index[263] PINMUX_MIO_PAD_SLEEP_REGWEN_0
+    4'b 0001, // index[264] PINMUX_MIO_PAD_SLEEP_REGWEN_1
+    4'b 0001, // index[265] PINMUX_MIO_PAD_SLEEP_REGWEN_2
+    4'b 0001, // index[266] PINMUX_MIO_PAD_SLEEP_REGWEN_3
+    4'b 0001, // index[267] PINMUX_MIO_PAD_SLEEP_REGWEN_4
+    4'b 0001, // index[268] PINMUX_MIO_PAD_SLEEP_REGWEN_5
+    4'b 0001, // index[269] PINMUX_MIO_PAD_SLEEP_REGWEN_6
+    4'b 0001, // index[270] PINMUX_MIO_PAD_SLEEP_REGWEN_7
+    4'b 0001, // index[271] PINMUX_MIO_PAD_SLEEP_REGWEN_8
+    4'b 0001, // index[272] PINMUX_MIO_PAD_SLEEP_REGWEN_9
+    4'b 0001, // index[273] PINMUX_MIO_PAD_SLEEP_REGWEN_10
+    4'b 0001, // index[274] PINMUX_MIO_PAD_SLEEP_REGWEN_11
+    4'b 0001, // index[275] PINMUX_MIO_PAD_SLEEP_REGWEN_12
+    4'b 0001, // index[276] PINMUX_MIO_PAD_SLEEP_REGWEN_13
+    4'b 0001, // index[277] PINMUX_MIO_PAD_SLEEP_REGWEN_14
+    4'b 0001, // index[278] PINMUX_MIO_PAD_SLEEP_REGWEN_15
+    4'b 0001, // index[279] PINMUX_MIO_PAD_SLEEP_REGWEN_16
+    4'b 0001, // index[280] PINMUX_MIO_PAD_SLEEP_REGWEN_17
+    4'b 0001, // index[281] PINMUX_MIO_PAD_SLEEP_REGWEN_18
+    4'b 0001, // index[282] PINMUX_MIO_PAD_SLEEP_REGWEN_19
+    4'b 0001, // index[283] PINMUX_MIO_PAD_SLEEP_REGWEN_20
+    4'b 0001, // index[284] PINMUX_MIO_PAD_SLEEP_REGWEN_21
+    4'b 0001, // index[285] PINMUX_MIO_PAD_SLEEP_REGWEN_22
+    4'b 0001, // index[286] PINMUX_MIO_PAD_SLEEP_REGWEN_23
+    4'b 0001, // index[287] PINMUX_MIO_PAD_SLEEP_REGWEN_24
+    4'b 0001, // index[288] PINMUX_MIO_PAD_SLEEP_REGWEN_25
+    4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_REGWEN_26
+    4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_REGWEN_27
+    4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_REGWEN_28
+    4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_REGWEN_29
+    4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_REGWEN_30
+    4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_REGWEN_31
+    4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_EN_0
+    4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_EN_1
+    4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_EN_2
+    4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_EN_3
+    4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_EN_4
+    4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_EN_5
+    4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_EN_6
+    4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_EN_7
+    4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_EN_8
+    4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_EN_9
+    4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_EN_10
+    4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_EN_11
+    4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_EN_12
+    4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_EN_13
+    4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_EN_14
+    4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_EN_15
+    4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_EN_16
+    4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_EN_17
+    4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_EN_18
+    4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_EN_19
+    4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_EN_20
+    4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_EN_21
+    4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_EN_22
+    4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_EN_23
+    4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_EN_24
+    4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_EN_25
+    4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_EN_26
+    4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_EN_27
+    4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_EN_28
+    4'b 0001, // index[324] PINMUX_MIO_PAD_SLEEP_EN_29
+    4'b 0001, // index[325] PINMUX_MIO_PAD_SLEEP_EN_30
+    4'b 0001, // index[326] PINMUX_MIO_PAD_SLEEP_EN_31
+    4'b 0001, // index[327] PINMUX_MIO_PAD_SLEEP_MODE_0
+    4'b 0001, // index[328] PINMUX_MIO_PAD_SLEEP_MODE_1
+    4'b 0001, // index[329] PINMUX_MIO_PAD_SLEEP_MODE_2
+    4'b 0001, // index[330] PINMUX_MIO_PAD_SLEEP_MODE_3
+    4'b 0001, // index[331] PINMUX_MIO_PAD_SLEEP_MODE_4
+    4'b 0001, // index[332] PINMUX_MIO_PAD_SLEEP_MODE_5
+    4'b 0001, // index[333] PINMUX_MIO_PAD_SLEEP_MODE_6
+    4'b 0001, // index[334] PINMUX_MIO_PAD_SLEEP_MODE_7
+    4'b 0001, // index[335] PINMUX_MIO_PAD_SLEEP_MODE_8
+    4'b 0001, // index[336] PINMUX_MIO_PAD_SLEEP_MODE_9
+    4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_MODE_10
+    4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_MODE_11
+    4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_MODE_12
+    4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_MODE_13
+    4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_MODE_14
+    4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_MODE_15
+    4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_MODE_16
+    4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_MODE_17
+    4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_MODE_18
+    4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_MODE_19
+    4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_MODE_20
+    4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_MODE_21
+    4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_MODE_22
+    4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_MODE_23
+    4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_MODE_24
+    4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_MODE_25
+    4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_MODE_26
+    4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_MODE_27
+    4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_MODE_28
+    4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_MODE_29
+    4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_MODE_30
+    4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_MODE_31
+    4'b 0111, // index[359] PINMUX_DIO_PAD_SLEEP_STATUS
+    4'b 0001, // index[360] PINMUX_DIO_PAD_SLEEP_REGWEN_0
+    4'b 0001, // index[361] PINMUX_DIO_PAD_SLEEP_REGWEN_1
+    4'b 0001, // index[362] PINMUX_DIO_PAD_SLEEP_REGWEN_2
+    4'b 0001, // index[363] PINMUX_DIO_PAD_SLEEP_REGWEN_3
+    4'b 0001, // index[364] PINMUX_DIO_PAD_SLEEP_REGWEN_4
+    4'b 0001, // index[365] PINMUX_DIO_PAD_SLEEP_REGWEN_5
+    4'b 0001, // index[366] PINMUX_DIO_PAD_SLEEP_REGWEN_6
+    4'b 0001, // index[367] PINMUX_DIO_PAD_SLEEP_REGWEN_7
+    4'b 0001, // index[368] PINMUX_DIO_PAD_SLEEP_REGWEN_8
+    4'b 0001, // index[369] PINMUX_DIO_PAD_SLEEP_REGWEN_9
+    4'b 0001, // index[370] PINMUX_DIO_PAD_SLEEP_REGWEN_10
+    4'b 0001, // index[371] PINMUX_DIO_PAD_SLEEP_REGWEN_11
+    4'b 0001, // index[372] PINMUX_DIO_PAD_SLEEP_REGWEN_12
+    4'b 0001, // index[373] PINMUX_DIO_PAD_SLEEP_REGWEN_13
+    4'b 0001, // index[374] PINMUX_DIO_PAD_SLEEP_REGWEN_14
+    4'b 0001, // index[375] PINMUX_DIO_PAD_SLEEP_REGWEN_15
+    4'b 0001, // index[376] PINMUX_DIO_PAD_SLEEP_REGWEN_16
+    4'b 0001, // index[377] PINMUX_DIO_PAD_SLEEP_REGWEN_17
+    4'b 0001, // index[378] PINMUX_DIO_PAD_SLEEP_REGWEN_18
+    4'b 0001, // index[379] PINMUX_DIO_PAD_SLEEP_REGWEN_19
+    4'b 0001, // index[380] PINMUX_DIO_PAD_SLEEP_REGWEN_20
+    4'b 0001, // index[381] PINMUX_DIO_PAD_SLEEP_EN_0
+    4'b 0001, // index[382] PINMUX_DIO_PAD_SLEEP_EN_1
+    4'b 0001, // index[383] PINMUX_DIO_PAD_SLEEP_EN_2
+    4'b 0001, // index[384] PINMUX_DIO_PAD_SLEEP_EN_3
+    4'b 0001, // index[385] PINMUX_DIO_PAD_SLEEP_EN_4
+    4'b 0001, // index[386] PINMUX_DIO_PAD_SLEEP_EN_5
+    4'b 0001, // index[387] PINMUX_DIO_PAD_SLEEP_EN_6
+    4'b 0001, // index[388] PINMUX_DIO_PAD_SLEEP_EN_7
+    4'b 0001, // index[389] PINMUX_DIO_PAD_SLEEP_EN_8
+    4'b 0001, // index[390] PINMUX_DIO_PAD_SLEEP_EN_9
+    4'b 0001, // index[391] PINMUX_DIO_PAD_SLEEP_EN_10
+    4'b 0001, // index[392] PINMUX_DIO_PAD_SLEEP_EN_11
+    4'b 0001, // index[393] PINMUX_DIO_PAD_SLEEP_EN_12
+    4'b 0001, // index[394] PINMUX_DIO_PAD_SLEEP_EN_13
+    4'b 0001, // index[395] PINMUX_DIO_PAD_SLEEP_EN_14
+    4'b 0001, // index[396] PINMUX_DIO_PAD_SLEEP_EN_15
+    4'b 0001, // index[397] PINMUX_DIO_PAD_SLEEP_EN_16
+    4'b 0001, // index[398] PINMUX_DIO_PAD_SLEEP_EN_17
+    4'b 0001, // index[399] PINMUX_DIO_PAD_SLEEP_EN_18
+    4'b 0001, // index[400] PINMUX_DIO_PAD_SLEEP_EN_19
+    4'b 0001, // index[401] PINMUX_DIO_PAD_SLEEP_EN_20
+    4'b 0001, // index[402] PINMUX_DIO_PAD_SLEEP_MODE_0
+    4'b 0001, // index[403] PINMUX_DIO_PAD_SLEEP_MODE_1
+    4'b 0001, // index[404] PINMUX_DIO_PAD_SLEEP_MODE_2
+    4'b 0001, // index[405] PINMUX_DIO_PAD_SLEEP_MODE_3
+    4'b 0001, // index[406] PINMUX_DIO_PAD_SLEEP_MODE_4
+    4'b 0001, // index[407] PINMUX_DIO_PAD_SLEEP_MODE_5
+    4'b 0001, // index[408] PINMUX_DIO_PAD_SLEEP_MODE_6
+    4'b 0001, // index[409] PINMUX_DIO_PAD_SLEEP_MODE_7
+    4'b 0001, // index[410] PINMUX_DIO_PAD_SLEEP_MODE_8
+    4'b 0001, // index[411] PINMUX_DIO_PAD_SLEEP_MODE_9
+    4'b 0001, // index[412] PINMUX_DIO_PAD_SLEEP_MODE_10
+    4'b 0001, // index[413] PINMUX_DIO_PAD_SLEEP_MODE_11
+    4'b 0001, // index[414] PINMUX_DIO_PAD_SLEEP_MODE_12
+    4'b 0001, // index[415] PINMUX_DIO_PAD_SLEEP_MODE_13
+    4'b 0001, // index[416] PINMUX_DIO_PAD_SLEEP_MODE_14
+    4'b 0001, // index[417] PINMUX_DIO_PAD_SLEEP_MODE_15
+    4'b 0001, // index[418] PINMUX_DIO_PAD_SLEEP_MODE_16
+    4'b 0001, // index[419] PINMUX_DIO_PAD_SLEEP_MODE_17
+    4'b 0001, // index[420] PINMUX_DIO_PAD_SLEEP_MODE_18
+    4'b 0001, // index[421] PINMUX_DIO_PAD_SLEEP_MODE_19
+    4'b 0001, // index[422] PINMUX_DIO_PAD_SLEEP_MODE_20
+    4'b 0001, // index[423] PINMUX_WKUP_DETECTOR_REGWEN_0
+    4'b 0001, // index[424] PINMUX_WKUP_DETECTOR_REGWEN_1
+    4'b 0001, // index[425] PINMUX_WKUP_DETECTOR_REGWEN_2
+    4'b 0001, // index[426] PINMUX_WKUP_DETECTOR_REGWEN_3
+    4'b 0001, // index[427] PINMUX_WKUP_DETECTOR_REGWEN_4
+    4'b 0001, // index[428] PINMUX_WKUP_DETECTOR_REGWEN_5
+    4'b 0001, // index[429] PINMUX_WKUP_DETECTOR_REGWEN_6
+    4'b 0001, // index[430] PINMUX_WKUP_DETECTOR_REGWEN_7
+    4'b 0001, // index[431] PINMUX_WKUP_DETECTOR_EN_0
+    4'b 0001, // index[432] PINMUX_WKUP_DETECTOR_EN_1
+    4'b 0001, // index[433] PINMUX_WKUP_DETECTOR_EN_2
+    4'b 0001, // index[434] PINMUX_WKUP_DETECTOR_EN_3
+    4'b 0001, // index[435] PINMUX_WKUP_DETECTOR_EN_4
+    4'b 0001, // index[436] PINMUX_WKUP_DETECTOR_EN_5
+    4'b 0001, // index[437] PINMUX_WKUP_DETECTOR_EN_6
+    4'b 0001, // index[438] PINMUX_WKUP_DETECTOR_EN_7
+    4'b 0001, // index[439] PINMUX_WKUP_DETECTOR_0
+    4'b 0001, // index[440] PINMUX_WKUP_DETECTOR_1
+    4'b 0001, // index[441] PINMUX_WKUP_DETECTOR_2
+    4'b 0001, // index[442] PINMUX_WKUP_DETECTOR_3
+    4'b 0001, // index[443] PINMUX_WKUP_DETECTOR_4
+    4'b 0001, // index[444] PINMUX_WKUP_DETECTOR_5
+    4'b 0001, // index[445] PINMUX_WKUP_DETECTOR_6
+    4'b 0001, // index[446] PINMUX_WKUP_DETECTOR_7
+    4'b 0001, // index[447] PINMUX_WKUP_DETECTOR_CNT_TH_0
+    4'b 0001, // index[448] PINMUX_WKUP_DETECTOR_CNT_TH_1
+    4'b 0001, // index[449] PINMUX_WKUP_DETECTOR_CNT_TH_2
+    4'b 0001, // index[450] PINMUX_WKUP_DETECTOR_CNT_TH_3
+    4'b 0001, // index[451] PINMUX_WKUP_DETECTOR_CNT_TH_4
+    4'b 0001, // index[452] PINMUX_WKUP_DETECTOR_CNT_TH_5
+    4'b 0001, // index[453] PINMUX_WKUP_DETECTOR_CNT_TH_6
+    4'b 0001, // index[454] PINMUX_WKUP_DETECTOR_CNT_TH_7
+    4'b 0001, // index[455] PINMUX_WKUP_DETECTOR_PADSEL_0
+    4'b 0001, // index[456] PINMUX_WKUP_DETECTOR_PADSEL_1
+    4'b 0001, // index[457] PINMUX_WKUP_DETECTOR_PADSEL_2
+    4'b 0001, // index[458] PINMUX_WKUP_DETECTOR_PADSEL_3
+    4'b 0001, // index[459] PINMUX_WKUP_DETECTOR_PADSEL_4
+    4'b 0001, // index[460] PINMUX_WKUP_DETECTOR_PADSEL_5
+    4'b 0001, // index[461] PINMUX_WKUP_DETECTOR_PADSEL_6
+    4'b 0001, // index[462] PINMUX_WKUP_DETECTOR_PADSEL_7
+    4'b 0001  // index[463] PINMUX_WKUP_CAUSE
   };
 endpackage
 
diff --git a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
index cb667a4..8b9514c 100644
--- a/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
+++ b/hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv
@@ -194,6 +194,21 @@
   logic mio_periph_insel_regwen_40_qs;
   logic mio_periph_insel_regwen_40_wd;
   logic mio_periph_insel_regwen_40_we;
+  logic mio_periph_insel_regwen_41_qs;
+  logic mio_periph_insel_regwen_41_wd;
+  logic mio_periph_insel_regwen_41_we;
+  logic mio_periph_insel_regwen_42_qs;
+  logic mio_periph_insel_regwen_42_wd;
+  logic mio_periph_insel_regwen_42_we;
+  logic mio_periph_insel_regwen_43_qs;
+  logic mio_periph_insel_regwen_43_wd;
+  logic mio_periph_insel_regwen_43_we;
+  logic mio_periph_insel_regwen_44_qs;
+  logic mio_periph_insel_regwen_44_wd;
+  logic mio_periph_insel_regwen_44_we;
+  logic mio_periph_insel_regwen_45_qs;
+  logic mio_periph_insel_regwen_45_wd;
+  logic mio_periph_insel_regwen_45_we;
   logic [5:0] mio_periph_insel_0_qs;
   logic [5:0] mio_periph_insel_0_wd;
   logic mio_periph_insel_0_we;
@@ -317,6 +332,21 @@
   logic [5:0] mio_periph_insel_40_qs;
   logic [5:0] mio_periph_insel_40_wd;
   logic mio_periph_insel_40_we;
+  logic [5:0] mio_periph_insel_41_qs;
+  logic [5:0] mio_periph_insel_41_wd;
+  logic mio_periph_insel_41_we;
+  logic [5:0] mio_periph_insel_42_qs;
+  logic [5:0] mio_periph_insel_42_wd;
+  logic mio_periph_insel_42_we;
+  logic [5:0] mio_periph_insel_43_qs;
+  logic [5:0] mio_periph_insel_43_wd;
+  logic mio_periph_insel_43_we;
+  logic [5:0] mio_periph_insel_44_qs;
+  logic [5:0] mio_periph_insel_44_wd;
+  logic mio_periph_insel_44_we;
+  logic [5:0] mio_periph_insel_45_qs;
+  logic [5:0] mio_periph_insel_45_wd;
+  logic mio_periph_insel_45_we;
   logic mio_outsel_regwen_0_qs;
   logic mio_outsel_regwen_0_wd;
   logic mio_outsel_regwen_0_we;
@@ -778,6 +808,24 @@
   logic dio_pad_attr_regwen_14_qs;
   logic dio_pad_attr_regwen_14_wd;
   logic dio_pad_attr_regwen_14_we;
+  logic dio_pad_attr_regwen_15_qs;
+  logic dio_pad_attr_regwen_15_wd;
+  logic dio_pad_attr_regwen_15_we;
+  logic dio_pad_attr_regwen_16_qs;
+  logic dio_pad_attr_regwen_16_wd;
+  logic dio_pad_attr_regwen_16_we;
+  logic dio_pad_attr_regwen_17_qs;
+  logic dio_pad_attr_regwen_17_wd;
+  logic dio_pad_attr_regwen_17_we;
+  logic dio_pad_attr_regwen_18_qs;
+  logic dio_pad_attr_regwen_18_wd;
+  logic dio_pad_attr_regwen_18_we;
+  logic dio_pad_attr_regwen_19_qs;
+  logic dio_pad_attr_regwen_19_wd;
+  logic dio_pad_attr_regwen_19_we;
+  logic dio_pad_attr_regwen_20_qs;
+  logic dio_pad_attr_regwen_20_wd;
+  logic dio_pad_attr_regwen_20_we;
   logic [9:0] dio_pad_attr_0_qs;
   logic [9:0] dio_pad_attr_0_wd;
   logic dio_pad_attr_0_we;
@@ -838,6 +886,30 @@
   logic [9:0] dio_pad_attr_14_wd;
   logic dio_pad_attr_14_we;
   logic dio_pad_attr_14_re;
+  logic [9:0] dio_pad_attr_15_qs;
+  logic [9:0] dio_pad_attr_15_wd;
+  logic dio_pad_attr_15_we;
+  logic dio_pad_attr_15_re;
+  logic [9:0] dio_pad_attr_16_qs;
+  logic [9:0] dio_pad_attr_16_wd;
+  logic dio_pad_attr_16_we;
+  logic dio_pad_attr_16_re;
+  logic [9:0] dio_pad_attr_17_qs;
+  logic [9:0] dio_pad_attr_17_wd;
+  logic dio_pad_attr_17_we;
+  logic dio_pad_attr_17_re;
+  logic [9:0] dio_pad_attr_18_qs;
+  logic [9:0] dio_pad_attr_18_wd;
+  logic dio_pad_attr_18_we;
+  logic dio_pad_attr_18_re;
+  logic [9:0] dio_pad_attr_19_qs;
+  logic [9:0] dio_pad_attr_19_wd;
+  logic dio_pad_attr_19_we;
+  logic dio_pad_attr_19_re;
+  logic [9:0] dio_pad_attr_20_qs;
+  logic [9:0] dio_pad_attr_20_wd;
+  logic dio_pad_attr_20_we;
+  logic dio_pad_attr_20_re;
   logic mio_pad_sleep_status_en_0_qs;
   logic mio_pad_sleep_status_en_0_wd;
   logic mio_pad_sleep_status_en_0_we;
@@ -1267,6 +1339,24 @@
   logic dio_pad_sleep_status_en_14_qs;
   logic dio_pad_sleep_status_en_14_wd;
   logic dio_pad_sleep_status_en_14_we;
+  logic dio_pad_sleep_status_en_15_qs;
+  logic dio_pad_sleep_status_en_15_wd;
+  logic dio_pad_sleep_status_en_15_we;
+  logic dio_pad_sleep_status_en_16_qs;
+  logic dio_pad_sleep_status_en_16_wd;
+  logic dio_pad_sleep_status_en_16_we;
+  logic dio_pad_sleep_status_en_17_qs;
+  logic dio_pad_sleep_status_en_17_wd;
+  logic dio_pad_sleep_status_en_17_we;
+  logic dio_pad_sleep_status_en_18_qs;
+  logic dio_pad_sleep_status_en_18_wd;
+  logic dio_pad_sleep_status_en_18_we;
+  logic dio_pad_sleep_status_en_19_qs;
+  logic dio_pad_sleep_status_en_19_wd;
+  logic dio_pad_sleep_status_en_19_we;
+  logic dio_pad_sleep_status_en_20_qs;
+  logic dio_pad_sleep_status_en_20_wd;
+  logic dio_pad_sleep_status_en_20_we;
   logic dio_pad_sleep_regwen_0_qs;
   logic dio_pad_sleep_regwen_0_wd;
   logic dio_pad_sleep_regwen_0_we;
@@ -1312,6 +1402,24 @@
   logic dio_pad_sleep_regwen_14_qs;
   logic dio_pad_sleep_regwen_14_wd;
   logic dio_pad_sleep_regwen_14_we;
+  logic dio_pad_sleep_regwen_15_qs;
+  logic dio_pad_sleep_regwen_15_wd;
+  logic dio_pad_sleep_regwen_15_we;
+  logic dio_pad_sleep_regwen_16_qs;
+  logic dio_pad_sleep_regwen_16_wd;
+  logic dio_pad_sleep_regwen_16_we;
+  logic dio_pad_sleep_regwen_17_qs;
+  logic dio_pad_sleep_regwen_17_wd;
+  logic dio_pad_sleep_regwen_17_we;
+  logic dio_pad_sleep_regwen_18_qs;
+  logic dio_pad_sleep_regwen_18_wd;
+  logic dio_pad_sleep_regwen_18_we;
+  logic dio_pad_sleep_regwen_19_qs;
+  logic dio_pad_sleep_regwen_19_wd;
+  logic dio_pad_sleep_regwen_19_we;
+  logic dio_pad_sleep_regwen_20_qs;
+  logic dio_pad_sleep_regwen_20_wd;
+  logic dio_pad_sleep_regwen_20_we;
   logic dio_pad_sleep_en_0_qs;
   logic dio_pad_sleep_en_0_wd;
   logic dio_pad_sleep_en_0_we;
@@ -1357,6 +1465,24 @@
   logic dio_pad_sleep_en_14_qs;
   logic dio_pad_sleep_en_14_wd;
   logic dio_pad_sleep_en_14_we;
+  logic dio_pad_sleep_en_15_qs;
+  logic dio_pad_sleep_en_15_wd;
+  logic dio_pad_sleep_en_15_we;
+  logic dio_pad_sleep_en_16_qs;
+  logic dio_pad_sleep_en_16_wd;
+  logic dio_pad_sleep_en_16_we;
+  logic dio_pad_sleep_en_17_qs;
+  logic dio_pad_sleep_en_17_wd;
+  logic dio_pad_sleep_en_17_we;
+  logic dio_pad_sleep_en_18_qs;
+  logic dio_pad_sleep_en_18_wd;
+  logic dio_pad_sleep_en_18_we;
+  logic dio_pad_sleep_en_19_qs;
+  logic dio_pad_sleep_en_19_wd;
+  logic dio_pad_sleep_en_19_we;
+  logic dio_pad_sleep_en_20_qs;
+  logic dio_pad_sleep_en_20_wd;
+  logic dio_pad_sleep_en_20_we;
   logic [1:0] dio_pad_sleep_mode_0_qs;
   logic [1:0] dio_pad_sleep_mode_0_wd;
   logic dio_pad_sleep_mode_0_we;
@@ -1402,6 +1528,24 @@
   logic [1:0] dio_pad_sleep_mode_14_qs;
   logic [1:0] dio_pad_sleep_mode_14_wd;
   logic dio_pad_sleep_mode_14_we;
+  logic [1:0] dio_pad_sleep_mode_15_qs;
+  logic [1:0] dio_pad_sleep_mode_15_wd;
+  logic dio_pad_sleep_mode_15_we;
+  logic [1:0] dio_pad_sleep_mode_16_qs;
+  logic [1:0] dio_pad_sleep_mode_16_wd;
+  logic dio_pad_sleep_mode_16_we;
+  logic [1:0] dio_pad_sleep_mode_17_qs;
+  logic [1:0] dio_pad_sleep_mode_17_wd;
+  logic dio_pad_sleep_mode_17_we;
+  logic [1:0] dio_pad_sleep_mode_18_qs;
+  logic [1:0] dio_pad_sleep_mode_18_wd;
+  logic dio_pad_sleep_mode_18_we;
+  logic [1:0] dio_pad_sleep_mode_19_qs;
+  logic [1:0] dio_pad_sleep_mode_19_wd;
+  logic dio_pad_sleep_mode_19_we;
+  logic [1:0] dio_pad_sleep_mode_20_qs;
+  logic [1:0] dio_pad_sleep_mode_20_wd;
+  logic dio_pad_sleep_mode_20_we;
   logic wkup_detector_regwen_0_qs;
   logic wkup_detector_regwen_0_wd;
   logic wkup_detector_regwen_0_we;
@@ -2712,6 +2856,141 @@
     .qs     (mio_periph_insel_regwen_40_qs)
   );
 
+  // Subregister 41 of Multireg mio_periph_insel_regwen
+  // R[mio_periph_insel_regwen_41]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_periph_insel_regwen_41 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_periph_insel_regwen_41_we),
+    .wd     (mio_periph_insel_regwen_41_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_regwen_41_qs)
+  );
+
+  // Subregister 42 of Multireg mio_periph_insel_regwen
+  // R[mio_periph_insel_regwen_42]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_periph_insel_regwen_42 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_periph_insel_regwen_42_we),
+    .wd     (mio_periph_insel_regwen_42_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_regwen_42_qs)
+  );
+
+  // Subregister 43 of Multireg mio_periph_insel_regwen
+  // R[mio_periph_insel_regwen_43]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_periph_insel_regwen_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_periph_insel_regwen_43_we),
+    .wd     (mio_periph_insel_regwen_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_regwen_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_periph_insel_regwen
+  // R[mio_periph_insel_regwen_44]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_periph_insel_regwen_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_periph_insel_regwen_44_we),
+    .wd     (mio_periph_insel_regwen_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_regwen_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_periph_insel_regwen
+  // R[mio_periph_insel_regwen_45]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_mio_periph_insel_regwen_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (mio_periph_insel_regwen_45_we),
+    .wd     (mio_periph_insel_regwen_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_regwen_45_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_periph_insel
@@ -3821,6 +4100,141 @@
     .qs     (mio_periph_insel_40_qs)
   );
 
+  // Subregister 41 of Multireg mio_periph_insel
+  // R[mio_periph_insel_41]: V(False)
+
+  prim_subreg #(
+    .DW      (6),
+    .SWACCESS("RW"),
+    .RESVAL  (6'h0)
+  ) u_mio_periph_insel_41 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_periph_insel_41_we & mio_periph_insel_regwen_41_qs),
+    .wd     (mio_periph_insel_41_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_periph_insel[41].q ),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_41_qs)
+  );
+
+  // Subregister 42 of Multireg mio_periph_insel
+  // R[mio_periph_insel_42]: V(False)
+
+  prim_subreg #(
+    .DW      (6),
+    .SWACCESS("RW"),
+    .RESVAL  (6'h0)
+  ) u_mio_periph_insel_42 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_periph_insel_42_we & mio_periph_insel_regwen_42_qs),
+    .wd     (mio_periph_insel_42_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_periph_insel[42].q ),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_42_qs)
+  );
+
+  // Subregister 43 of Multireg mio_periph_insel
+  // R[mio_periph_insel_43]: V(False)
+
+  prim_subreg #(
+    .DW      (6),
+    .SWACCESS("RW"),
+    .RESVAL  (6'h0)
+  ) u_mio_periph_insel_43 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_periph_insel_43_we & mio_periph_insel_regwen_43_qs),
+    .wd     (mio_periph_insel_43_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_periph_insel[43].q ),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_43_qs)
+  );
+
+  // Subregister 44 of Multireg mio_periph_insel
+  // R[mio_periph_insel_44]: V(False)
+
+  prim_subreg #(
+    .DW      (6),
+    .SWACCESS("RW"),
+    .RESVAL  (6'h0)
+  ) u_mio_periph_insel_44 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_periph_insel_44_we & mio_periph_insel_regwen_44_qs),
+    .wd     (mio_periph_insel_44_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_periph_insel[44].q ),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_44_qs)
+  );
+
+  // Subregister 45 of Multireg mio_periph_insel
+  // R[mio_periph_insel_45]: V(False)
+
+  prim_subreg #(
+    .DW      (6),
+    .SWACCESS("RW"),
+    .RESVAL  (6'h0)
+  ) u_mio_periph_insel_45 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (mio_periph_insel_45_we & mio_periph_insel_regwen_45_qs),
+    .wd     (mio_periph_insel_45_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.mio_periph_insel[45].q ),
+
+    // to register interface (read)
+    .qs     (mio_periph_insel_45_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_outsel_regwen
@@ -7372,6 +7786,168 @@
     .qs     (dio_pad_attr_regwen_14_qs)
   );
 
+  // Subregister 15 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_15]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_15 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_15_we),
+    .wd     (dio_pad_attr_regwen_15_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_15_qs)
+  );
+
+  // Subregister 16 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_16]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_16 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_16_we),
+    .wd     (dio_pad_attr_regwen_16_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_16_qs)
+  );
+
+  // Subregister 17 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_17]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_17 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_17_we),
+    .wd     (dio_pad_attr_regwen_17_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_17_qs)
+  );
+
+  // Subregister 18 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_18]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_18 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_18_we),
+    .wd     (dio_pad_attr_regwen_18_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_18_qs)
+  );
+
+  // Subregister 19 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_19]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_19 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_19_we),
+    .wd     (dio_pad_attr_regwen_19_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_19_qs)
+  );
+
+  // Subregister 20 of Multireg dio_pad_attr_regwen
+  // R[dio_pad_attr_regwen_20]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_attr_regwen_20 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_attr_regwen_20_we),
+    .wd     (dio_pad_attr_regwen_20_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_attr_regwen_20_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_attr
@@ -7629,6 +8205,108 @@
     .qs     (dio_pad_attr_14_qs)
   );
 
+  // Subregister 15 of Multireg dio_pad_attr
+  // R[dio_pad_attr_15]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_15 (
+    .re     (dio_pad_attr_15_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_15_we & dio_pad_attr_regwen_15_qs),
+    .wd     (dio_pad_attr_15_wd),
+    .d      (hw2reg.dio_pad_attr[15].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[15].qe),
+    .q      (reg2hw.dio_pad_attr[15].q ),
+    .qs     (dio_pad_attr_15_qs)
+  );
+
+  // Subregister 16 of Multireg dio_pad_attr
+  // R[dio_pad_attr_16]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_16 (
+    .re     (dio_pad_attr_16_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_16_we & dio_pad_attr_regwen_16_qs),
+    .wd     (dio_pad_attr_16_wd),
+    .d      (hw2reg.dio_pad_attr[16].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[16].qe),
+    .q      (reg2hw.dio_pad_attr[16].q ),
+    .qs     (dio_pad_attr_16_qs)
+  );
+
+  // Subregister 17 of Multireg dio_pad_attr
+  // R[dio_pad_attr_17]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_17 (
+    .re     (dio_pad_attr_17_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_17_we & dio_pad_attr_regwen_17_qs),
+    .wd     (dio_pad_attr_17_wd),
+    .d      (hw2reg.dio_pad_attr[17].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[17].qe),
+    .q      (reg2hw.dio_pad_attr[17].q ),
+    .qs     (dio_pad_attr_17_qs)
+  );
+
+  // Subregister 18 of Multireg dio_pad_attr
+  // R[dio_pad_attr_18]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_18 (
+    .re     (dio_pad_attr_18_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_18_we & dio_pad_attr_regwen_18_qs),
+    .wd     (dio_pad_attr_18_wd),
+    .d      (hw2reg.dio_pad_attr[18].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[18].qe),
+    .q      (reg2hw.dio_pad_attr[18].q ),
+    .qs     (dio_pad_attr_18_qs)
+  );
+
+  // Subregister 19 of Multireg dio_pad_attr
+  // R[dio_pad_attr_19]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_19 (
+    .re     (dio_pad_attr_19_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_19_we & dio_pad_attr_regwen_19_qs),
+    .wd     (dio_pad_attr_19_wd),
+    .d      (hw2reg.dio_pad_attr[19].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[19].qe),
+    .q      (reg2hw.dio_pad_attr[19].q ),
+    .qs     (dio_pad_attr_19_qs)
+  );
+
+  // Subregister 20 of Multireg dio_pad_attr
+  // R[dio_pad_attr_20]: V(True)
+
+  prim_subreg_ext #(
+    .DW    (10)
+  ) u_dio_pad_attr_20 (
+    .re     (dio_pad_attr_20_re),
+    // qualified with register enable
+    .we     (dio_pad_attr_20_we & dio_pad_attr_regwen_20_qs),
+    .wd     (dio_pad_attr_20_wd),
+    .d      (hw2reg.dio_pad_attr[20].d),
+    .qre    (),
+    .qe     (reg2hw.dio_pad_attr[20].qe),
+    .q      (reg2hw.dio_pad_attr[20].q ),
+    .qs     (dio_pad_attr_20_qs)
+  );
+
 
 
   // Subregister 0 of Multireg mio_pad_sleep_status
@@ -11459,6 +12137,162 @@
   );
 
 
+  // F[en_15]: 15:15
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_15 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_15_we),
+    .wd     (dio_pad_sleep_status_en_15_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[15].de),
+    .d      (hw2reg.dio_pad_sleep_status[15].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[15].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_15_qs)
+  );
+
+
+  // F[en_16]: 16:16
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_16 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_16_we),
+    .wd     (dio_pad_sleep_status_en_16_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[16].de),
+    .d      (hw2reg.dio_pad_sleep_status[16].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[16].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_16_qs)
+  );
+
+
+  // F[en_17]: 17:17
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_17 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_17_we),
+    .wd     (dio_pad_sleep_status_en_17_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[17].de),
+    .d      (hw2reg.dio_pad_sleep_status[17].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[17].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_17_qs)
+  );
+
+
+  // F[en_18]: 18:18
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_18 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_18_we),
+    .wd     (dio_pad_sleep_status_en_18_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[18].de),
+    .d      (hw2reg.dio_pad_sleep_status[18].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[18].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_18_qs)
+  );
+
+
+  // F[en_19]: 19:19
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_19 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_19_we),
+    .wd     (dio_pad_sleep_status_en_19_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[19].de),
+    .d      (hw2reg.dio_pad_sleep_status[19].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[19].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_19_qs)
+  );
+
+
+  // F[en_20]: 20:20
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_status_en_20 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_status_en_20_we),
+    .wd     (dio_pad_sleep_status_en_20_wd),
+
+    // from internal hardware
+    .de     (hw2reg.dio_pad_sleep_status[20].de),
+    .d      (hw2reg.dio_pad_sleep_status[20].d ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_status[20].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_status_en_20_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_regwen
@@ -11866,6 +12700,168 @@
     .qs     (dio_pad_sleep_regwen_14_qs)
   );
 
+  // Subregister 15 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_15]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_15 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_15_we),
+    .wd     (dio_pad_sleep_regwen_15_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_15_qs)
+  );
+
+  // Subregister 16 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_16]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_16 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_16_we),
+    .wd     (dio_pad_sleep_regwen_16_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_16_qs)
+  );
+
+  // Subregister 17 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_17]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_17 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_17_we),
+    .wd     (dio_pad_sleep_regwen_17_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_17_qs)
+  );
+
+  // Subregister 18 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_18]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_18 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_18_we),
+    .wd     (dio_pad_sleep_regwen_18_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_18_qs)
+  );
+
+  // Subregister 19 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_19]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_19 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_19_we),
+    .wd     (dio_pad_sleep_regwen_19_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_19_qs)
+  );
+
+  // Subregister 20 of Multireg dio_pad_sleep_regwen
+  // R[dio_pad_sleep_regwen_20]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_dio_pad_sleep_regwen_20 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (dio_pad_sleep_regwen_20_we),
+    .wd     (dio_pad_sleep_regwen_20_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_regwen_20_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_en
@@ -12273,6 +13269,168 @@
     .qs     (dio_pad_sleep_en_14_qs)
   );
 
+  // Subregister 15 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_15]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_15 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_15_we & dio_pad_sleep_regwen_15_qs),
+    .wd     (dio_pad_sleep_en_15_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[15].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_15_qs)
+  );
+
+  // Subregister 16 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_16]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_16 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_16_we & dio_pad_sleep_regwen_16_qs),
+    .wd     (dio_pad_sleep_en_16_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[16].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_16_qs)
+  );
+
+  // Subregister 17 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_17]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_17 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_17_we & dio_pad_sleep_regwen_17_qs),
+    .wd     (dio_pad_sleep_en_17_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[17].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_17_qs)
+  );
+
+  // Subregister 18 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_18]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_18 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_18_we & dio_pad_sleep_regwen_18_qs),
+    .wd     (dio_pad_sleep_en_18_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[18].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_18_qs)
+  );
+
+  // Subregister 19 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_19]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_19 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_19_we & dio_pad_sleep_regwen_19_qs),
+    .wd     (dio_pad_sleep_en_19_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[19].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_19_qs)
+  );
+
+  // Subregister 20 of Multireg dio_pad_sleep_en
+  // R[dio_pad_sleep_en_20]: V(False)
+
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("RW"),
+    .RESVAL  (1'h0)
+  ) u_dio_pad_sleep_en_20 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_en_20_we & dio_pad_sleep_regwen_20_qs),
+    .wd     (dio_pad_sleep_en_20_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_en[20].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_en_20_qs)
+  );
+
 
 
   // Subregister 0 of Multireg dio_pad_sleep_mode
@@ -12680,6 +13838,168 @@
     .qs     (dio_pad_sleep_mode_14_qs)
   );
 
+  // Subregister 15 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_15]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_15 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_15_we & dio_pad_sleep_regwen_15_qs),
+    .wd     (dio_pad_sleep_mode_15_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[15].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_15_qs)
+  );
+
+  // Subregister 16 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_16]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_16 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_16_we & dio_pad_sleep_regwen_16_qs),
+    .wd     (dio_pad_sleep_mode_16_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[16].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_16_qs)
+  );
+
+  // Subregister 17 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_17]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_17 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_17_we & dio_pad_sleep_regwen_17_qs),
+    .wd     (dio_pad_sleep_mode_17_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[17].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_17_qs)
+  );
+
+  // Subregister 18 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_18]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_18 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_18_we & dio_pad_sleep_regwen_18_qs),
+    .wd     (dio_pad_sleep_mode_18_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[18].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_18_qs)
+  );
+
+  // Subregister 19 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_19]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_19 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_19_we & dio_pad_sleep_regwen_19_qs),
+    .wd     (dio_pad_sleep_mode_19_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[19].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_19_qs)
+  );
+
+  // Subregister 20 of Multireg dio_pad_sleep_mode
+  // R[dio_pad_sleep_mode_20]: V(False)
+
+  prim_subreg #(
+    .DW      (2),
+    .SWACCESS("RW"),
+    .RESVAL  (2'h2)
+  ) u_dio_pad_sleep_mode_20 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface (qualified with register enable)
+    .we     (dio_pad_sleep_mode_20_we & dio_pad_sleep_regwen_20_qs),
+    .wd     (dio_pad_sleep_mode_20_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.dio_pad_sleep_mode[20].q ),
+
+    // to register interface (read)
+    .qs     (dio_pad_sleep_mode_20_qs)
+  );
+
 
 
   // Subregister 0 of Multireg wkup_detector_regwen
@@ -14330,7 +15650,7 @@
 
 
 
-  logic [423:0] addr_hit;
+  logic [463:0] addr_hit;
   always_comb begin
     addr_hit = '0;
     addr_hit[  0] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET);
@@ -14374,389 +15694,429 @@
     addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_38_OFFSET);
     addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_39_OFFSET);
     addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_40_OFFSET);
-    addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
-    addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
-    addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
-    addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
-    addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
-    addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
-    addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
-    addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
-    addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
-    addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
-    addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
-    addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
-    addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
-    addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
-    addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
-    addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
-    addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
-    addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
-    addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
-    addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
-    addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
-    addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
-    addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
-    addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
-    addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
-    addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
-    addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
-    addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
-    addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
-    addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
-    addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
-    addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
-    addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
-    addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
-    addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
-    addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
-    addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
-    addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
-    addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
-    addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
-    addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
-    addr_hit[ 82] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
-    addr_hit[ 83] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
-    addr_hit[ 84] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
-    addr_hit[ 85] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
-    addr_hit[ 86] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
-    addr_hit[ 87] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
-    addr_hit[ 88] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
-    addr_hit[ 89] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
-    addr_hit[ 90] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
-    addr_hit[ 91] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
-    addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
-    addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
-    addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
-    addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
-    addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
-    addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
-    addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
-    addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
-    addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
-    addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
-    addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
-    addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
-    addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
-    addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
-    addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
-    addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
-    addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
-    addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
-    addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
-    addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
-    addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
-    addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
-    addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
-    addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
-    addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
-    addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
-    addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
-    addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
-    addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
-    addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
-    addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
-    addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
-    addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
-    addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
-    addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
-    addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
-    addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
-    addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
-    addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
-    addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
-    addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
-    addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
-    addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
-    addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
-    addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
-    addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
-    addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
-    addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
-    addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
-    addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
-    addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
-    addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
-    addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
-    addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
-    addr_hit[146] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
-    addr_hit[147] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
-    addr_hit[148] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
-    addr_hit[149] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
-    addr_hit[150] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
-    addr_hit[151] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
-    addr_hit[152] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
-    addr_hit[153] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
-    addr_hit[154] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
-    addr_hit[155] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
-    addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
-    addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
-    addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
-    addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
-    addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
-    addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
-    addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
-    addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
-    addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
-    addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
-    addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
-    addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
-    addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
-    addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
-    addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
-    addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
-    addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
-    addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
-    addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
-    addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
-    addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
-    addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
-    addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
-    addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
-    addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
-    addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
-    addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
-    addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
-    addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
-    addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
-    addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
-    addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
-    addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
-    addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
-    addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
-    addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
-    addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
-    addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
-    addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
-    addr_hit[195] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
-    addr_hit[196] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
-    addr_hit[197] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
-    addr_hit[198] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
-    addr_hit[199] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
-    addr_hit[200] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
-    addr_hit[201] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
-    addr_hit[202] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
-    addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
-    addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
-    addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
-    addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
-    addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
-    addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
-    addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
-    addr_hit[210] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
-    addr_hit[211] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
-    addr_hit[212] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
-    addr_hit[213] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
-    addr_hit[214] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
-    addr_hit[215] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
-    addr_hit[216] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
-    addr_hit[217] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
-    addr_hit[218] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
-    addr_hit[219] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
-    addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
-    addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
-    addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
-    addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
-    addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
-    addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
-    addr_hit[226] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
-    addr_hit[227] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
-    addr_hit[228] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
-    addr_hit[229] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
-    addr_hit[230] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
-    addr_hit[231] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
-    addr_hit[232] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
-    addr_hit[233] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
-    addr_hit[234] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
-    addr_hit[235] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
-    addr_hit[236] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
-    addr_hit[237] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
-    addr_hit[238] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
-    addr_hit[239] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
-    addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET);
-    addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
-    addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
-    addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
-    addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
-    addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
-    addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
-    addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
-    addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
-    addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
-    addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
-    addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
-    addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
-    addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
-    addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
-    addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
-    addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
-    addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
-    addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
-    addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
-    addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
-    addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
-    addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
-    addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
-    addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
-    addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
-    addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
-    addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
-    addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
-    addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
-    addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
-    addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
-    addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
-    addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
-    addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
-    addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
-    addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
-    addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
-    addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
-    addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
-    addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
-    addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
-    addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
-    addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
-    addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
-    addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
-    addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
-    addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
-    addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
-    addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
-    addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
-    addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
-    addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
-    addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
-    addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
-    addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
-    addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
-    addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
-    addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
-    addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
-    addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
-    addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
-    addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
-    addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
-    addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
-    addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
-    addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
-    addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
-    addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
-    addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
-    addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
-    addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
-    addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
-    addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
-    addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
-    addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
-    addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
-    addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
-    addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
-    addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
-    addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
-    addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
-    addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
-    addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
-    addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
-    addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
-    addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
-    addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
-    addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
-    addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
-    addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
-    addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
-    addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
-    addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
-    addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
-    addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
-    addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
-    addr_hit[337] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
-    addr_hit[338] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
-    addr_hit[339] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
-    addr_hit[340] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
-    addr_hit[341] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
-    addr_hit[342] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
-    addr_hit[343] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
-    addr_hit[344] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
-    addr_hit[345] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
-    addr_hit[346] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
-    addr_hit[347] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
-    addr_hit[348] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
-    addr_hit[349] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
-    addr_hit[350] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
-    addr_hit[351] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
-    addr_hit[352] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
-    addr_hit[353] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
-    addr_hit[354] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
-    addr_hit[355] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
-    addr_hit[356] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
-    addr_hit[357] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
-    addr_hit[358] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
-    addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
-    addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
-    addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
-    addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
-    addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
-    addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
-    addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
-    addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
-    addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
-    addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
-    addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
-    addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
-    addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
-    addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
-    addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
-    addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
-    addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
-    addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
-    addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
-    addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
-    addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
-    addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
-    addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
-    addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
-    addr_hit[383] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
-    addr_hit[384] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
-    addr_hit[385] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
-    addr_hit[386] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
-    addr_hit[387] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
-    addr_hit[388] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
-    addr_hit[389] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
-    addr_hit[390] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
-    addr_hit[391] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
-    addr_hit[392] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
-    addr_hit[393] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
-    addr_hit[394] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
-    addr_hit[395] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
-    addr_hit[396] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
-    addr_hit[397] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
-    addr_hit[398] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
-    addr_hit[399] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
-    addr_hit[400] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
-    addr_hit[401] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
-    addr_hit[402] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
-    addr_hit[403] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
-    addr_hit[404] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
-    addr_hit[405] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
-    addr_hit[406] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
-    addr_hit[407] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
-    addr_hit[408] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
-    addr_hit[409] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
-    addr_hit[410] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
-    addr_hit[411] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
-    addr_hit[412] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
-    addr_hit[413] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
-    addr_hit[414] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
-    addr_hit[415] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
-    addr_hit[416] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
-    addr_hit[417] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
-    addr_hit[418] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
-    addr_hit[419] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
-    addr_hit[420] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
-    addr_hit[421] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
-    addr_hit[422] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
-    addr_hit[423] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
+    addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_41_OFFSET);
+    addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_42_OFFSET);
+    addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_43_OFFSET);
+    addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_44_OFFSET);
+    addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_45_OFFSET);
+    addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET);
+    addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET);
+    addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET);
+    addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET);
+    addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET);
+    addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET);
+    addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET);
+    addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET);
+    addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET);
+    addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET);
+    addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET);
+    addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET);
+    addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET);
+    addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET);
+    addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET);
+    addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET);
+    addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET);
+    addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET);
+    addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET);
+    addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET);
+    addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET);
+    addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET);
+    addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET);
+    addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET);
+    addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET);
+    addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET);
+    addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET);
+    addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET);
+    addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET);
+    addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET);
+    addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET);
+    addr_hit[ 77] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET);
+    addr_hit[ 78] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET);
+    addr_hit[ 79] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET);
+    addr_hit[ 80] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET);
+    addr_hit[ 81] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET);
+    addr_hit[ 82] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET);
+    addr_hit[ 83] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET);
+    addr_hit[ 84] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_38_OFFSET);
+    addr_hit[ 85] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_39_OFFSET);
+    addr_hit[ 86] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_40_OFFSET);
+    addr_hit[ 87] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_41_OFFSET);
+    addr_hit[ 88] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_42_OFFSET);
+    addr_hit[ 89] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_43_OFFSET);
+    addr_hit[ 90] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_44_OFFSET);
+    addr_hit[ 91] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_45_OFFSET);
+    addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET);
+    addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET);
+    addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET);
+    addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET);
+    addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET);
+    addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET);
+    addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET);
+    addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET);
+    addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET);
+    addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET);
+    addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET);
+    addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET);
+    addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET);
+    addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET);
+    addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET);
+    addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET);
+    addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET);
+    addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET);
+    addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET);
+    addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET);
+    addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET);
+    addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET);
+    addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET);
+    addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET);
+    addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET);
+    addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET);
+    addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET);
+    addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET);
+    addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET);
+    addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET);
+    addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET);
+    addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET);
+    addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET);
+    addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET);
+    addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET);
+    addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET);
+    addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET);
+    addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET);
+    addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET);
+    addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET);
+    addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET);
+    addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET);
+    addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET);
+    addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET);
+    addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET);
+    addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET);
+    addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET);
+    addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET);
+    addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET);
+    addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET);
+    addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET);
+    addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET);
+    addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET);
+    addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET);
+    addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET);
+    addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET);
+    addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET);
+    addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET);
+    addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET);
+    addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET);
+    addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET);
+    addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET);
+    addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET);
+    addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET);
+    addr_hit[156] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET);
+    addr_hit[157] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET);
+    addr_hit[158] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET);
+    addr_hit[159] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET);
+    addr_hit[160] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET);
+    addr_hit[161] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET);
+    addr_hit[162] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET);
+    addr_hit[163] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET);
+    addr_hit[164] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET);
+    addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET);
+    addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET);
+    addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET);
+    addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET);
+    addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET);
+    addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET);
+    addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET);
+    addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET);
+    addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET);
+    addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET);
+    addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET);
+    addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET);
+    addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET);
+    addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET);
+    addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET);
+    addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET);
+    addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET);
+    addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET);
+    addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET);
+    addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET);
+    addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET);
+    addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET);
+    addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET);
+    addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET);
+    addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET);
+    addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET);
+    addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET);
+    addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET);
+    addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET);
+    addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET);
+    addr_hit[195] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET);
+    addr_hit[196] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET);
+    addr_hit[197] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET);
+    addr_hit[198] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET);
+    addr_hit[199] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET);
+    addr_hit[200] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET);
+    addr_hit[201] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET);
+    addr_hit[202] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET);
+    addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET);
+    addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET);
+    addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET);
+    addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET);
+    addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET);
+    addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET);
+    addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET);
+    addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET);
+    addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET);
+    addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET);
+    addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET);
+    addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET);
+    addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET);
+    addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET);
+    addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET);
+    addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET);
+    addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET);
+    addr_hit[220] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET);
+    addr_hit[221] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET);
+    addr_hit[222] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET);
+    addr_hit[223] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET);
+    addr_hit[224] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET);
+    addr_hit[225] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET);
+    addr_hit[226] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET);
+    addr_hit[227] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET);
+    addr_hit[228] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET);
+    addr_hit[229] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET);
+    addr_hit[230] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET);
+    addr_hit[231] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET);
+    addr_hit[232] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET);
+    addr_hit[233] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET);
+    addr_hit[234] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_14_OFFSET);
+    addr_hit[235] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_15_OFFSET);
+    addr_hit[236] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_16_OFFSET);
+    addr_hit[237] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_17_OFFSET);
+    addr_hit[238] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_18_OFFSET);
+    addr_hit[239] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_19_OFFSET);
+    addr_hit[240] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_20_OFFSET);
+    addr_hit[241] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET);
+    addr_hit[242] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET);
+    addr_hit[243] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET);
+    addr_hit[244] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET);
+    addr_hit[245] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET);
+    addr_hit[246] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET);
+    addr_hit[247] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET);
+    addr_hit[248] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET);
+    addr_hit[249] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET);
+    addr_hit[250] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET);
+    addr_hit[251] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET);
+    addr_hit[252] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET);
+    addr_hit[253] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET);
+    addr_hit[254] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET);
+    addr_hit[255] = (reg_addr == PINMUX_DIO_PAD_ATTR_14_OFFSET);
+    addr_hit[256] = (reg_addr == PINMUX_DIO_PAD_ATTR_15_OFFSET);
+    addr_hit[257] = (reg_addr == PINMUX_DIO_PAD_ATTR_16_OFFSET);
+    addr_hit[258] = (reg_addr == PINMUX_DIO_PAD_ATTR_17_OFFSET);
+    addr_hit[259] = (reg_addr == PINMUX_DIO_PAD_ATTR_18_OFFSET);
+    addr_hit[260] = (reg_addr == PINMUX_DIO_PAD_ATTR_19_OFFSET);
+    addr_hit[261] = (reg_addr == PINMUX_DIO_PAD_ATTR_20_OFFSET);
+    addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_OFFSET);
+    addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET);
+    addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET);
+    addr_hit[265] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET);
+    addr_hit[266] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET);
+    addr_hit[267] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET);
+    addr_hit[268] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET);
+    addr_hit[269] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET);
+    addr_hit[270] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET);
+    addr_hit[271] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET);
+    addr_hit[272] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET);
+    addr_hit[273] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET);
+    addr_hit[274] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET);
+    addr_hit[275] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET);
+    addr_hit[276] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET);
+    addr_hit[277] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET);
+    addr_hit[278] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET);
+    addr_hit[279] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET);
+    addr_hit[280] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET);
+    addr_hit[281] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET);
+    addr_hit[282] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET);
+    addr_hit[283] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET);
+    addr_hit[284] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET);
+    addr_hit[285] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET);
+    addr_hit[286] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET);
+    addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET);
+    addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET);
+    addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET);
+    addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET);
+    addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET);
+    addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET);
+    addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET);
+    addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET);
+    addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET);
+    addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET);
+    addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET);
+    addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET);
+    addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET);
+    addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET);
+    addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET);
+    addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET);
+    addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET);
+    addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET);
+    addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET);
+    addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET);
+    addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET);
+    addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET);
+    addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET);
+    addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET);
+    addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET);
+    addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET);
+    addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET);
+    addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET);
+    addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET);
+    addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET);
+    addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET);
+    addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET);
+    addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET);
+    addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET);
+    addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET);
+    addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET);
+    addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET);
+    addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET);
+    addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET);
+    addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET);
+    addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET);
+    addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET);
+    addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET);
+    addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET);
+    addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET);
+    addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET);
+    addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET);
+    addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET);
+    addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET);
+    addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET);
+    addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET);
+    addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET);
+    addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET);
+    addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET);
+    addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET);
+    addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET);
+    addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET);
+    addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET);
+    addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET);
+    addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET);
+    addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET);
+    addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET);
+    addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET);
+    addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET);
+    addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET);
+    addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET);
+    addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET);
+    addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET);
+    addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET);
+    addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET);
+    addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET);
+    addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET);
+    addr_hit[359] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET);
+    addr_hit[360] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET);
+    addr_hit[361] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET);
+    addr_hit[362] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET);
+    addr_hit[363] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET);
+    addr_hit[364] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET);
+    addr_hit[365] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET);
+    addr_hit[366] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET);
+    addr_hit[367] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET);
+    addr_hit[368] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET);
+    addr_hit[369] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET);
+    addr_hit[370] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET);
+    addr_hit[371] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET);
+    addr_hit[372] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET);
+    addr_hit[373] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET);
+    addr_hit[374] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_14_OFFSET);
+    addr_hit[375] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_15_OFFSET);
+    addr_hit[376] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_16_OFFSET);
+    addr_hit[377] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_17_OFFSET);
+    addr_hit[378] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_18_OFFSET);
+    addr_hit[379] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_19_OFFSET);
+    addr_hit[380] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_20_OFFSET);
+    addr_hit[381] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET);
+    addr_hit[382] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET);
+    addr_hit[383] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET);
+    addr_hit[384] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET);
+    addr_hit[385] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET);
+    addr_hit[386] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET);
+    addr_hit[387] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET);
+    addr_hit[388] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET);
+    addr_hit[389] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET);
+    addr_hit[390] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET);
+    addr_hit[391] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET);
+    addr_hit[392] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET);
+    addr_hit[393] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET);
+    addr_hit[394] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET);
+    addr_hit[395] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_14_OFFSET);
+    addr_hit[396] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_15_OFFSET);
+    addr_hit[397] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_16_OFFSET);
+    addr_hit[398] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_17_OFFSET);
+    addr_hit[399] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_18_OFFSET);
+    addr_hit[400] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_19_OFFSET);
+    addr_hit[401] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_20_OFFSET);
+    addr_hit[402] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET);
+    addr_hit[403] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET);
+    addr_hit[404] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET);
+    addr_hit[405] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET);
+    addr_hit[406] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET);
+    addr_hit[407] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET);
+    addr_hit[408] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET);
+    addr_hit[409] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET);
+    addr_hit[410] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET);
+    addr_hit[411] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET);
+    addr_hit[412] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET);
+    addr_hit[413] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET);
+    addr_hit[414] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET);
+    addr_hit[415] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET);
+    addr_hit[416] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_14_OFFSET);
+    addr_hit[417] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_15_OFFSET);
+    addr_hit[418] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_16_OFFSET);
+    addr_hit[419] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_17_OFFSET);
+    addr_hit[420] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_18_OFFSET);
+    addr_hit[421] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_19_OFFSET);
+    addr_hit[422] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_20_OFFSET);
+    addr_hit[423] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET);
+    addr_hit[424] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET);
+    addr_hit[425] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET);
+    addr_hit[426] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET);
+    addr_hit[427] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET);
+    addr_hit[428] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET);
+    addr_hit[429] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET);
+    addr_hit[430] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET);
+    addr_hit[431] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET);
+    addr_hit[432] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET);
+    addr_hit[433] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET);
+    addr_hit[434] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET);
+    addr_hit[435] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET);
+    addr_hit[436] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET);
+    addr_hit[437] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET);
+    addr_hit[438] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET);
+    addr_hit[439] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET);
+    addr_hit[440] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET);
+    addr_hit[441] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET);
+    addr_hit[442] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET);
+    addr_hit[443] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET);
+    addr_hit[444] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET);
+    addr_hit[445] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET);
+    addr_hit[446] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET);
+    addr_hit[447] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET);
+    addr_hit[448] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET);
+    addr_hit[449] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET);
+    addr_hit[450] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET);
+    addr_hit[451] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET);
+    addr_hit[452] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET);
+    addr_hit[453] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET);
+    addr_hit[454] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET);
+    addr_hit[455] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET);
+    addr_hit[456] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET);
+    addr_hit[457] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET);
+    addr_hit[458] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET);
+    addr_hit[459] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET);
+    addr_hit[460] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET);
+    addr_hit[461] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET);
+    addr_hit[462] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET);
+    addr_hit[463] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
   end
 
   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
@@ -15188,6 +16548,46 @@
     if (addr_hit[421] && reg_we && (PINMUX_PERMIT[421] != (PINMUX_PERMIT[421] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[422] && reg_we && (PINMUX_PERMIT[422] != (PINMUX_PERMIT[422] & reg_be))) wr_err = 1'b1 ;
     if (addr_hit[423] && reg_we && (PINMUX_PERMIT[423] != (PINMUX_PERMIT[423] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[424] && reg_we && (PINMUX_PERMIT[424] != (PINMUX_PERMIT[424] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[425] && reg_we && (PINMUX_PERMIT[425] != (PINMUX_PERMIT[425] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[426] && reg_we && (PINMUX_PERMIT[426] != (PINMUX_PERMIT[426] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[427] && reg_we && (PINMUX_PERMIT[427] != (PINMUX_PERMIT[427] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[428] && reg_we && (PINMUX_PERMIT[428] != (PINMUX_PERMIT[428] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[429] && reg_we && (PINMUX_PERMIT[429] != (PINMUX_PERMIT[429] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[430] && reg_we && (PINMUX_PERMIT[430] != (PINMUX_PERMIT[430] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[431] && reg_we && (PINMUX_PERMIT[431] != (PINMUX_PERMIT[431] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[432] && reg_we && (PINMUX_PERMIT[432] != (PINMUX_PERMIT[432] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[433] && reg_we && (PINMUX_PERMIT[433] != (PINMUX_PERMIT[433] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[434] && reg_we && (PINMUX_PERMIT[434] != (PINMUX_PERMIT[434] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[435] && reg_we && (PINMUX_PERMIT[435] != (PINMUX_PERMIT[435] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[436] && reg_we && (PINMUX_PERMIT[436] != (PINMUX_PERMIT[436] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[437] && reg_we && (PINMUX_PERMIT[437] != (PINMUX_PERMIT[437] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[438] && reg_we && (PINMUX_PERMIT[438] != (PINMUX_PERMIT[438] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[439] && reg_we && (PINMUX_PERMIT[439] != (PINMUX_PERMIT[439] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[440] && reg_we && (PINMUX_PERMIT[440] != (PINMUX_PERMIT[440] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[441] && reg_we && (PINMUX_PERMIT[441] != (PINMUX_PERMIT[441] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[442] && reg_we && (PINMUX_PERMIT[442] != (PINMUX_PERMIT[442] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[443] && reg_we && (PINMUX_PERMIT[443] != (PINMUX_PERMIT[443] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[444] && reg_we && (PINMUX_PERMIT[444] != (PINMUX_PERMIT[444] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[445] && reg_we && (PINMUX_PERMIT[445] != (PINMUX_PERMIT[445] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[446] && reg_we && (PINMUX_PERMIT[446] != (PINMUX_PERMIT[446] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[447] && reg_we && (PINMUX_PERMIT[447] != (PINMUX_PERMIT[447] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[448] && reg_we && (PINMUX_PERMIT[448] != (PINMUX_PERMIT[448] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[449] && reg_we && (PINMUX_PERMIT[449] != (PINMUX_PERMIT[449] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[450] && reg_we && (PINMUX_PERMIT[450] != (PINMUX_PERMIT[450] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[451] && reg_we && (PINMUX_PERMIT[451] != (PINMUX_PERMIT[451] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[452] && reg_we && (PINMUX_PERMIT[452] != (PINMUX_PERMIT[452] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[453] && reg_we && (PINMUX_PERMIT[453] != (PINMUX_PERMIT[453] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[454] && reg_we && (PINMUX_PERMIT[454] != (PINMUX_PERMIT[454] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[455] && reg_we && (PINMUX_PERMIT[455] != (PINMUX_PERMIT[455] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[456] && reg_we && (PINMUX_PERMIT[456] != (PINMUX_PERMIT[456] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[457] && reg_we && (PINMUX_PERMIT[457] != (PINMUX_PERMIT[457] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[458] && reg_we && (PINMUX_PERMIT[458] != (PINMUX_PERMIT[458] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[459] && reg_we && (PINMUX_PERMIT[459] != (PINMUX_PERMIT[459] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[460] && reg_we && (PINMUX_PERMIT[460] != (PINMUX_PERMIT[460] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[461] && reg_we && (PINMUX_PERMIT[461] != (PINMUX_PERMIT[461] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[462] && reg_we && (PINMUX_PERMIT[462] != (PINMUX_PERMIT[462] & reg_be))) wr_err = 1'b1 ;
+    if (addr_hit[463] && reg_we && (PINMUX_PERMIT[463] != (PINMUX_PERMIT[463] & reg_be))) wr_err = 1'b1 ;
   end
 
   assign mio_periph_insel_regwen_0_we = addr_hit[0] & reg_we & ~wr_err;
@@ -15313,1413 +16713,1557 @@
   assign mio_periph_insel_regwen_40_we = addr_hit[40] & reg_we & ~wr_err;
   assign mio_periph_insel_regwen_40_wd = reg_wdata[0];
 
-  assign mio_periph_insel_0_we = addr_hit[41] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_41_we = addr_hit[41] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_41_wd = reg_wdata[0];
+
+  assign mio_periph_insel_regwen_42_we = addr_hit[42] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_42_wd = reg_wdata[0];
+
+  assign mio_periph_insel_regwen_43_we = addr_hit[43] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_43_wd = reg_wdata[0];
+
+  assign mio_periph_insel_regwen_44_we = addr_hit[44] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_44_wd = reg_wdata[0];
+
+  assign mio_periph_insel_regwen_45_we = addr_hit[45] & reg_we & ~wr_err;
+  assign mio_periph_insel_regwen_45_wd = reg_wdata[0];
+
+  assign mio_periph_insel_0_we = addr_hit[46] & reg_we & ~wr_err;
   assign mio_periph_insel_0_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_1_we = addr_hit[42] & reg_we & ~wr_err;
+  assign mio_periph_insel_1_we = addr_hit[47] & reg_we & ~wr_err;
   assign mio_periph_insel_1_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_2_we = addr_hit[43] & reg_we & ~wr_err;
+  assign mio_periph_insel_2_we = addr_hit[48] & reg_we & ~wr_err;
   assign mio_periph_insel_2_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_3_we = addr_hit[44] & reg_we & ~wr_err;
+  assign mio_periph_insel_3_we = addr_hit[49] & reg_we & ~wr_err;
   assign mio_periph_insel_3_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_4_we = addr_hit[45] & reg_we & ~wr_err;
+  assign mio_periph_insel_4_we = addr_hit[50] & reg_we & ~wr_err;
   assign mio_periph_insel_4_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_5_we = addr_hit[46] & reg_we & ~wr_err;
+  assign mio_periph_insel_5_we = addr_hit[51] & reg_we & ~wr_err;
   assign mio_periph_insel_5_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_6_we = addr_hit[47] & reg_we & ~wr_err;
+  assign mio_periph_insel_6_we = addr_hit[52] & reg_we & ~wr_err;
   assign mio_periph_insel_6_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_7_we = addr_hit[48] & reg_we & ~wr_err;
+  assign mio_periph_insel_7_we = addr_hit[53] & reg_we & ~wr_err;
   assign mio_periph_insel_7_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_8_we = addr_hit[49] & reg_we & ~wr_err;
+  assign mio_periph_insel_8_we = addr_hit[54] & reg_we & ~wr_err;
   assign mio_periph_insel_8_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_9_we = addr_hit[50] & reg_we & ~wr_err;
+  assign mio_periph_insel_9_we = addr_hit[55] & reg_we & ~wr_err;
   assign mio_periph_insel_9_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_10_we = addr_hit[51] & reg_we & ~wr_err;
+  assign mio_periph_insel_10_we = addr_hit[56] & reg_we & ~wr_err;
   assign mio_periph_insel_10_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_11_we = addr_hit[52] & reg_we & ~wr_err;
+  assign mio_periph_insel_11_we = addr_hit[57] & reg_we & ~wr_err;
   assign mio_periph_insel_11_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_12_we = addr_hit[53] & reg_we & ~wr_err;
+  assign mio_periph_insel_12_we = addr_hit[58] & reg_we & ~wr_err;
   assign mio_periph_insel_12_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_13_we = addr_hit[54] & reg_we & ~wr_err;
+  assign mio_periph_insel_13_we = addr_hit[59] & reg_we & ~wr_err;
   assign mio_periph_insel_13_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_14_we = addr_hit[55] & reg_we & ~wr_err;
+  assign mio_periph_insel_14_we = addr_hit[60] & reg_we & ~wr_err;
   assign mio_periph_insel_14_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_15_we = addr_hit[56] & reg_we & ~wr_err;
+  assign mio_periph_insel_15_we = addr_hit[61] & reg_we & ~wr_err;
   assign mio_periph_insel_15_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_16_we = addr_hit[57] & reg_we & ~wr_err;
+  assign mio_periph_insel_16_we = addr_hit[62] & reg_we & ~wr_err;
   assign mio_periph_insel_16_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_17_we = addr_hit[58] & reg_we & ~wr_err;
+  assign mio_periph_insel_17_we = addr_hit[63] & reg_we & ~wr_err;
   assign mio_periph_insel_17_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_18_we = addr_hit[59] & reg_we & ~wr_err;
+  assign mio_periph_insel_18_we = addr_hit[64] & reg_we & ~wr_err;
   assign mio_periph_insel_18_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_19_we = addr_hit[60] & reg_we & ~wr_err;
+  assign mio_periph_insel_19_we = addr_hit[65] & reg_we & ~wr_err;
   assign mio_periph_insel_19_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_20_we = addr_hit[61] & reg_we & ~wr_err;
+  assign mio_periph_insel_20_we = addr_hit[66] & reg_we & ~wr_err;
   assign mio_periph_insel_20_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_21_we = addr_hit[62] & reg_we & ~wr_err;
+  assign mio_periph_insel_21_we = addr_hit[67] & reg_we & ~wr_err;
   assign mio_periph_insel_21_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_22_we = addr_hit[63] & reg_we & ~wr_err;
+  assign mio_periph_insel_22_we = addr_hit[68] & reg_we & ~wr_err;
   assign mio_periph_insel_22_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_23_we = addr_hit[64] & reg_we & ~wr_err;
+  assign mio_periph_insel_23_we = addr_hit[69] & reg_we & ~wr_err;
   assign mio_periph_insel_23_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_24_we = addr_hit[65] & reg_we & ~wr_err;
+  assign mio_periph_insel_24_we = addr_hit[70] & reg_we & ~wr_err;
   assign mio_periph_insel_24_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_25_we = addr_hit[66] & reg_we & ~wr_err;
+  assign mio_periph_insel_25_we = addr_hit[71] & reg_we & ~wr_err;
   assign mio_periph_insel_25_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_26_we = addr_hit[67] & reg_we & ~wr_err;
+  assign mio_periph_insel_26_we = addr_hit[72] & reg_we & ~wr_err;
   assign mio_periph_insel_26_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_27_we = addr_hit[68] & reg_we & ~wr_err;
+  assign mio_periph_insel_27_we = addr_hit[73] & reg_we & ~wr_err;
   assign mio_periph_insel_27_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_28_we = addr_hit[69] & reg_we & ~wr_err;
+  assign mio_periph_insel_28_we = addr_hit[74] & reg_we & ~wr_err;
   assign mio_periph_insel_28_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_29_we = addr_hit[70] & reg_we & ~wr_err;
+  assign mio_periph_insel_29_we = addr_hit[75] & reg_we & ~wr_err;
   assign mio_periph_insel_29_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_30_we = addr_hit[71] & reg_we & ~wr_err;
+  assign mio_periph_insel_30_we = addr_hit[76] & reg_we & ~wr_err;
   assign mio_periph_insel_30_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_31_we = addr_hit[72] & reg_we & ~wr_err;
+  assign mio_periph_insel_31_we = addr_hit[77] & reg_we & ~wr_err;
   assign mio_periph_insel_31_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_32_we = addr_hit[73] & reg_we & ~wr_err;
+  assign mio_periph_insel_32_we = addr_hit[78] & reg_we & ~wr_err;
   assign mio_periph_insel_32_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_33_we = addr_hit[74] & reg_we & ~wr_err;
+  assign mio_periph_insel_33_we = addr_hit[79] & reg_we & ~wr_err;
   assign mio_periph_insel_33_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_34_we = addr_hit[75] & reg_we & ~wr_err;
+  assign mio_periph_insel_34_we = addr_hit[80] & reg_we & ~wr_err;
   assign mio_periph_insel_34_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_35_we = addr_hit[76] & reg_we & ~wr_err;
+  assign mio_periph_insel_35_we = addr_hit[81] & reg_we & ~wr_err;
   assign mio_periph_insel_35_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_36_we = addr_hit[77] & reg_we & ~wr_err;
+  assign mio_periph_insel_36_we = addr_hit[82] & reg_we & ~wr_err;
   assign mio_periph_insel_36_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_37_we = addr_hit[78] & reg_we & ~wr_err;
+  assign mio_periph_insel_37_we = addr_hit[83] & reg_we & ~wr_err;
   assign mio_periph_insel_37_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_38_we = addr_hit[79] & reg_we & ~wr_err;
+  assign mio_periph_insel_38_we = addr_hit[84] & reg_we & ~wr_err;
   assign mio_periph_insel_38_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_39_we = addr_hit[80] & reg_we & ~wr_err;
+  assign mio_periph_insel_39_we = addr_hit[85] & reg_we & ~wr_err;
   assign mio_periph_insel_39_wd = reg_wdata[5:0];
 
-  assign mio_periph_insel_40_we = addr_hit[81] & reg_we & ~wr_err;
+  assign mio_periph_insel_40_we = addr_hit[86] & reg_we & ~wr_err;
   assign mio_periph_insel_40_wd = reg_wdata[5:0];
 
-  assign mio_outsel_regwen_0_we = addr_hit[82] & reg_we & ~wr_err;
+  assign mio_periph_insel_41_we = addr_hit[87] & reg_we & ~wr_err;
+  assign mio_periph_insel_41_wd = reg_wdata[5:0];
+
+  assign mio_periph_insel_42_we = addr_hit[88] & reg_we & ~wr_err;
+  assign mio_periph_insel_42_wd = reg_wdata[5:0];
+
+  assign mio_periph_insel_43_we = addr_hit[89] & reg_we & ~wr_err;
+  assign mio_periph_insel_43_wd = reg_wdata[5:0];
+
+  assign mio_periph_insel_44_we = addr_hit[90] & reg_we & ~wr_err;
+  assign mio_periph_insel_44_wd = reg_wdata[5:0];
+
+  assign mio_periph_insel_45_we = addr_hit[91] & reg_we & ~wr_err;
+  assign mio_periph_insel_45_wd = reg_wdata[5:0];
+
+  assign mio_outsel_regwen_0_we = addr_hit[92] & reg_we & ~wr_err;
   assign mio_outsel_regwen_0_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_1_we = addr_hit[83] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_1_we = addr_hit[93] & reg_we & ~wr_err;
   assign mio_outsel_regwen_1_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_2_we = addr_hit[84] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_2_we = addr_hit[94] & reg_we & ~wr_err;
   assign mio_outsel_regwen_2_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_3_we = addr_hit[85] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_3_we = addr_hit[95] & reg_we & ~wr_err;
   assign mio_outsel_regwen_3_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_4_we = addr_hit[86] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_4_we = addr_hit[96] & reg_we & ~wr_err;
   assign mio_outsel_regwen_4_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_5_we = addr_hit[87] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_5_we = addr_hit[97] & reg_we & ~wr_err;
   assign mio_outsel_regwen_5_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_6_we = addr_hit[88] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_6_we = addr_hit[98] & reg_we & ~wr_err;
   assign mio_outsel_regwen_6_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_7_we = addr_hit[89] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_7_we = addr_hit[99] & reg_we & ~wr_err;
   assign mio_outsel_regwen_7_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_8_we = addr_hit[90] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_8_we = addr_hit[100] & reg_we & ~wr_err;
   assign mio_outsel_regwen_8_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_9_we = addr_hit[91] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_9_we = addr_hit[101] & reg_we & ~wr_err;
   assign mio_outsel_regwen_9_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_10_we = addr_hit[92] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_10_we = addr_hit[102] & reg_we & ~wr_err;
   assign mio_outsel_regwen_10_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_11_we = addr_hit[93] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_11_we = addr_hit[103] & reg_we & ~wr_err;
   assign mio_outsel_regwen_11_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_12_we = addr_hit[94] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_12_we = addr_hit[104] & reg_we & ~wr_err;
   assign mio_outsel_regwen_12_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_13_we = addr_hit[95] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_13_we = addr_hit[105] & reg_we & ~wr_err;
   assign mio_outsel_regwen_13_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_14_we = addr_hit[96] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_14_we = addr_hit[106] & reg_we & ~wr_err;
   assign mio_outsel_regwen_14_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_15_we = addr_hit[97] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_15_we = addr_hit[107] & reg_we & ~wr_err;
   assign mio_outsel_regwen_15_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_16_we = addr_hit[98] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_16_we = addr_hit[108] & reg_we & ~wr_err;
   assign mio_outsel_regwen_16_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_17_we = addr_hit[99] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_17_we = addr_hit[109] & reg_we & ~wr_err;
   assign mio_outsel_regwen_17_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_18_we = addr_hit[100] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_18_we = addr_hit[110] & reg_we & ~wr_err;
   assign mio_outsel_regwen_18_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_19_we = addr_hit[101] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_19_we = addr_hit[111] & reg_we & ~wr_err;
   assign mio_outsel_regwen_19_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_20_we = addr_hit[102] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_20_we = addr_hit[112] & reg_we & ~wr_err;
   assign mio_outsel_regwen_20_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_21_we = addr_hit[103] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_21_we = addr_hit[113] & reg_we & ~wr_err;
   assign mio_outsel_regwen_21_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_22_we = addr_hit[104] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_22_we = addr_hit[114] & reg_we & ~wr_err;
   assign mio_outsel_regwen_22_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_23_we = addr_hit[105] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_23_we = addr_hit[115] & reg_we & ~wr_err;
   assign mio_outsel_regwen_23_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_24_we = addr_hit[106] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_24_we = addr_hit[116] & reg_we & ~wr_err;
   assign mio_outsel_regwen_24_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_25_we = addr_hit[107] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_25_we = addr_hit[117] & reg_we & ~wr_err;
   assign mio_outsel_regwen_25_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_26_we = addr_hit[108] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_26_we = addr_hit[118] & reg_we & ~wr_err;
   assign mio_outsel_regwen_26_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_27_we = addr_hit[109] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_27_we = addr_hit[119] & reg_we & ~wr_err;
   assign mio_outsel_regwen_27_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_28_we = addr_hit[110] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_28_we = addr_hit[120] & reg_we & ~wr_err;
   assign mio_outsel_regwen_28_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_29_we = addr_hit[111] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_29_we = addr_hit[121] & reg_we & ~wr_err;
   assign mio_outsel_regwen_29_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_30_we = addr_hit[112] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_30_we = addr_hit[122] & reg_we & ~wr_err;
   assign mio_outsel_regwen_30_wd = reg_wdata[0];
 
-  assign mio_outsel_regwen_31_we = addr_hit[113] & reg_we & ~wr_err;
+  assign mio_outsel_regwen_31_we = addr_hit[123] & reg_we & ~wr_err;
   assign mio_outsel_regwen_31_wd = reg_wdata[0];
 
-  assign mio_outsel_0_we = addr_hit[114] & reg_we & ~wr_err;
+  assign mio_outsel_0_we = addr_hit[124] & reg_we & ~wr_err;
   assign mio_outsel_0_wd = reg_wdata[5:0];
 
-  assign mio_outsel_1_we = addr_hit[115] & reg_we & ~wr_err;
+  assign mio_outsel_1_we = addr_hit[125] & reg_we & ~wr_err;
   assign mio_outsel_1_wd = reg_wdata[5:0];
 
-  assign mio_outsel_2_we = addr_hit[116] & reg_we & ~wr_err;
+  assign mio_outsel_2_we = addr_hit[126] & reg_we & ~wr_err;
   assign mio_outsel_2_wd = reg_wdata[5:0];
 
-  assign mio_outsel_3_we = addr_hit[117] & reg_we & ~wr_err;
+  assign mio_outsel_3_we = addr_hit[127] & reg_we & ~wr_err;
   assign mio_outsel_3_wd = reg_wdata[5:0];
 
-  assign mio_outsel_4_we = addr_hit[118] & reg_we & ~wr_err;
+  assign mio_outsel_4_we = addr_hit[128] & reg_we & ~wr_err;
   assign mio_outsel_4_wd = reg_wdata[5:0];
 
-  assign mio_outsel_5_we = addr_hit[119] & reg_we & ~wr_err;
+  assign mio_outsel_5_we = addr_hit[129] & reg_we & ~wr_err;
   assign mio_outsel_5_wd = reg_wdata[5:0];
 
-  assign mio_outsel_6_we = addr_hit[120] & reg_we & ~wr_err;
+  assign mio_outsel_6_we = addr_hit[130] & reg_we & ~wr_err;
   assign mio_outsel_6_wd = reg_wdata[5:0];
 
-  assign mio_outsel_7_we = addr_hit[121] & reg_we & ~wr_err;
+  assign mio_outsel_7_we = addr_hit[131] & reg_we & ~wr_err;
   assign mio_outsel_7_wd = reg_wdata[5:0];
 
-  assign mio_outsel_8_we = addr_hit[122] & reg_we & ~wr_err;
+  assign mio_outsel_8_we = addr_hit[132] & reg_we & ~wr_err;
   assign mio_outsel_8_wd = reg_wdata[5:0];
 
-  assign mio_outsel_9_we = addr_hit[123] & reg_we & ~wr_err;
+  assign mio_outsel_9_we = addr_hit[133] & reg_we & ~wr_err;
   assign mio_outsel_9_wd = reg_wdata[5:0];
 
-  assign mio_outsel_10_we = addr_hit[124] & reg_we & ~wr_err;
+  assign mio_outsel_10_we = addr_hit[134] & reg_we & ~wr_err;
   assign mio_outsel_10_wd = reg_wdata[5:0];
 
-  assign mio_outsel_11_we = addr_hit[125] & reg_we & ~wr_err;
+  assign mio_outsel_11_we = addr_hit[135] & reg_we & ~wr_err;
   assign mio_outsel_11_wd = reg_wdata[5:0];
 
-  assign mio_outsel_12_we = addr_hit[126] & reg_we & ~wr_err;
+  assign mio_outsel_12_we = addr_hit[136] & reg_we & ~wr_err;
   assign mio_outsel_12_wd = reg_wdata[5:0];
 
-  assign mio_outsel_13_we = addr_hit[127] & reg_we & ~wr_err;
+  assign mio_outsel_13_we = addr_hit[137] & reg_we & ~wr_err;
   assign mio_outsel_13_wd = reg_wdata[5:0];
 
-  assign mio_outsel_14_we = addr_hit[128] & reg_we & ~wr_err;
+  assign mio_outsel_14_we = addr_hit[138] & reg_we & ~wr_err;
   assign mio_outsel_14_wd = reg_wdata[5:0];
 
-  assign mio_outsel_15_we = addr_hit[129] & reg_we & ~wr_err;
+  assign mio_outsel_15_we = addr_hit[139] & reg_we & ~wr_err;
   assign mio_outsel_15_wd = reg_wdata[5:0];
 
-  assign mio_outsel_16_we = addr_hit[130] & reg_we & ~wr_err;
+  assign mio_outsel_16_we = addr_hit[140] & reg_we & ~wr_err;
   assign mio_outsel_16_wd = reg_wdata[5:0];
 
-  assign mio_outsel_17_we = addr_hit[131] & reg_we & ~wr_err;
+  assign mio_outsel_17_we = addr_hit[141] & reg_we & ~wr_err;
   assign mio_outsel_17_wd = reg_wdata[5:0];
 
-  assign mio_outsel_18_we = addr_hit[132] & reg_we & ~wr_err;
+  assign mio_outsel_18_we = addr_hit[142] & reg_we & ~wr_err;
   assign mio_outsel_18_wd = reg_wdata[5:0];
 
-  assign mio_outsel_19_we = addr_hit[133] & reg_we & ~wr_err;
+  assign mio_outsel_19_we = addr_hit[143] & reg_we & ~wr_err;
   assign mio_outsel_19_wd = reg_wdata[5:0];
 
-  assign mio_outsel_20_we = addr_hit[134] & reg_we & ~wr_err;
+  assign mio_outsel_20_we = addr_hit[144] & reg_we & ~wr_err;
   assign mio_outsel_20_wd = reg_wdata[5:0];
 
-  assign mio_outsel_21_we = addr_hit[135] & reg_we & ~wr_err;
+  assign mio_outsel_21_we = addr_hit[145] & reg_we & ~wr_err;
   assign mio_outsel_21_wd = reg_wdata[5:0];
 
-  assign mio_outsel_22_we = addr_hit[136] & reg_we & ~wr_err;
+  assign mio_outsel_22_we = addr_hit[146] & reg_we & ~wr_err;
   assign mio_outsel_22_wd = reg_wdata[5:0];
 
-  assign mio_outsel_23_we = addr_hit[137] & reg_we & ~wr_err;
+  assign mio_outsel_23_we = addr_hit[147] & reg_we & ~wr_err;
   assign mio_outsel_23_wd = reg_wdata[5:0];
 
-  assign mio_outsel_24_we = addr_hit[138] & reg_we & ~wr_err;
+  assign mio_outsel_24_we = addr_hit[148] & reg_we & ~wr_err;
   assign mio_outsel_24_wd = reg_wdata[5:0];
 
-  assign mio_outsel_25_we = addr_hit[139] & reg_we & ~wr_err;
+  assign mio_outsel_25_we = addr_hit[149] & reg_we & ~wr_err;
   assign mio_outsel_25_wd = reg_wdata[5:0];
 
-  assign mio_outsel_26_we = addr_hit[140] & reg_we & ~wr_err;
+  assign mio_outsel_26_we = addr_hit[150] & reg_we & ~wr_err;
   assign mio_outsel_26_wd = reg_wdata[5:0];
 
-  assign mio_outsel_27_we = addr_hit[141] & reg_we & ~wr_err;
+  assign mio_outsel_27_we = addr_hit[151] & reg_we & ~wr_err;
   assign mio_outsel_27_wd = reg_wdata[5:0];
 
-  assign mio_outsel_28_we = addr_hit[142] & reg_we & ~wr_err;
+  assign mio_outsel_28_we = addr_hit[152] & reg_we & ~wr_err;
   assign mio_outsel_28_wd = reg_wdata[5:0];
 
-  assign mio_outsel_29_we = addr_hit[143] & reg_we & ~wr_err;
+  assign mio_outsel_29_we = addr_hit[153] & reg_we & ~wr_err;
   assign mio_outsel_29_wd = reg_wdata[5:0];
 
-  assign mio_outsel_30_we = addr_hit[144] & reg_we & ~wr_err;
+  assign mio_outsel_30_we = addr_hit[154] & reg_we & ~wr_err;
   assign mio_outsel_30_wd = reg_wdata[5:0];
 
-  assign mio_outsel_31_we = addr_hit[145] & reg_we & ~wr_err;
+  assign mio_outsel_31_we = addr_hit[155] & reg_we & ~wr_err;
   assign mio_outsel_31_wd = reg_wdata[5:0];
 
-  assign mio_pad_attr_regwen_0_we = addr_hit[146] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_0_we = addr_hit[156] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_0_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_1_we = addr_hit[147] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_1_we = addr_hit[157] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_1_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_2_we = addr_hit[148] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_2_we = addr_hit[158] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_2_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_3_we = addr_hit[149] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_3_we = addr_hit[159] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_3_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_4_we = addr_hit[150] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_4_we = addr_hit[160] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_4_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_5_we = addr_hit[151] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_5_we = addr_hit[161] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_5_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_6_we = addr_hit[152] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_6_we = addr_hit[162] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_6_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_7_we = addr_hit[153] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_7_we = addr_hit[163] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_7_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_8_we = addr_hit[154] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_8_we = addr_hit[164] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_8_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_9_we = addr_hit[155] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_9_we = addr_hit[165] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_9_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_10_we = addr_hit[156] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_10_we = addr_hit[166] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_10_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_11_we = addr_hit[157] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_11_we = addr_hit[167] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_11_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_12_we = addr_hit[158] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_12_we = addr_hit[168] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_12_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_13_we = addr_hit[159] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_13_we = addr_hit[169] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_13_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_14_we = addr_hit[160] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_14_we = addr_hit[170] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_14_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_15_we = addr_hit[161] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_15_we = addr_hit[171] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_15_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_16_we = addr_hit[162] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_16_we = addr_hit[172] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_16_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_17_we = addr_hit[163] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_17_we = addr_hit[173] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_17_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_18_we = addr_hit[164] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_18_we = addr_hit[174] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_18_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_19_we = addr_hit[165] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_19_we = addr_hit[175] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_19_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_20_we = addr_hit[166] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_20_we = addr_hit[176] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_20_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_21_we = addr_hit[167] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_21_we = addr_hit[177] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_21_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_22_we = addr_hit[168] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_22_we = addr_hit[178] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_22_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_23_we = addr_hit[169] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_23_we = addr_hit[179] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_23_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_24_we = addr_hit[170] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_24_we = addr_hit[180] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_24_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_25_we = addr_hit[171] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_25_we = addr_hit[181] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_25_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_26_we = addr_hit[172] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_26_we = addr_hit[182] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_26_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_27_we = addr_hit[173] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_27_we = addr_hit[183] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_27_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_28_we = addr_hit[174] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_28_we = addr_hit[184] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_28_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_29_we = addr_hit[175] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_29_we = addr_hit[185] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_29_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_30_we = addr_hit[176] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_30_we = addr_hit[186] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_30_wd = reg_wdata[0];
 
-  assign mio_pad_attr_regwen_31_we = addr_hit[177] & reg_we & ~wr_err;
+  assign mio_pad_attr_regwen_31_we = addr_hit[187] & reg_we & ~wr_err;
   assign mio_pad_attr_regwen_31_wd = reg_wdata[0];
 
-  assign mio_pad_attr_0_we = addr_hit[178] & reg_we & ~wr_err;
+  assign mio_pad_attr_0_we = addr_hit[188] & reg_we & ~wr_err;
   assign mio_pad_attr_0_wd = reg_wdata[9:0];
-  assign mio_pad_attr_0_re = addr_hit[178] && reg_re;
+  assign mio_pad_attr_0_re = addr_hit[188] && reg_re;
 
-  assign mio_pad_attr_1_we = addr_hit[179] & reg_we & ~wr_err;
+  assign mio_pad_attr_1_we = addr_hit[189] & reg_we & ~wr_err;
   assign mio_pad_attr_1_wd = reg_wdata[9:0];
-  assign mio_pad_attr_1_re = addr_hit[179] && reg_re;
+  assign mio_pad_attr_1_re = addr_hit[189] && reg_re;
 
-  assign mio_pad_attr_2_we = addr_hit[180] & reg_we & ~wr_err;
+  assign mio_pad_attr_2_we = addr_hit[190] & reg_we & ~wr_err;
   assign mio_pad_attr_2_wd = reg_wdata[9:0];
-  assign mio_pad_attr_2_re = addr_hit[180] && reg_re;
+  assign mio_pad_attr_2_re = addr_hit[190] && reg_re;
 
-  assign mio_pad_attr_3_we = addr_hit[181] & reg_we & ~wr_err;
+  assign mio_pad_attr_3_we = addr_hit[191] & reg_we & ~wr_err;
   assign mio_pad_attr_3_wd = reg_wdata[9:0];
-  assign mio_pad_attr_3_re = addr_hit[181] && reg_re;
+  assign mio_pad_attr_3_re = addr_hit[191] && reg_re;
 
-  assign mio_pad_attr_4_we = addr_hit[182] & reg_we & ~wr_err;
+  assign mio_pad_attr_4_we = addr_hit[192] & reg_we & ~wr_err;
   assign mio_pad_attr_4_wd = reg_wdata[9:0];
-  assign mio_pad_attr_4_re = addr_hit[182] && reg_re;
+  assign mio_pad_attr_4_re = addr_hit[192] && reg_re;
 
-  assign mio_pad_attr_5_we = addr_hit[183] & reg_we & ~wr_err;
+  assign mio_pad_attr_5_we = addr_hit[193] & reg_we & ~wr_err;
   assign mio_pad_attr_5_wd = reg_wdata[9:0];
-  assign mio_pad_attr_5_re = addr_hit[183] && reg_re;
+  assign mio_pad_attr_5_re = addr_hit[193] && reg_re;
 
-  assign mio_pad_attr_6_we = addr_hit[184] & reg_we & ~wr_err;
+  assign mio_pad_attr_6_we = addr_hit[194] & reg_we & ~wr_err;
   assign mio_pad_attr_6_wd = reg_wdata[9:0];
-  assign mio_pad_attr_6_re = addr_hit[184] && reg_re;
+  assign mio_pad_attr_6_re = addr_hit[194] && reg_re;
 
-  assign mio_pad_attr_7_we = addr_hit[185] & reg_we & ~wr_err;
+  assign mio_pad_attr_7_we = addr_hit[195] & reg_we & ~wr_err;
   assign mio_pad_attr_7_wd = reg_wdata[9:0];
-  assign mio_pad_attr_7_re = addr_hit[185] && reg_re;
+  assign mio_pad_attr_7_re = addr_hit[195] && reg_re;
 
-  assign mio_pad_attr_8_we = addr_hit[186] & reg_we & ~wr_err;
+  assign mio_pad_attr_8_we = addr_hit[196] & reg_we & ~wr_err;
   assign mio_pad_attr_8_wd = reg_wdata[9:0];
-  assign mio_pad_attr_8_re = addr_hit[186] && reg_re;
+  assign mio_pad_attr_8_re = addr_hit[196] && reg_re;
 
-  assign mio_pad_attr_9_we = addr_hit[187] & reg_we & ~wr_err;
+  assign mio_pad_attr_9_we = addr_hit[197] & reg_we & ~wr_err;
   assign mio_pad_attr_9_wd = reg_wdata[9:0];
-  assign mio_pad_attr_9_re = addr_hit[187] && reg_re;
+  assign mio_pad_attr_9_re = addr_hit[197] && reg_re;
 
-  assign mio_pad_attr_10_we = addr_hit[188] & reg_we & ~wr_err;
+  assign mio_pad_attr_10_we = addr_hit[198] & reg_we & ~wr_err;
   assign mio_pad_attr_10_wd = reg_wdata[9:0];
-  assign mio_pad_attr_10_re = addr_hit[188] && reg_re;
+  assign mio_pad_attr_10_re = addr_hit[198] && reg_re;
 
-  assign mio_pad_attr_11_we = addr_hit[189] & reg_we & ~wr_err;
+  assign mio_pad_attr_11_we = addr_hit[199] & reg_we & ~wr_err;
   assign mio_pad_attr_11_wd = reg_wdata[9:0];
-  assign mio_pad_attr_11_re = addr_hit[189] && reg_re;
+  assign mio_pad_attr_11_re = addr_hit[199] && reg_re;
 
-  assign mio_pad_attr_12_we = addr_hit[190] & reg_we & ~wr_err;
+  assign mio_pad_attr_12_we = addr_hit[200] & reg_we & ~wr_err;
   assign mio_pad_attr_12_wd = reg_wdata[9:0];
-  assign mio_pad_attr_12_re = addr_hit[190] && reg_re;
+  assign mio_pad_attr_12_re = addr_hit[200] && reg_re;
 
-  assign mio_pad_attr_13_we = addr_hit[191] & reg_we & ~wr_err;
+  assign mio_pad_attr_13_we = addr_hit[201] & reg_we & ~wr_err;
   assign mio_pad_attr_13_wd = reg_wdata[9:0];
-  assign mio_pad_attr_13_re = addr_hit[191] && reg_re;
+  assign mio_pad_attr_13_re = addr_hit[201] && reg_re;
 
-  assign mio_pad_attr_14_we = addr_hit[192] & reg_we & ~wr_err;
+  assign mio_pad_attr_14_we = addr_hit[202] & reg_we & ~wr_err;
   assign mio_pad_attr_14_wd = reg_wdata[9:0];
-  assign mio_pad_attr_14_re = addr_hit[192] && reg_re;
+  assign mio_pad_attr_14_re = addr_hit[202] && reg_re;
 
-  assign mio_pad_attr_15_we = addr_hit[193] & reg_we & ~wr_err;
+  assign mio_pad_attr_15_we = addr_hit[203] & reg_we & ~wr_err;
   assign mio_pad_attr_15_wd = reg_wdata[9:0];
-  assign mio_pad_attr_15_re = addr_hit[193] && reg_re;
+  assign mio_pad_attr_15_re = addr_hit[203] && reg_re;
 
-  assign mio_pad_attr_16_we = addr_hit[194] & reg_we & ~wr_err;
+  assign mio_pad_attr_16_we = addr_hit[204] & reg_we & ~wr_err;
   assign mio_pad_attr_16_wd = reg_wdata[9:0];
-  assign mio_pad_attr_16_re = addr_hit[194] && reg_re;
+  assign mio_pad_attr_16_re = addr_hit[204] && reg_re;
 
-  assign mio_pad_attr_17_we = addr_hit[195] & reg_we & ~wr_err;
+  assign mio_pad_attr_17_we = addr_hit[205] & reg_we & ~wr_err;
   assign mio_pad_attr_17_wd = reg_wdata[9:0];
-  assign mio_pad_attr_17_re = addr_hit[195] && reg_re;
+  assign mio_pad_attr_17_re = addr_hit[205] && reg_re;
 
-  assign mio_pad_attr_18_we = addr_hit[196] & reg_we & ~wr_err;
+  assign mio_pad_attr_18_we = addr_hit[206] & reg_we & ~wr_err;
   assign mio_pad_attr_18_wd = reg_wdata[9:0];
-  assign mio_pad_attr_18_re = addr_hit[196] && reg_re;
+  assign mio_pad_attr_18_re = addr_hit[206] && reg_re;
 
-  assign mio_pad_attr_19_we = addr_hit[197] & reg_we & ~wr_err;
+  assign mio_pad_attr_19_we = addr_hit[207] & reg_we & ~wr_err;
   assign mio_pad_attr_19_wd = reg_wdata[9:0];
-  assign mio_pad_attr_19_re = addr_hit[197] && reg_re;
+  assign mio_pad_attr_19_re = addr_hit[207] && reg_re;
 
-  assign mio_pad_attr_20_we = addr_hit[198] & reg_we & ~wr_err;
+  assign mio_pad_attr_20_we = addr_hit[208] & reg_we & ~wr_err;
   assign mio_pad_attr_20_wd = reg_wdata[9:0];
-  assign mio_pad_attr_20_re = addr_hit[198] && reg_re;
+  assign mio_pad_attr_20_re = addr_hit[208] && reg_re;
 
-  assign mio_pad_attr_21_we = addr_hit[199] & reg_we & ~wr_err;
+  assign mio_pad_attr_21_we = addr_hit[209] & reg_we & ~wr_err;
   assign mio_pad_attr_21_wd = reg_wdata[9:0];
-  assign mio_pad_attr_21_re = addr_hit[199] && reg_re;
+  assign mio_pad_attr_21_re = addr_hit[209] && reg_re;
 
-  assign mio_pad_attr_22_we = addr_hit[200] & reg_we & ~wr_err;
+  assign mio_pad_attr_22_we = addr_hit[210] & reg_we & ~wr_err;
   assign mio_pad_attr_22_wd = reg_wdata[9:0];
-  assign mio_pad_attr_22_re = addr_hit[200] && reg_re;
+  assign mio_pad_attr_22_re = addr_hit[210] && reg_re;
 
-  assign mio_pad_attr_23_we = addr_hit[201] & reg_we & ~wr_err;
+  assign mio_pad_attr_23_we = addr_hit[211] & reg_we & ~wr_err;
   assign mio_pad_attr_23_wd = reg_wdata[9:0];
-  assign mio_pad_attr_23_re = addr_hit[201] && reg_re;
+  assign mio_pad_attr_23_re = addr_hit[211] && reg_re;
 
-  assign mio_pad_attr_24_we = addr_hit[202] & reg_we & ~wr_err;
+  assign mio_pad_attr_24_we = addr_hit[212] & reg_we & ~wr_err;
   assign mio_pad_attr_24_wd = reg_wdata[9:0];
-  assign mio_pad_attr_24_re = addr_hit[202] && reg_re;
+  assign mio_pad_attr_24_re = addr_hit[212] && reg_re;
 
-  assign mio_pad_attr_25_we = addr_hit[203] & reg_we & ~wr_err;
+  assign mio_pad_attr_25_we = addr_hit[213] & reg_we & ~wr_err;
   assign mio_pad_attr_25_wd = reg_wdata[9:0];
-  assign mio_pad_attr_25_re = addr_hit[203] && reg_re;
+  assign mio_pad_attr_25_re = addr_hit[213] && reg_re;
 
-  assign mio_pad_attr_26_we = addr_hit[204] & reg_we & ~wr_err;
+  assign mio_pad_attr_26_we = addr_hit[214] & reg_we & ~wr_err;
   assign mio_pad_attr_26_wd = reg_wdata[9:0];
-  assign mio_pad_attr_26_re = addr_hit[204] && reg_re;
+  assign mio_pad_attr_26_re = addr_hit[214] && reg_re;
 
-  assign mio_pad_attr_27_we = addr_hit[205] & reg_we & ~wr_err;
+  assign mio_pad_attr_27_we = addr_hit[215] & reg_we & ~wr_err;
   assign mio_pad_attr_27_wd = reg_wdata[9:0];
-  assign mio_pad_attr_27_re = addr_hit[205] && reg_re;
+  assign mio_pad_attr_27_re = addr_hit[215] && reg_re;
 
-  assign mio_pad_attr_28_we = addr_hit[206] & reg_we & ~wr_err;
+  assign mio_pad_attr_28_we = addr_hit[216] & reg_we & ~wr_err;
   assign mio_pad_attr_28_wd = reg_wdata[9:0];
-  assign mio_pad_attr_28_re = addr_hit[206] && reg_re;
+  assign mio_pad_attr_28_re = addr_hit[216] && reg_re;
 
-  assign mio_pad_attr_29_we = addr_hit[207] & reg_we & ~wr_err;
+  assign mio_pad_attr_29_we = addr_hit[217] & reg_we & ~wr_err;
   assign mio_pad_attr_29_wd = reg_wdata[9:0];
-  assign mio_pad_attr_29_re = addr_hit[207] && reg_re;
+  assign mio_pad_attr_29_re = addr_hit[217] && reg_re;
 
-  assign mio_pad_attr_30_we = addr_hit[208] & reg_we & ~wr_err;
+  assign mio_pad_attr_30_we = addr_hit[218] & reg_we & ~wr_err;
   assign mio_pad_attr_30_wd = reg_wdata[9:0];
-  assign mio_pad_attr_30_re = addr_hit[208] && reg_re;
+  assign mio_pad_attr_30_re = addr_hit[218] && reg_re;
 
-  assign mio_pad_attr_31_we = addr_hit[209] & reg_we & ~wr_err;
+  assign mio_pad_attr_31_we = addr_hit[219] & reg_we & ~wr_err;
   assign mio_pad_attr_31_wd = reg_wdata[9:0];
-  assign mio_pad_attr_31_re = addr_hit[209] && reg_re;
+  assign mio_pad_attr_31_re = addr_hit[219] && reg_re;
 
-  assign dio_pad_attr_regwen_0_we = addr_hit[210] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_0_we = addr_hit[220] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_0_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_1_we = addr_hit[211] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_1_we = addr_hit[221] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_1_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_2_we = addr_hit[212] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_2_we = addr_hit[222] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_2_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_3_we = addr_hit[213] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_3_we = addr_hit[223] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_3_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_4_we = addr_hit[214] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_4_we = addr_hit[224] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_4_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_5_we = addr_hit[215] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_5_we = addr_hit[225] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_5_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_6_we = addr_hit[216] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_6_we = addr_hit[226] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_6_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_7_we = addr_hit[217] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_7_we = addr_hit[227] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_7_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_8_we = addr_hit[218] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_8_we = addr_hit[228] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_8_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_9_we = addr_hit[219] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_9_we = addr_hit[229] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_9_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_10_we = addr_hit[220] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_10_we = addr_hit[230] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_10_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_11_we = addr_hit[221] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_11_we = addr_hit[231] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_11_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_12_we = addr_hit[222] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_12_we = addr_hit[232] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_12_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_13_we = addr_hit[223] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_13_we = addr_hit[233] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_13_wd = reg_wdata[0];
 
-  assign dio_pad_attr_regwen_14_we = addr_hit[224] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_14_we = addr_hit[234] & reg_we & ~wr_err;
   assign dio_pad_attr_regwen_14_wd = reg_wdata[0];
 
-  assign dio_pad_attr_0_we = addr_hit[225] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_15_we = addr_hit[235] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_15_wd = reg_wdata[0];
+
+  assign dio_pad_attr_regwen_16_we = addr_hit[236] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_16_wd = reg_wdata[0];
+
+  assign dio_pad_attr_regwen_17_we = addr_hit[237] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_17_wd = reg_wdata[0];
+
+  assign dio_pad_attr_regwen_18_we = addr_hit[238] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_18_wd = reg_wdata[0];
+
+  assign dio_pad_attr_regwen_19_we = addr_hit[239] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_19_wd = reg_wdata[0];
+
+  assign dio_pad_attr_regwen_20_we = addr_hit[240] & reg_we & ~wr_err;
+  assign dio_pad_attr_regwen_20_wd = reg_wdata[0];
+
+  assign dio_pad_attr_0_we = addr_hit[241] & reg_we & ~wr_err;
   assign dio_pad_attr_0_wd = reg_wdata[9:0];
-  assign dio_pad_attr_0_re = addr_hit[225] && reg_re;
+  assign dio_pad_attr_0_re = addr_hit[241] && reg_re;
 
-  assign dio_pad_attr_1_we = addr_hit[226] & reg_we & ~wr_err;
+  assign dio_pad_attr_1_we = addr_hit[242] & reg_we & ~wr_err;
   assign dio_pad_attr_1_wd = reg_wdata[9:0];
-  assign dio_pad_attr_1_re = addr_hit[226] && reg_re;
+  assign dio_pad_attr_1_re = addr_hit[242] && reg_re;
 
-  assign dio_pad_attr_2_we = addr_hit[227] & reg_we & ~wr_err;
+  assign dio_pad_attr_2_we = addr_hit[243] & reg_we & ~wr_err;
   assign dio_pad_attr_2_wd = reg_wdata[9:0];
-  assign dio_pad_attr_2_re = addr_hit[227] && reg_re;
+  assign dio_pad_attr_2_re = addr_hit[243] && reg_re;
 
-  assign dio_pad_attr_3_we = addr_hit[228] & reg_we & ~wr_err;
+  assign dio_pad_attr_3_we = addr_hit[244] & reg_we & ~wr_err;
   assign dio_pad_attr_3_wd = reg_wdata[9:0];
-  assign dio_pad_attr_3_re = addr_hit[228] && reg_re;
+  assign dio_pad_attr_3_re = addr_hit[244] && reg_re;
 
-  assign dio_pad_attr_4_we = addr_hit[229] & reg_we & ~wr_err;
+  assign dio_pad_attr_4_we = addr_hit[245] & reg_we & ~wr_err;
   assign dio_pad_attr_4_wd = reg_wdata[9:0];
-  assign dio_pad_attr_4_re = addr_hit[229] && reg_re;
+  assign dio_pad_attr_4_re = addr_hit[245] && reg_re;
 
-  assign dio_pad_attr_5_we = addr_hit[230] & reg_we & ~wr_err;
+  assign dio_pad_attr_5_we = addr_hit[246] & reg_we & ~wr_err;
   assign dio_pad_attr_5_wd = reg_wdata[9:0];
-  assign dio_pad_attr_5_re = addr_hit[230] && reg_re;
+  assign dio_pad_attr_5_re = addr_hit[246] && reg_re;
 
-  assign dio_pad_attr_6_we = addr_hit[231] & reg_we & ~wr_err;
+  assign dio_pad_attr_6_we = addr_hit[247] & reg_we & ~wr_err;
   assign dio_pad_attr_6_wd = reg_wdata[9:0];
-  assign dio_pad_attr_6_re = addr_hit[231] && reg_re;
+  assign dio_pad_attr_6_re = addr_hit[247] && reg_re;
 
-  assign dio_pad_attr_7_we = addr_hit[232] & reg_we & ~wr_err;
+  assign dio_pad_attr_7_we = addr_hit[248] & reg_we & ~wr_err;
   assign dio_pad_attr_7_wd = reg_wdata[9:0];
-  assign dio_pad_attr_7_re = addr_hit[232] && reg_re;
+  assign dio_pad_attr_7_re = addr_hit[248] && reg_re;
 
-  assign dio_pad_attr_8_we = addr_hit[233] & reg_we & ~wr_err;
+  assign dio_pad_attr_8_we = addr_hit[249] & reg_we & ~wr_err;
   assign dio_pad_attr_8_wd = reg_wdata[9:0];
-  assign dio_pad_attr_8_re = addr_hit[233] && reg_re;
+  assign dio_pad_attr_8_re = addr_hit[249] && reg_re;
 
-  assign dio_pad_attr_9_we = addr_hit[234] & reg_we & ~wr_err;
+  assign dio_pad_attr_9_we = addr_hit[250] & reg_we & ~wr_err;
   assign dio_pad_attr_9_wd = reg_wdata[9:0];
-  assign dio_pad_attr_9_re = addr_hit[234] && reg_re;
+  assign dio_pad_attr_9_re = addr_hit[250] && reg_re;
 
-  assign dio_pad_attr_10_we = addr_hit[235] & reg_we & ~wr_err;
+  assign dio_pad_attr_10_we = addr_hit[251] & reg_we & ~wr_err;
   assign dio_pad_attr_10_wd = reg_wdata[9:0];
-  assign dio_pad_attr_10_re = addr_hit[235] && reg_re;
+  assign dio_pad_attr_10_re = addr_hit[251] && reg_re;
 
-  assign dio_pad_attr_11_we = addr_hit[236] & reg_we & ~wr_err;
+  assign dio_pad_attr_11_we = addr_hit[252] & reg_we & ~wr_err;
   assign dio_pad_attr_11_wd = reg_wdata[9:0];
-  assign dio_pad_attr_11_re = addr_hit[236] && reg_re;
+  assign dio_pad_attr_11_re = addr_hit[252] && reg_re;
 
-  assign dio_pad_attr_12_we = addr_hit[237] & reg_we & ~wr_err;
+  assign dio_pad_attr_12_we = addr_hit[253] & reg_we & ~wr_err;
   assign dio_pad_attr_12_wd = reg_wdata[9:0];
-  assign dio_pad_attr_12_re = addr_hit[237] && reg_re;
+  assign dio_pad_attr_12_re = addr_hit[253] && reg_re;
 
-  assign dio_pad_attr_13_we = addr_hit[238] & reg_we & ~wr_err;
+  assign dio_pad_attr_13_we = addr_hit[254] & reg_we & ~wr_err;
   assign dio_pad_attr_13_wd = reg_wdata[9:0];
-  assign dio_pad_attr_13_re = addr_hit[238] && reg_re;
+  assign dio_pad_attr_13_re = addr_hit[254] && reg_re;
 
-  assign dio_pad_attr_14_we = addr_hit[239] & reg_we & ~wr_err;
+  assign dio_pad_attr_14_we = addr_hit[255] & reg_we & ~wr_err;
   assign dio_pad_attr_14_wd = reg_wdata[9:0];
-  assign dio_pad_attr_14_re = addr_hit[239] && reg_re;
+  assign dio_pad_attr_14_re = addr_hit[255] && reg_re;
 
-  assign mio_pad_sleep_status_en_0_we = addr_hit[240] & reg_we & ~wr_err;
+  assign dio_pad_attr_15_we = addr_hit[256] & reg_we & ~wr_err;
+  assign dio_pad_attr_15_wd = reg_wdata[9:0];
+  assign dio_pad_attr_15_re = addr_hit[256] && reg_re;
+
+  assign dio_pad_attr_16_we = addr_hit[257] & reg_we & ~wr_err;
+  assign dio_pad_attr_16_wd = reg_wdata[9:0];
+  assign dio_pad_attr_16_re = addr_hit[257] && reg_re;
+
+  assign dio_pad_attr_17_we = addr_hit[258] & reg_we & ~wr_err;
+  assign dio_pad_attr_17_wd = reg_wdata[9:0];
+  assign dio_pad_attr_17_re = addr_hit[258] && reg_re;
+
+  assign dio_pad_attr_18_we = addr_hit[259] & reg_we & ~wr_err;
+  assign dio_pad_attr_18_wd = reg_wdata[9:0];
+  assign dio_pad_attr_18_re = addr_hit[259] && reg_re;
+
+  assign dio_pad_attr_19_we = addr_hit[260] & reg_we & ~wr_err;
+  assign dio_pad_attr_19_wd = reg_wdata[9:0];
+  assign dio_pad_attr_19_re = addr_hit[260] && reg_re;
+
+  assign dio_pad_attr_20_we = addr_hit[261] & reg_we & ~wr_err;
+  assign dio_pad_attr_20_wd = reg_wdata[9:0];
+  assign dio_pad_attr_20_re = addr_hit[261] && reg_re;
+
+  assign mio_pad_sleep_status_en_0_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_status_en_1_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_1_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_1_wd = reg_wdata[1];
 
-  assign mio_pad_sleep_status_en_2_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_2_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_2_wd = reg_wdata[2];
 
-  assign mio_pad_sleep_status_en_3_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_3_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_3_wd = reg_wdata[3];
 
-  assign mio_pad_sleep_status_en_4_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_4_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_4_wd = reg_wdata[4];
 
-  assign mio_pad_sleep_status_en_5_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_5_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_5_wd = reg_wdata[5];
 
-  assign mio_pad_sleep_status_en_6_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_6_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_6_wd = reg_wdata[6];
 
-  assign mio_pad_sleep_status_en_7_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_7_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_7_wd = reg_wdata[7];
 
-  assign mio_pad_sleep_status_en_8_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_8_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_8_wd = reg_wdata[8];
 
-  assign mio_pad_sleep_status_en_9_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_9_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_9_wd = reg_wdata[9];
 
-  assign mio_pad_sleep_status_en_10_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_10_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_10_wd = reg_wdata[10];
 
-  assign mio_pad_sleep_status_en_11_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_11_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_11_wd = reg_wdata[11];
 
-  assign mio_pad_sleep_status_en_12_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_12_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_12_wd = reg_wdata[12];
 
-  assign mio_pad_sleep_status_en_13_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_13_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_13_wd = reg_wdata[13];
 
-  assign mio_pad_sleep_status_en_14_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_14_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_14_wd = reg_wdata[14];
 
-  assign mio_pad_sleep_status_en_15_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_15_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_15_wd = reg_wdata[15];
 
-  assign mio_pad_sleep_status_en_16_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_16_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_16_wd = reg_wdata[16];
 
-  assign mio_pad_sleep_status_en_17_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_17_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_17_wd = reg_wdata[17];
 
-  assign mio_pad_sleep_status_en_18_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_18_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_18_wd = reg_wdata[18];
 
-  assign mio_pad_sleep_status_en_19_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_19_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_19_wd = reg_wdata[19];
 
-  assign mio_pad_sleep_status_en_20_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_20_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_20_wd = reg_wdata[20];
 
-  assign mio_pad_sleep_status_en_21_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_21_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_21_wd = reg_wdata[21];
 
-  assign mio_pad_sleep_status_en_22_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_22_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_22_wd = reg_wdata[22];
 
-  assign mio_pad_sleep_status_en_23_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_23_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_23_wd = reg_wdata[23];
 
-  assign mio_pad_sleep_status_en_24_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_24_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_24_wd = reg_wdata[24];
 
-  assign mio_pad_sleep_status_en_25_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_25_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_25_wd = reg_wdata[25];
 
-  assign mio_pad_sleep_status_en_26_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_26_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_26_wd = reg_wdata[26];
 
-  assign mio_pad_sleep_status_en_27_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_27_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_27_wd = reg_wdata[27];
 
-  assign mio_pad_sleep_status_en_28_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_28_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_28_wd = reg_wdata[28];
 
-  assign mio_pad_sleep_status_en_29_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_29_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_29_wd = reg_wdata[29];
 
-  assign mio_pad_sleep_status_en_30_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_30_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_30_wd = reg_wdata[30];
 
-  assign mio_pad_sleep_status_en_31_we = addr_hit[240] & reg_we & ~wr_err;
+  assign mio_pad_sleep_status_en_31_we = addr_hit[262] & reg_we & ~wr_err;
   assign mio_pad_sleep_status_en_31_wd = reg_wdata[31];
 
-  assign mio_pad_sleep_regwen_0_we = addr_hit[241] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_0_we = addr_hit[263] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_1_we = addr_hit[242] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_1_we = addr_hit[264] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_1_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_2_we = addr_hit[243] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_2_we = addr_hit[265] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_2_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_3_we = addr_hit[244] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_3_we = addr_hit[266] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_3_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_4_we = addr_hit[245] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_4_we = addr_hit[267] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_4_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_5_we = addr_hit[246] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_5_we = addr_hit[268] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_5_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_6_we = addr_hit[247] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_6_we = addr_hit[269] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_6_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_7_we = addr_hit[248] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_7_we = addr_hit[270] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_7_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_8_we = addr_hit[249] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_8_we = addr_hit[271] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_8_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_9_we = addr_hit[250] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_9_we = addr_hit[272] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_9_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_10_we = addr_hit[251] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_10_we = addr_hit[273] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_10_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_11_we = addr_hit[252] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_11_we = addr_hit[274] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_11_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_12_we = addr_hit[253] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_12_we = addr_hit[275] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_12_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_13_we = addr_hit[254] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_13_we = addr_hit[276] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_13_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_14_we = addr_hit[255] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_14_we = addr_hit[277] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_14_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_15_we = addr_hit[256] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_15_we = addr_hit[278] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_15_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_16_we = addr_hit[257] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_16_we = addr_hit[279] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_16_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_17_we = addr_hit[258] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_17_we = addr_hit[280] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_17_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_18_we = addr_hit[259] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_18_we = addr_hit[281] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_18_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_19_we = addr_hit[260] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_19_we = addr_hit[282] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_19_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_20_we = addr_hit[261] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_20_we = addr_hit[283] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_20_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_21_we = addr_hit[262] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_21_we = addr_hit[284] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_21_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_22_we = addr_hit[263] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_22_we = addr_hit[285] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_22_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_23_we = addr_hit[264] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_23_we = addr_hit[286] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_23_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_24_we = addr_hit[265] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_24_we = addr_hit[287] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_24_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_25_we = addr_hit[266] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_25_we = addr_hit[288] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_25_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_26_we = addr_hit[267] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_26_we = addr_hit[289] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_26_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_27_we = addr_hit[268] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_27_we = addr_hit[290] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_27_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_28_we = addr_hit[269] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_28_we = addr_hit[291] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_28_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_29_we = addr_hit[270] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_29_we = addr_hit[292] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_29_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_30_we = addr_hit[271] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_30_we = addr_hit[293] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_30_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_regwen_31_we = addr_hit[272] & reg_we & ~wr_err;
+  assign mio_pad_sleep_regwen_31_we = addr_hit[294] & reg_we & ~wr_err;
   assign mio_pad_sleep_regwen_31_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_0_we = addr_hit[273] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_0_we = addr_hit[295] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_0_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_1_we = addr_hit[274] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_1_we = addr_hit[296] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_1_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_2_we = addr_hit[275] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_2_we = addr_hit[297] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_2_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_3_we = addr_hit[276] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_3_we = addr_hit[298] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_3_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_4_we = addr_hit[277] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_4_we = addr_hit[299] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_4_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_5_we = addr_hit[278] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_5_we = addr_hit[300] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_5_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_6_we = addr_hit[279] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_6_we = addr_hit[301] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_6_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_7_we = addr_hit[280] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_7_we = addr_hit[302] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_7_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_8_we = addr_hit[281] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_8_we = addr_hit[303] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_8_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_9_we = addr_hit[282] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_9_we = addr_hit[304] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_9_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_10_we = addr_hit[283] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_10_we = addr_hit[305] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_10_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_11_we = addr_hit[284] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_11_we = addr_hit[306] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_11_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_12_we = addr_hit[285] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_12_we = addr_hit[307] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_12_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_13_we = addr_hit[286] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_13_we = addr_hit[308] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_13_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_14_we = addr_hit[287] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_14_we = addr_hit[309] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_14_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_15_we = addr_hit[288] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_15_we = addr_hit[310] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_15_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_16_we = addr_hit[289] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_16_we = addr_hit[311] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_16_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_17_we = addr_hit[290] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_17_we = addr_hit[312] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_17_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_18_we = addr_hit[291] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_18_we = addr_hit[313] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_18_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_19_we = addr_hit[292] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_19_we = addr_hit[314] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_19_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_20_we = addr_hit[293] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_20_we = addr_hit[315] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_20_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_21_we = addr_hit[294] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_21_we = addr_hit[316] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_21_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_22_we = addr_hit[295] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_22_we = addr_hit[317] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_22_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_23_we = addr_hit[296] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_23_we = addr_hit[318] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_23_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_24_we = addr_hit[297] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_24_we = addr_hit[319] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_24_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_25_we = addr_hit[298] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_25_we = addr_hit[320] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_25_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_26_we = addr_hit[299] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_26_we = addr_hit[321] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_26_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_27_we = addr_hit[300] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_27_we = addr_hit[322] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_27_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_28_we = addr_hit[301] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_28_we = addr_hit[323] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_28_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_29_we = addr_hit[302] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_29_we = addr_hit[324] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_29_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_30_we = addr_hit[303] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_30_we = addr_hit[325] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_30_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_en_31_we = addr_hit[304] & reg_we & ~wr_err;
+  assign mio_pad_sleep_en_31_we = addr_hit[326] & reg_we & ~wr_err;
   assign mio_pad_sleep_en_31_wd = reg_wdata[0];
 
-  assign mio_pad_sleep_mode_0_we = addr_hit[305] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_0_we = addr_hit[327] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_1_we = addr_hit[306] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_1_we = addr_hit[328] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_2_we = addr_hit[307] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_2_we = addr_hit[329] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_3_we = addr_hit[308] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_3_we = addr_hit[330] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_4_we = addr_hit[309] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_4_we = addr_hit[331] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_5_we = addr_hit[310] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_5_we = addr_hit[332] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_6_we = addr_hit[311] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_6_we = addr_hit[333] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_7_we = addr_hit[312] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_7_we = addr_hit[334] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_8_we = addr_hit[313] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_8_we = addr_hit[335] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_9_we = addr_hit[314] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_9_we = addr_hit[336] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_10_we = addr_hit[315] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_10_we = addr_hit[337] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_11_we = addr_hit[316] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_11_we = addr_hit[338] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_12_we = addr_hit[317] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_12_we = addr_hit[339] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_13_we = addr_hit[318] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_13_we = addr_hit[340] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_14_we = addr_hit[319] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_14_we = addr_hit[341] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_15_we = addr_hit[320] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_15_we = addr_hit[342] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_16_we = addr_hit[321] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_16_we = addr_hit[343] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_17_we = addr_hit[322] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_17_we = addr_hit[344] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_18_we = addr_hit[323] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_18_we = addr_hit[345] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_19_we = addr_hit[324] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_19_we = addr_hit[346] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_20_we = addr_hit[325] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_20_we = addr_hit[347] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_21_we = addr_hit[326] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_21_we = addr_hit[348] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_22_we = addr_hit[327] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_22_we = addr_hit[349] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_23_we = addr_hit[328] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_23_we = addr_hit[350] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_24_we = addr_hit[329] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_24_we = addr_hit[351] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_25_we = addr_hit[330] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_25_we = addr_hit[352] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_26_we = addr_hit[331] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_26_we = addr_hit[353] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_27_we = addr_hit[332] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_27_we = addr_hit[354] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_28_we = addr_hit[333] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_28_we = addr_hit[355] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_29_we = addr_hit[334] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_29_we = addr_hit[356] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_30_we = addr_hit[335] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_30_we = addr_hit[357] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0];
 
-  assign mio_pad_sleep_mode_31_we = addr_hit[336] & reg_we & ~wr_err;
+  assign mio_pad_sleep_mode_31_we = addr_hit[358] & reg_we & ~wr_err;
   assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_status_en_0_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_0_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_status_en_1_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_1_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_1_wd = reg_wdata[1];
 
-  assign dio_pad_sleep_status_en_2_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_2_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_2_wd = reg_wdata[2];
 
-  assign dio_pad_sleep_status_en_3_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_3_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_3_wd = reg_wdata[3];
 
-  assign dio_pad_sleep_status_en_4_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_4_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_4_wd = reg_wdata[4];
 
-  assign dio_pad_sleep_status_en_5_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_5_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_5_wd = reg_wdata[5];
 
-  assign dio_pad_sleep_status_en_6_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_6_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_6_wd = reg_wdata[6];
 
-  assign dio_pad_sleep_status_en_7_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_7_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_7_wd = reg_wdata[7];
 
-  assign dio_pad_sleep_status_en_8_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_8_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_8_wd = reg_wdata[8];
 
-  assign dio_pad_sleep_status_en_9_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_9_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_9_wd = reg_wdata[9];
 
-  assign dio_pad_sleep_status_en_10_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_10_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_10_wd = reg_wdata[10];
 
-  assign dio_pad_sleep_status_en_11_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_11_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_11_wd = reg_wdata[11];
 
-  assign dio_pad_sleep_status_en_12_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_12_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_12_wd = reg_wdata[12];
 
-  assign dio_pad_sleep_status_en_13_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_13_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_13_wd = reg_wdata[13];
 
-  assign dio_pad_sleep_status_en_14_we = addr_hit[337] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_14_we = addr_hit[359] & reg_we & ~wr_err;
   assign dio_pad_sleep_status_en_14_wd = reg_wdata[14];
 
-  assign dio_pad_sleep_regwen_0_we = addr_hit[338] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_15_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_15_wd = reg_wdata[15];
+
+  assign dio_pad_sleep_status_en_16_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_16_wd = reg_wdata[16];
+
+  assign dio_pad_sleep_status_en_17_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_17_wd = reg_wdata[17];
+
+  assign dio_pad_sleep_status_en_18_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_18_wd = reg_wdata[18];
+
+  assign dio_pad_sleep_status_en_19_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_19_wd = reg_wdata[19];
+
+  assign dio_pad_sleep_status_en_20_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_status_en_20_wd = reg_wdata[20];
+
+  assign dio_pad_sleep_regwen_0_we = addr_hit[360] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_1_we = addr_hit[339] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_1_we = addr_hit[361] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_1_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_2_we = addr_hit[340] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_2_we = addr_hit[362] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_2_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_3_we = addr_hit[341] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_3_we = addr_hit[363] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_3_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_4_we = addr_hit[342] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_4_we = addr_hit[364] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_4_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_5_we = addr_hit[343] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_5_we = addr_hit[365] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_5_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_6_we = addr_hit[344] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_6_we = addr_hit[366] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_6_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_7_we = addr_hit[345] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_7_we = addr_hit[367] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_7_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_8_we = addr_hit[346] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_8_we = addr_hit[368] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_8_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_9_we = addr_hit[347] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_9_we = addr_hit[369] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_9_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_10_we = addr_hit[348] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_10_we = addr_hit[370] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_10_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_11_we = addr_hit[349] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_11_we = addr_hit[371] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_11_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_12_we = addr_hit[350] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_12_we = addr_hit[372] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_12_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_13_we = addr_hit[351] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_13_we = addr_hit[373] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_13_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_regwen_14_we = addr_hit[352] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_14_we = addr_hit[374] & reg_we & ~wr_err;
   assign dio_pad_sleep_regwen_14_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_0_we = addr_hit[353] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_15_we = addr_hit[375] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_15_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_regwen_16_we = addr_hit[376] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_16_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_regwen_17_we = addr_hit[377] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_17_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_regwen_18_we = addr_hit[378] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_18_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_regwen_19_we = addr_hit[379] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_19_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_regwen_20_we = addr_hit[380] & reg_we & ~wr_err;
+  assign dio_pad_sleep_regwen_20_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_0_we = addr_hit[381] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_0_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_1_we = addr_hit[354] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_1_we = addr_hit[382] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_1_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_2_we = addr_hit[355] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_2_we = addr_hit[383] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_2_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_3_we = addr_hit[356] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_3_we = addr_hit[384] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_3_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_4_we = addr_hit[357] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_4_we = addr_hit[385] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_4_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_5_we = addr_hit[358] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_5_we = addr_hit[386] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_5_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_6_we = addr_hit[359] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_6_we = addr_hit[387] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_6_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_7_we = addr_hit[360] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_7_we = addr_hit[388] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_7_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_8_we = addr_hit[361] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_8_we = addr_hit[389] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_8_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_9_we = addr_hit[362] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_9_we = addr_hit[390] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_9_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_10_we = addr_hit[363] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_10_we = addr_hit[391] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_10_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_11_we = addr_hit[364] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_11_we = addr_hit[392] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_11_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_12_we = addr_hit[365] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_12_we = addr_hit[393] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_12_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_13_we = addr_hit[366] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_13_we = addr_hit[394] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_13_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_en_14_we = addr_hit[367] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_14_we = addr_hit[395] & reg_we & ~wr_err;
   assign dio_pad_sleep_en_14_wd = reg_wdata[0];
 
-  assign dio_pad_sleep_mode_0_we = addr_hit[368] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_15_we = addr_hit[396] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_15_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_16_we = addr_hit[397] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_16_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_17_we = addr_hit[398] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_17_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_18_we = addr_hit[399] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_18_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_19_we = addr_hit[400] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_19_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_en_20_we = addr_hit[401] & reg_we & ~wr_err;
+  assign dio_pad_sleep_en_20_wd = reg_wdata[0];
+
+  assign dio_pad_sleep_mode_0_we = addr_hit[402] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_1_we = addr_hit[369] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_1_we = addr_hit[403] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_2_we = addr_hit[370] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_2_we = addr_hit[404] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_3_we = addr_hit[371] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_3_we = addr_hit[405] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_4_we = addr_hit[372] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_4_we = addr_hit[406] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_5_we = addr_hit[373] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_5_we = addr_hit[407] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_6_we = addr_hit[374] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_6_we = addr_hit[408] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_7_we = addr_hit[375] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_7_we = addr_hit[409] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_8_we = addr_hit[376] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_8_we = addr_hit[410] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_9_we = addr_hit[377] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_9_we = addr_hit[411] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_10_we = addr_hit[378] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_10_we = addr_hit[412] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_11_we = addr_hit[379] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_11_we = addr_hit[413] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_12_we = addr_hit[380] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_12_we = addr_hit[414] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_13_we = addr_hit[381] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_13_we = addr_hit[415] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0];
 
-  assign dio_pad_sleep_mode_14_we = addr_hit[382] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_14_we = addr_hit[416] & reg_we & ~wr_err;
   assign dio_pad_sleep_mode_14_wd = reg_wdata[1:0];
 
-  assign wkup_detector_regwen_0_we = addr_hit[383] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_15_we = addr_hit[417] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_15_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_mode_16_we = addr_hit[418] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_16_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_mode_17_we = addr_hit[419] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_17_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_mode_18_we = addr_hit[420] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_18_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_mode_19_we = addr_hit[421] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_19_wd = reg_wdata[1:0];
+
+  assign dio_pad_sleep_mode_20_we = addr_hit[422] & reg_we & ~wr_err;
+  assign dio_pad_sleep_mode_20_wd = reg_wdata[1:0];
+
+  assign wkup_detector_regwen_0_we = addr_hit[423] & reg_we & ~wr_err;
   assign wkup_detector_regwen_0_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_1_we = addr_hit[384] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_1_we = addr_hit[424] & reg_we & ~wr_err;
   assign wkup_detector_regwen_1_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_2_we = addr_hit[385] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_2_we = addr_hit[425] & reg_we & ~wr_err;
   assign wkup_detector_regwen_2_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_3_we = addr_hit[386] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_3_we = addr_hit[426] & reg_we & ~wr_err;
   assign wkup_detector_regwen_3_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_4_we = addr_hit[387] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_4_we = addr_hit[427] & reg_we & ~wr_err;
   assign wkup_detector_regwen_4_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_5_we = addr_hit[388] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_5_we = addr_hit[428] & reg_we & ~wr_err;
   assign wkup_detector_regwen_5_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_6_we = addr_hit[389] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_6_we = addr_hit[429] & reg_we & ~wr_err;
   assign wkup_detector_regwen_6_wd = reg_wdata[0];
 
-  assign wkup_detector_regwen_7_we = addr_hit[390] & reg_we & ~wr_err;
+  assign wkup_detector_regwen_7_we = addr_hit[430] & reg_we & ~wr_err;
   assign wkup_detector_regwen_7_wd = reg_wdata[0];
 
-  assign wkup_detector_en_0_we = addr_hit[391] & reg_we & ~wr_err;
+  assign wkup_detector_en_0_we = addr_hit[431] & reg_we & ~wr_err;
   assign wkup_detector_en_0_wd = reg_wdata[0];
 
-  assign wkup_detector_en_1_we = addr_hit[392] & reg_we & ~wr_err;
+  assign wkup_detector_en_1_we = addr_hit[432] & reg_we & ~wr_err;
   assign wkup_detector_en_1_wd = reg_wdata[0];
 
-  assign wkup_detector_en_2_we = addr_hit[393] & reg_we & ~wr_err;
+  assign wkup_detector_en_2_we = addr_hit[433] & reg_we & ~wr_err;
   assign wkup_detector_en_2_wd = reg_wdata[0];
 
-  assign wkup_detector_en_3_we = addr_hit[394] & reg_we & ~wr_err;
+  assign wkup_detector_en_3_we = addr_hit[434] & reg_we & ~wr_err;
   assign wkup_detector_en_3_wd = reg_wdata[0];
 
-  assign wkup_detector_en_4_we = addr_hit[395] & reg_we & ~wr_err;
+  assign wkup_detector_en_4_we = addr_hit[435] & reg_we & ~wr_err;
   assign wkup_detector_en_4_wd = reg_wdata[0];
 
-  assign wkup_detector_en_5_we = addr_hit[396] & reg_we & ~wr_err;
+  assign wkup_detector_en_5_we = addr_hit[436] & reg_we & ~wr_err;
   assign wkup_detector_en_5_wd = reg_wdata[0];
 
-  assign wkup_detector_en_6_we = addr_hit[397] & reg_we & ~wr_err;
+  assign wkup_detector_en_6_we = addr_hit[437] & reg_we & ~wr_err;
   assign wkup_detector_en_6_wd = reg_wdata[0];
 
-  assign wkup_detector_en_7_we = addr_hit[398] & reg_we & ~wr_err;
+  assign wkup_detector_en_7_we = addr_hit[438] & reg_we & ~wr_err;
   assign wkup_detector_en_7_wd = reg_wdata[0];
 
-  assign wkup_detector_0_mode_0_we = addr_hit[399] & reg_we & ~wr_err;
+  assign wkup_detector_0_mode_0_we = addr_hit[439] & reg_we & ~wr_err;
   assign wkup_detector_0_mode_0_wd = reg_wdata[2:0];
 
-  assign wkup_detector_0_filter_0_we = addr_hit[399] & reg_we & ~wr_err;
+  assign wkup_detector_0_filter_0_we = addr_hit[439] & reg_we & ~wr_err;
   assign wkup_detector_0_filter_0_wd = reg_wdata[3];
 
-  assign wkup_detector_0_miodio_0_we = addr_hit[399] & reg_we & ~wr_err;
+  assign wkup_detector_0_miodio_0_we = addr_hit[439] & reg_we & ~wr_err;
   assign wkup_detector_0_miodio_0_wd = reg_wdata[4];
 
-  assign wkup_detector_1_mode_1_we = addr_hit[400] & reg_we & ~wr_err;
+  assign wkup_detector_1_mode_1_we = addr_hit[440] & reg_we & ~wr_err;
   assign wkup_detector_1_mode_1_wd = reg_wdata[2:0];
 
-  assign wkup_detector_1_filter_1_we = addr_hit[400] & reg_we & ~wr_err;
+  assign wkup_detector_1_filter_1_we = addr_hit[440] & reg_we & ~wr_err;
   assign wkup_detector_1_filter_1_wd = reg_wdata[3];
 
-  assign wkup_detector_1_miodio_1_we = addr_hit[400] & reg_we & ~wr_err;
+  assign wkup_detector_1_miodio_1_we = addr_hit[440] & reg_we & ~wr_err;
   assign wkup_detector_1_miodio_1_wd = reg_wdata[4];
 
-  assign wkup_detector_2_mode_2_we = addr_hit[401] & reg_we & ~wr_err;
+  assign wkup_detector_2_mode_2_we = addr_hit[441] & reg_we & ~wr_err;
   assign wkup_detector_2_mode_2_wd = reg_wdata[2:0];
 
-  assign wkup_detector_2_filter_2_we = addr_hit[401] & reg_we & ~wr_err;
+  assign wkup_detector_2_filter_2_we = addr_hit[441] & reg_we & ~wr_err;
   assign wkup_detector_2_filter_2_wd = reg_wdata[3];
 
-  assign wkup_detector_2_miodio_2_we = addr_hit[401] & reg_we & ~wr_err;
+  assign wkup_detector_2_miodio_2_we = addr_hit[441] & reg_we & ~wr_err;
   assign wkup_detector_2_miodio_2_wd = reg_wdata[4];
 
-  assign wkup_detector_3_mode_3_we = addr_hit[402] & reg_we & ~wr_err;
+  assign wkup_detector_3_mode_3_we = addr_hit[442] & reg_we & ~wr_err;
   assign wkup_detector_3_mode_3_wd = reg_wdata[2:0];
 
-  assign wkup_detector_3_filter_3_we = addr_hit[402] & reg_we & ~wr_err;
+  assign wkup_detector_3_filter_3_we = addr_hit[442] & reg_we & ~wr_err;
   assign wkup_detector_3_filter_3_wd = reg_wdata[3];
 
-  assign wkup_detector_3_miodio_3_we = addr_hit[402] & reg_we & ~wr_err;
+  assign wkup_detector_3_miodio_3_we = addr_hit[442] & reg_we & ~wr_err;
   assign wkup_detector_3_miodio_3_wd = reg_wdata[4];
 
-  assign wkup_detector_4_mode_4_we = addr_hit[403] & reg_we & ~wr_err;
+  assign wkup_detector_4_mode_4_we = addr_hit[443] & reg_we & ~wr_err;
   assign wkup_detector_4_mode_4_wd = reg_wdata[2:0];
 
-  assign wkup_detector_4_filter_4_we = addr_hit[403] & reg_we & ~wr_err;
+  assign wkup_detector_4_filter_4_we = addr_hit[443] & reg_we & ~wr_err;
   assign wkup_detector_4_filter_4_wd = reg_wdata[3];
 
-  assign wkup_detector_4_miodio_4_we = addr_hit[403] & reg_we & ~wr_err;
+  assign wkup_detector_4_miodio_4_we = addr_hit[443] & reg_we & ~wr_err;
   assign wkup_detector_4_miodio_4_wd = reg_wdata[4];
 
-  assign wkup_detector_5_mode_5_we = addr_hit[404] & reg_we & ~wr_err;
+  assign wkup_detector_5_mode_5_we = addr_hit[444] & reg_we & ~wr_err;
   assign wkup_detector_5_mode_5_wd = reg_wdata[2:0];
 
-  assign wkup_detector_5_filter_5_we = addr_hit[404] & reg_we & ~wr_err;
+  assign wkup_detector_5_filter_5_we = addr_hit[444] & reg_we & ~wr_err;
   assign wkup_detector_5_filter_5_wd = reg_wdata[3];
 
-  assign wkup_detector_5_miodio_5_we = addr_hit[404] & reg_we & ~wr_err;
+  assign wkup_detector_5_miodio_5_we = addr_hit[444] & reg_we & ~wr_err;
   assign wkup_detector_5_miodio_5_wd = reg_wdata[4];
 
-  assign wkup_detector_6_mode_6_we = addr_hit[405] & reg_we & ~wr_err;
+  assign wkup_detector_6_mode_6_we = addr_hit[445] & reg_we & ~wr_err;
   assign wkup_detector_6_mode_6_wd = reg_wdata[2:0];
 
-  assign wkup_detector_6_filter_6_we = addr_hit[405] & reg_we & ~wr_err;
+  assign wkup_detector_6_filter_6_we = addr_hit[445] & reg_we & ~wr_err;
   assign wkup_detector_6_filter_6_wd = reg_wdata[3];
 
-  assign wkup_detector_6_miodio_6_we = addr_hit[405] & reg_we & ~wr_err;
+  assign wkup_detector_6_miodio_6_we = addr_hit[445] & reg_we & ~wr_err;
   assign wkup_detector_6_miodio_6_wd = reg_wdata[4];
 
-  assign wkup_detector_7_mode_7_we = addr_hit[406] & reg_we & ~wr_err;
+  assign wkup_detector_7_mode_7_we = addr_hit[446] & reg_we & ~wr_err;
   assign wkup_detector_7_mode_7_wd = reg_wdata[2:0];
 
-  assign wkup_detector_7_filter_7_we = addr_hit[406] & reg_we & ~wr_err;
+  assign wkup_detector_7_filter_7_we = addr_hit[446] & reg_we & ~wr_err;
   assign wkup_detector_7_filter_7_wd = reg_wdata[3];
 
-  assign wkup_detector_7_miodio_7_we = addr_hit[406] & reg_we & ~wr_err;
+  assign wkup_detector_7_miodio_7_we = addr_hit[446] & reg_we & ~wr_err;
   assign wkup_detector_7_miodio_7_wd = reg_wdata[4];
 
-  assign wkup_detector_cnt_th_0_we = addr_hit[407] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_0_we = addr_hit[447] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_0_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_1_we = addr_hit[408] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_1_we = addr_hit[448] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_1_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_2_we = addr_hit[409] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_2_we = addr_hit[449] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_2_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_3_we = addr_hit[410] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_3_we = addr_hit[450] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_3_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_4_we = addr_hit[411] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_4_we = addr_hit[451] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_4_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_5_we = addr_hit[412] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_5_we = addr_hit[452] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_5_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_6_we = addr_hit[413] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_6_we = addr_hit[453] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_6_wd = reg_wdata[7:0];
 
-  assign wkup_detector_cnt_th_7_we = addr_hit[414] & reg_we & ~wr_err;
+  assign wkup_detector_cnt_th_7_we = addr_hit[454] & reg_we & ~wr_err;
   assign wkup_detector_cnt_th_7_wd = reg_wdata[7:0];
 
-  assign wkup_detector_padsel_0_we = addr_hit[415] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_0_we = addr_hit[455] & reg_we & ~wr_err;
   assign wkup_detector_padsel_0_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_1_we = addr_hit[416] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_1_we = addr_hit[456] & reg_we & ~wr_err;
   assign wkup_detector_padsel_1_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_2_we = addr_hit[417] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_2_we = addr_hit[457] & reg_we & ~wr_err;
   assign wkup_detector_padsel_2_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_3_we = addr_hit[418] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_3_we = addr_hit[458] & reg_we & ~wr_err;
   assign wkup_detector_padsel_3_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_4_we = addr_hit[419] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_4_we = addr_hit[459] & reg_we & ~wr_err;
   assign wkup_detector_padsel_4_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_5_we = addr_hit[420] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_5_we = addr_hit[460] & reg_we & ~wr_err;
   assign wkup_detector_padsel_5_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_6_we = addr_hit[421] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_6_we = addr_hit[461] & reg_we & ~wr_err;
   assign wkup_detector_padsel_6_wd = reg_wdata[5:0];
 
-  assign wkup_detector_padsel_7_we = addr_hit[422] & reg_we & ~wr_err;
+  assign wkup_detector_padsel_7_we = addr_hit[462] & reg_we & ~wr_err;
   assign wkup_detector_padsel_7_wd = reg_wdata[5:0];
 
-  assign wkup_cause_cause_0_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_0_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_0_wd = reg_wdata[0];
-  assign wkup_cause_cause_0_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_0_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_1_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_1_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_1_wd = reg_wdata[1];
-  assign wkup_cause_cause_1_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_1_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_2_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_2_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_2_wd = reg_wdata[2];
-  assign wkup_cause_cause_2_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_2_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_3_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_3_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_3_wd = reg_wdata[3];
-  assign wkup_cause_cause_3_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_3_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_4_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_4_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_4_wd = reg_wdata[4];
-  assign wkup_cause_cause_4_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_4_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_5_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_5_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_5_wd = reg_wdata[5];
-  assign wkup_cause_cause_5_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_5_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_6_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_6_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_6_wd = reg_wdata[6];
-  assign wkup_cause_cause_6_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_6_re = addr_hit[463] && reg_re;
 
-  assign wkup_cause_cause_7_we = addr_hit[423] & reg_we & ~wr_err;
+  assign wkup_cause_cause_7_we = addr_hit[463] & reg_we & ~wr_err;
   assign wkup_cause_cause_7_wd = reg_wdata[7];
-  assign wkup_cause_cause_7_re = addr_hit[423] && reg_re;
+  assign wkup_cause_cause_7_re = addr_hit[463] && reg_re;
 
   // Read data return
   always_comb begin
@@ -16890,802 +18434,890 @@
       end
 
       addr_hit[41]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_0_qs;
+        reg_rdata_next[0] = mio_periph_insel_regwen_41_qs;
       end
 
       addr_hit[42]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_1_qs;
+        reg_rdata_next[0] = mio_periph_insel_regwen_42_qs;
       end
 
       addr_hit[43]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_2_qs;
+        reg_rdata_next[0] = mio_periph_insel_regwen_43_qs;
       end
 
       addr_hit[44]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_3_qs;
+        reg_rdata_next[0] = mio_periph_insel_regwen_44_qs;
       end
 
       addr_hit[45]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_4_qs;
+        reg_rdata_next[0] = mio_periph_insel_regwen_45_qs;
       end
 
       addr_hit[46]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_5_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_0_qs;
       end
 
       addr_hit[47]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_6_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_1_qs;
       end
 
       addr_hit[48]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_7_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_2_qs;
       end
 
       addr_hit[49]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_8_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_3_qs;
       end
 
       addr_hit[50]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_9_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_4_qs;
       end
 
       addr_hit[51]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_10_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_5_qs;
       end
 
       addr_hit[52]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_11_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_6_qs;
       end
 
       addr_hit[53]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_12_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_7_qs;
       end
 
       addr_hit[54]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_13_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_8_qs;
       end
 
       addr_hit[55]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_14_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_9_qs;
       end
 
       addr_hit[56]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_15_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_10_qs;
       end
 
       addr_hit[57]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_16_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_11_qs;
       end
 
       addr_hit[58]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_17_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_12_qs;
       end
 
       addr_hit[59]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_18_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_13_qs;
       end
 
       addr_hit[60]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_19_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_14_qs;
       end
 
       addr_hit[61]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_20_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_15_qs;
       end
 
       addr_hit[62]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_21_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_16_qs;
       end
 
       addr_hit[63]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_22_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_17_qs;
       end
 
       addr_hit[64]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_23_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_18_qs;
       end
 
       addr_hit[65]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_24_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_19_qs;
       end
 
       addr_hit[66]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_25_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_20_qs;
       end
 
       addr_hit[67]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_26_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_21_qs;
       end
 
       addr_hit[68]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_27_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_22_qs;
       end
 
       addr_hit[69]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_28_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_23_qs;
       end
 
       addr_hit[70]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_29_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_24_qs;
       end
 
       addr_hit[71]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_30_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_25_qs;
       end
 
       addr_hit[72]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_31_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_26_qs;
       end
 
       addr_hit[73]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_32_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_27_qs;
       end
 
       addr_hit[74]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_33_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_28_qs;
       end
 
       addr_hit[75]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_34_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_29_qs;
       end
 
       addr_hit[76]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_35_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_30_qs;
       end
 
       addr_hit[77]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_36_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_31_qs;
       end
 
       addr_hit[78]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_37_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_32_qs;
       end
 
       addr_hit[79]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_38_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_33_qs;
       end
 
       addr_hit[80]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_39_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_34_qs;
       end
 
       addr_hit[81]: begin
-        reg_rdata_next[5:0] = mio_periph_insel_40_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_35_qs;
       end
 
       addr_hit[82]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_0_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_36_qs;
       end
 
       addr_hit[83]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_1_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_37_qs;
       end
 
       addr_hit[84]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_2_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_38_qs;
       end
 
       addr_hit[85]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_3_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_39_qs;
       end
 
       addr_hit[86]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_4_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_40_qs;
       end
 
       addr_hit[87]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_5_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_41_qs;
       end
 
       addr_hit[88]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_6_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_42_qs;
       end
 
       addr_hit[89]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_7_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_43_qs;
       end
 
       addr_hit[90]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_8_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_44_qs;
       end
 
       addr_hit[91]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_9_qs;
+        reg_rdata_next[5:0] = mio_periph_insel_45_qs;
       end
 
       addr_hit[92]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_10_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_0_qs;
       end
 
       addr_hit[93]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_11_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_1_qs;
       end
 
       addr_hit[94]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_12_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_2_qs;
       end
 
       addr_hit[95]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_13_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_3_qs;
       end
 
       addr_hit[96]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_14_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_4_qs;
       end
 
       addr_hit[97]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_15_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_5_qs;
       end
 
       addr_hit[98]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_16_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_6_qs;
       end
 
       addr_hit[99]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_17_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_7_qs;
       end
 
       addr_hit[100]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_18_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_8_qs;
       end
 
       addr_hit[101]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_19_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_9_qs;
       end
 
       addr_hit[102]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_20_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_10_qs;
       end
 
       addr_hit[103]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_21_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_11_qs;
       end
 
       addr_hit[104]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_22_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_12_qs;
       end
 
       addr_hit[105]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_23_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_13_qs;
       end
 
       addr_hit[106]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_24_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_14_qs;
       end
 
       addr_hit[107]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_25_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_15_qs;
       end
 
       addr_hit[108]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_26_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_16_qs;
       end
 
       addr_hit[109]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_27_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_17_qs;
       end
 
       addr_hit[110]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_28_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_18_qs;
       end
 
       addr_hit[111]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_29_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_19_qs;
       end
 
       addr_hit[112]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_30_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_20_qs;
       end
 
       addr_hit[113]: begin
-        reg_rdata_next[0] = mio_outsel_regwen_31_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_21_qs;
       end
 
       addr_hit[114]: begin
-        reg_rdata_next[5:0] = mio_outsel_0_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_22_qs;
       end
 
       addr_hit[115]: begin
-        reg_rdata_next[5:0] = mio_outsel_1_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_23_qs;
       end
 
       addr_hit[116]: begin
-        reg_rdata_next[5:0] = mio_outsel_2_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_24_qs;
       end
 
       addr_hit[117]: begin
-        reg_rdata_next[5:0] = mio_outsel_3_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_25_qs;
       end
 
       addr_hit[118]: begin
-        reg_rdata_next[5:0] = mio_outsel_4_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_26_qs;
       end
 
       addr_hit[119]: begin
-        reg_rdata_next[5:0] = mio_outsel_5_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_27_qs;
       end
 
       addr_hit[120]: begin
-        reg_rdata_next[5:0] = mio_outsel_6_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_28_qs;
       end
 
       addr_hit[121]: begin
-        reg_rdata_next[5:0] = mio_outsel_7_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_29_qs;
       end
 
       addr_hit[122]: begin
-        reg_rdata_next[5:0] = mio_outsel_8_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_30_qs;
       end
 
       addr_hit[123]: begin
-        reg_rdata_next[5:0] = mio_outsel_9_qs;
+        reg_rdata_next[0] = mio_outsel_regwen_31_qs;
       end
 
       addr_hit[124]: begin
-        reg_rdata_next[5:0] = mio_outsel_10_qs;
+        reg_rdata_next[5:0] = mio_outsel_0_qs;
       end
 
       addr_hit[125]: begin
-        reg_rdata_next[5:0] = mio_outsel_11_qs;
+        reg_rdata_next[5:0] = mio_outsel_1_qs;
       end
 
       addr_hit[126]: begin
-        reg_rdata_next[5:0] = mio_outsel_12_qs;
+        reg_rdata_next[5:0] = mio_outsel_2_qs;
       end
 
       addr_hit[127]: begin
-        reg_rdata_next[5:0] = mio_outsel_13_qs;
+        reg_rdata_next[5:0] = mio_outsel_3_qs;
       end
 
       addr_hit[128]: begin
-        reg_rdata_next[5:0] = mio_outsel_14_qs;
+        reg_rdata_next[5:0] = mio_outsel_4_qs;
       end
 
       addr_hit[129]: begin
-        reg_rdata_next[5:0] = mio_outsel_15_qs;
+        reg_rdata_next[5:0] = mio_outsel_5_qs;
       end
 
       addr_hit[130]: begin
-        reg_rdata_next[5:0] = mio_outsel_16_qs;
+        reg_rdata_next[5:0] = mio_outsel_6_qs;
       end
 
       addr_hit[131]: begin
-        reg_rdata_next[5:0] = mio_outsel_17_qs;
+        reg_rdata_next[5:0] = mio_outsel_7_qs;
       end
 
       addr_hit[132]: begin
-        reg_rdata_next[5:0] = mio_outsel_18_qs;
+        reg_rdata_next[5:0] = mio_outsel_8_qs;
       end
 
       addr_hit[133]: begin
-        reg_rdata_next[5:0] = mio_outsel_19_qs;
+        reg_rdata_next[5:0] = mio_outsel_9_qs;
       end
 
       addr_hit[134]: begin
-        reg_rdata_next[5:0] = mio_outsel_20_qs;
+        reg_rdata_next[5:0] = mio_outsel_10_qs;
       end
 
       addr_hit[135]: begin
-        reg_rdata_next[5:0] = mio_outsel_21_qs;
+        reg_rdata_next[5:0] = mio_outsel_11_qs;
       end
 
       addr_hit[136]: begin
-        reg_rdata_next[5:0] = mio_outsel_22_qs;
+        reg_rdata_next[5:0] = mio_outsel_12_qs;
       end
 
       addr_hit[137]: begin
-        reg_rdata_next[5:0] = mio_outsel_23_qs;
+        reg_rdata_next[5:0] = mio_outsel_13_qs;
       end
 
       addr_hit[138]: begin
-        reg_rdata_next[5:0] = mio_outsel_24_qs;
+        reg_rdata_next[5:0] = mio_outsel_14_qs;
       end
 
       addr_hit[139]: begin
-        reg_rdata_next[5:0] = mio_outsel_25_qs;
+        reg_rdata_next[5:0] = mio_outsel_15_qs;
       end
 
       addr_hit[140]: begin
-        reg_rdata_next[5:0] = mio_outsel_26_qs;
+        reg_rdata_next[5:0] = mio_outsel_16_qs;
       end
 
       addr_hit[141]: begin
-        reg_rdata_next[5:0] = mio_outsel_27_qs;
+        reg_rdata_next[5:0] = mio_outsel_17_qs;
       end
 
       addr_hit[142]: begin
-        reg_rdata_next[5:0] = mio_outsel_28_qs;
+        reg_rdata_next[5:0] = mio_outsel_18_qs;
       end
 
       addr_hit[143]: begin
-        reg_rdata_next[5:0] = mio_outsel_29_qs;
+        reg_rdata_next[5:0] = mio_outsel_19_qs;
       end
 
       addr_hit[144]: begin
-        reg_rdata_next[5:0] = mio_outsel_30_qs;
+        reg_rdata_next[5:0] = mio_outsel_20_qs;
       end
 
       addr_hit[145]: begin
-        reg_rdata_next[5:0] = mio_outsel_31_qs;
+        reg_rdata_next[5:0] = mio_outsel_21_qs;
       end
 
       addr_hit[146]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
+        reg_rdata_next[5:0] = mio_outsel_22_qs;
       end
 
       addr_hit[147]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
+        reg_rdata_next[5:0] = mio_outsel_23_qs;
       end
 
       addr_hit[148]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
+        reg_rdata_next[5:0] = mio_outsel_24_qs;
       end
 
       addr_hit[149]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
+        reg_rdata_next[5:0] = mio_outsel_25_qs;
       end
 
       addr_hit[150]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
+        reg_rdata_next[5:0] = mio_outsel_26_qs;
       end
 
       addr_hit[151]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
+        reg_rdata_next[5:0] = mio_outsel_27_qs;
       end
 
       addr_hit[152]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
+        reg_rdata_next[5:0] = mio_outsel_28_qs;
       end
 
       addr_hit[153]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
+        reg_rdata_next[5:0] = mio_outsel_29_qs;
       end
 
       addr_hit[154]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
+        reg_rdata_next[5:0] = mio_outsel_30_qs;
       end
 
       addr_hit[155]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
+        reg_rdata_next[5:0] = mio_outsel_31_qs;
       end
 
       addr_hit[156]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_0_qs;
       end
 
       addr_hit[157]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_1_qs;
       end
 
       addr_hit[158]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_2_qs;
       end
 
       addr_hit[159]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_3_qs;
       end
 
       addr_hit[160]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_4_qs;
       end
 
       addr_hit[161]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_5_qs;
       end
 
       addr_hit[162]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_6_qs;
       end
 
       addr_hit[163]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_7_qs;
       end
 
       addr_hit[164]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_8_qs;
       end
 
       addr_hit[165]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_9_qs;
       end
 
       addr_hit[166]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_10_qs;
       end
 
       addr_hit[167]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_11_qs;
       end
 
       addr_hit[168]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_12_qs;
       end
 
       addr_hit[169]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_13_qs;
       end
 
       addr_hit[170]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_14_qs;
       end
 
       addr_hit[171]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_15_qs;
       end
 
       addr_hit[172]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_16_qs;
       end
 
       addr_hit[173]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_17_qs;
       end
 
       addr_hit[174]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_18_qs;
       end
 
       addr_hit[175]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_19_qs;
       end
 
       addr_hit[176]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_20_qs;
       end
 
       addr_hit[177]: begin
-        reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_21_qs;
       end
 
       addr_hit[178]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_0_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_22_qs;
       end
 
       addr_hit[179]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_1_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_23_qs;
       end
 
       addr_hit[180]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_2_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_24_qs;
       end
 
       addr_hit[181]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_3_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_25_qs;
       end
 
       addr_hit[182]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_4_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_26_qs;
       end
 
       addr_hit[183]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_5_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_27_qs;
       end
 
       addr_hit[184]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_6_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_28_qs;
       end
 
       addr_hit[185]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_7_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_29_qs;
       end
 
       addr_hit[186]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_8_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_30_qs;
       end
 
       addr_hit[187]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_9_qs;
+        reg_rdata_next[0] = mio_pad_attr_regwen_31_qs;
       end
 
       addr_hit[188]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_10_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_0_qs;
       end
 
       addr_hit[189]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_11_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_1_qs;
       end
 
       addr_hit[190]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_12_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_2_qs;
       end
 
       addr_hit[191]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_13_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_3_qs;
       end
 
       addr_hit[192]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_14_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_4_qs;
       end
 
       addr_hit[193]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_15_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_5_qs;
       end
 
       addr_hit[194]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_16_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_6_qs;
       end
 
       addr_hit[195]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_17_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_7_qs;
       end
 
       addr_hit[196]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_18_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_8_qs;
       end
 
       addr_hit[197]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_19_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_9_qs;
       end
 
       addr_hit[198]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_20_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_10_qs;
       end
 
       addr_hit[199]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_21_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_11_qs;
       end
 
       addr_hit[200]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_22_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_12_qs;
       end
 
       addr_hit[201]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_23_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_13_qs;
       end
 
       addr_hit[202]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_24_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_14_qs;
       end
 
       addr_hit[203]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_25_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_15_qs;
       end
 
       addr_hit[204]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_26_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_16_qs;
       end
 
       addr_hit[205]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_27_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_17_qs;
       end
 
       addr_hit[206]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_28_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_18_qs;
       end
 
       addr_hit[207]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_29_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_19_qs;
       end
 
       addr_hit[208]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_30_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_20_qs;
       end
 
       addr_hit[209]: begin
-        reg_rdata_next[9:0] = mio_pad_attr_31_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_21_qs;
       end
 
       addr_hit[210]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_22_qs;
       end
 
       addr_hit[211]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_23_qs;
       end
 
       addr_hit[212]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_24_qs;
       end
 
       addr_hit[213]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_25_qs;
       end
 
       addr_hit[214]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_26_qs;
       end
 
       addr_hit[215]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_27_qs;
       end
 
       addr_hit[216]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_28_qs;
       end
 
       addr_hit[217]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_29_qs;
       end
 
       addr_hit[218]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_30_qs;
       end
 
       addr_hit[219]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
+        reg_rdata_next[9:0] = mio_pad_attr_31_qs;
       end
 
       addr_hit[220]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_0_qs;
       end
 
       addr_hit[221]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_1_qs;
       end
 
       addr_hit[222]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_2_qs;
       end
 
       addr_hit[223]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_3_qs;
       end
 
       addr_hit[224]: begin
-        reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_4_qs;
       end
 
       addr_hit[225]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_0_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_5_qs;
       end
 
       addr_hit[226]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_1_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_6_qs;
       end
 
       addr_hit[227]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_2_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_7_qs;
       end
 
       addr_hit[228]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_3_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_8_qs;
       end
 
       addr_hit[229]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_4_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_9_qs;
       end
 
       addr_hit[230]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_5_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_10_qs;
       end
 
       addr_hit[231]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_6_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_11_qs;
       end
 
       addr_hit[232]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_7_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_12_qs;
       end
 
       addr_hit[233]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_8_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_13_qs;
       end
 
       addr_hit[234]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_9_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_14_qs;
       end
 
       addr_hit[235]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_10_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_15_qs;
       end
 
       addr_hit[236]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_11_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_16_qs;
       end
 
       addr_hit[237]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_12_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_17_qs;
       end
 
       addr_hit[238]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_13_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_18_qs;
       end
 
       addr_hit[239]: begin
-        reg_rdata_next[9:0] = dio_pad_attr_14_qs;
+        reg_rdata_next[0] = dio_pad_attr_regwen_19_qs;
       end
 
       addr_hit[240]: begin
+        reg_rdata_next[0] = dio_pad_attr_regwen_20_qs;
+      end
+
+      addr_hit[241]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_0_qs;
+      end
+
+      addr_hit[242]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_1_qs;
+      end
+
+      addr_hit[243]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_2_qs;
+      end
+
+      addr_hit[244]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_3_qs;
+      end
+
+      addr_hit[245]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_4_qs;
+      end
+
+      addr_hit[246]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_5_qs;
+      end
+
+      addr_hit[247]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_6_qs;
+      end
+
+      addr_hit[248]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_7_qs;
+      end
+
+      addr_hit[249]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_8_qs;
+      end
+
+      addr_hit[250]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_9_qs;
+      end
+
+      addr_hit[251]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_10_qs;
+      end
+
+      addr_hit[252]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_11_qs;
+      end
+
+      addr_hit[253]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_12_qs;
+      end
+
+      addr_hit[254]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_13_qs;
+      end
+
+      addr_hit[255]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_14_qs;
+      end
+
+      addr_hit[256]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_15_qs;
+      end
+
+      addr_hit[257]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_16_qs;
+      end
+
+      addr_hit[258]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_17_qs;
+      end
+
+      addr_hit[259]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_18_qs;
+      end
+
+      addr_hit[260]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_19_qs;
+      end
+
+      addr_hit[261]: begin
+        reg_rdata_next[9:0] = dio_pad_attr_20_qs;
+      end
+
+      addr_hit[262]: begin
         reg_rdata_next[0] = mio_pad_sleep_status_en_0_qs;
         reg_rdata_next[1] = mio_pad_sleep_status_en_1_qs;
         reg_rdata_next[2] = mio_pad_sleep_status_en_2_qs;
@@ -17720,391 +19352,391 @@
         reg_rdata_next[31] = mio_pad_sleep_status_en_31_qs;
       end
 
-      addr_hit[241]: begin
+      addr_hit[263]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs;
       end
 
-      addr_hit[242]: begin
+      addr_hit[264]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs;
       end
 
-      addr_hit[243]: begin
+      addr_hit[265]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs;
       end
 
-      addr_hit[244]: begin
+      addr_hit[266]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs;
       end
 
-      addr_hit[245]: begin
+      addr_hit[267]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs;
       end
 
-      addr_hit[246]: begin
+      addr_hit[268]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs;
       end
 
-      addr_hit[247]: begin
+      addr_hit[269]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs;
       end
 
-      addr_hit[248]: begin
+      addr_hit[270]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs;
       end
 
-      addr_hit[249]: begin
+      addr_hit[271]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs;
       end
 
-      addr_hit[250]: begin
+      addr_hit[272]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs;
       end
 
-      addr_hit[251]: begin
+      addr_hit[273]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs;
       end
 
-      addr_hit[252]: begin
+      addr_hit[274]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs;
       end
 
-      addr_hit[253]: begin
+      addr_hit[275]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs;
       end
 
-      addr_hit[254]: begin
+      addr_hit[276]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs;
       end
 
-      addr_hit[255]: begin
+      addr_hit[277]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs;
       end
 
-      addr_hit[256]: begin
+      addr_hit[278]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs;
       end
 
-      addr_hit[257]: begin
+      addr_hit[279]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs;
       end
 
-      addr_hit[258]: begin
+      addr_hit[280]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs;
       end
 
-      addr_hit[259]: begin
+      addr_hit[281]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs;
       end
 
-      addr_hit[260]: begin
+      addr_hit[282]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs;
       end
 
-      addr_hit[261]: begin
+      addr_hit[283]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs;
       end
 
-      addr_hit[262]: begin
+      addr_hit[284]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs;
       end
 
-      addr_hit[263]: begin
+      addr_hit[285]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs;
       end
 
-      addr_hit[264]: begin
+      addr_hit[286]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs;
       end
 
-      addr_hit[265]: begin
+      addr_hit[287]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs;
       end
 
-      addr_hit[266]: begin
+      addr_hit[288]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs;
       end
 
-      addr_hit[267]: begin
+      addr_hit[289]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs;
       end
 
-      addr_hit[268]: begin
+      addr_hit[290]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs;
       end
 
-      addr_hit[269]: begin
+      addr_hit[291]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs;
       end
 
-      addr_hit[270]: begin
+      addr_hit[292]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs;
       end
 
-      addr_hit[271]: begin
+      addr_hit[293]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs;
       end
 
-      addr_hit[272]: begin
+      addr_hit[294]: begin
         reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs;
       end
 
-      addr_hit[273]: begin
+      addr_hit[295]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_0_qs;
       end
 
-      addr_hit[274]: begin
+      addr_hit[296]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_1_qs;
       end
 
-      addr_hit[275]: begin
+      addr_hit[297]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_2_qs;
       end
 
-      addr_hit[276]: begin
+      addr_hit[298]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_3_qs;
       end
 
-      addr_hit[277]: begin
+      addr_hit[299]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_4_qs;
       end
 
-      addr_hit[278]: begin
+      addr_hit[300]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_5_qs;
       end
 
-      addr_hit[279]: begin
+      addr_hit[301]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_6_qs;
       end
 
-      addr_hit[280]: begin
+      addr_hit[302]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_7_qs;
       end
 
-      addr_hit[281]: begin
+      addr_hit[303]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_8_qs;
       end
 
-      addr_hit[282]: begin
+      addr_hit[304]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_9_qs;
       end
 
-      addr_hit[283]: begin
+      addr_hit[305]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_10_qs;
       end
 
-      addr_hit[284]: begin
+      addr_hit[306]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_11_qs;
       end
 
-      addr_hit[285]: begin
+      addr_hit[307]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_12_qs;
       end
 
-      addr_hit[286]: begin
+      addr_hit[308]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_13_qs;
       end
 
-      addr_hit[287]: begin
+      addr_hit[309]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_14_qs;
       end
 
-      addr_hit[288]: begin
+      addr_hit[310]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_15_qs;
       end
 
-      addr_hit[289]: begin
+      addr_hit[311]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_16_qs;
       end
 
-      addr_hit[290]: begin
+      addr_hit[312]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_17_qs;
       end
 
-      addr_hit[291]: begin
+      addr_hit[313]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_18_qs;
       end
 
-      addr_hit[292]: begin
+      addr_hit[314]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_19_qs;
       end
 
-      addr_hit[293]: begin
+      addr_hit[315]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_20_qs;
       end
 
-      addr_hit[294]: begin
+      addr_hit[316]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_21_qs;
       end
 
-      addr_hit[295]: begin
+      addr_hit[317]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_22_qs;
       end
 
-      addr_hit[296]: begin
+      addr_hit[318]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_23_qs;
       end
 
-      addr_hit[297]: begin
+      addr_hit[319]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_24_qs;
       end
 
-      addr_hit[298]: begin
+      addr_hit[320]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_25_qs;
       end
 
-      addr_hit[299]: begin
+      addr_hit[321]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_26_qs;
       end
 
-      addr_hit[300]: begin
+      addr_hit[322]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_27_qs;
       end
 
-      addr_hit[301]: begin
+      addr_hit[323]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_28_qs;
       end
 
-      addr_hit[302]: begin
+      addr_hit[324]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_29_qs;
       end
 
-      addr_hit[303]: begin
+      addr_hit[325]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_30_qs;
       end
 
-      addr_hit[304]: begin
+      addr_hit[326]: begin
         reg_rdata_next[0] = mio_pad_sleep_en_31_qs;
       end
 
-      addr_hit[305]: begin
+      addr_hit[327]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs;
       end
 
-      addr_hit[306]: begin
+      addr_hit[328]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs;
       end
 
-      addr_hit[307]: begin
+      addr_hit[329]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs;
       end
 
-      addr_hit[308]: begin
+      addr_hit[330]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs;
       end
 
-      addr_hit[309]: begin
+      addr_hit[331]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs;
       end
 
-      addr_hit[310]: begin
+      addr_hit[332]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs;
       end
 
-      addr_hit[311]: begin
+      addr_hit[333]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs;
       end
 
-      addr_hit[312]: begin
+      addr_hit[334]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs;
       end
 
-      addr_hit[313]: begin
+      addr_hit[335]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs;
       end
 
-      addr_hit[314]: begin
+      addr_hit[336]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs;
       end
 
-      addr_hit[315]: begin
+      addr_hit[337]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs;
       end
 
-      addr_hit[316]: begin
+      addr_hit[338]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs;
       end
 
-      addr_hit[317]: begin
+      addr_hit[339]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs;
       end
 
-      addr_hit[318]: begin
+      addr_hit[340]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs;
       end
 
-      addr_hit[319]: begin
+      addr_hit[341]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs;
       end
 
-      addr_hit[320]: begin
+      addr_hit[342]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs;
       end
 
-      addr_hit[321]: begin
+      addr_hit[343]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs;
       end
 
-      addr_hit[322]: begin
+      addr_hit[344]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs;
       end
 
-      addr_hit[323]: begin
+      addr_hit[345]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs;
       end
 
-      addr_hit[324]: begin
+      addr_hit[346]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs;
       end
 
-      addr_hit[325]: begin
+      addr_hit[347]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs;
       end
 
-      addr_hit[326]: begin
+      addr_hit[348]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs;
       end
 
-      addr_hit[327]: begin
+      addr_hit[349]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs;
       end
 
-      addr_hit[328]: begin
+      addr_hit[350]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs;
       end
 
-      addr_hit[329]: begin
+      addr_hit[351]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs;
       end
 
-      addr_hit[330]: begin
+      addr_hit[352]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs;
       end
 
-      addr_hit[331]: begin
+      addr_hit[353]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs;
       end
 
-      addr_hit[332]: begin
+      addr_hit[354]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs;
       end
 
-      addr_hit[333]: begin
+      addr_hit[355]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs;
       end
 
-      addr_hit[334]: begin
+      addr_hit[356]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs;
       end
 
-      addr_hit[335]: begin
+      addr_hit[357]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs;
       end
 
-      addr_hit[336]: begin
+      addr_hit[358]: begin
         reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs;
       end
 
-      addr_hit[337]: begin
+      addr_hit[359]: begin
         reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs;
         reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs;
         reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs;
@@ -18120,365 +19752,443 @@
         reg_rdata_next[12] = dio_pad_sleep_status_en_12_qs;
         reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs;
         reg_rdata_next[14] = dio_pad_sleep_status_en_14_qs;
-      end
-
-      addr_hit[338]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
-      end
-
-      addr_hit[339]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
-      end
-
-      addr_hit[340]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
-      end
-
-      addr_hit[341]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
-      end
-
-      addr_hit[342]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
-      end
-
-      addr_hit[343]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
-      end
-
-      addr_hit[344]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
-      end
-
-      addr_hit[345]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
-      end
-
-      addr_hit[346]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
-      end
-
-      addr_hit[347]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
-      end
-
-      addr_hit[348]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
-      end
-
-      addr_hit[349]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
-      end
-
-      addr_hit[350]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
-      end
-
-      addr_hit[351]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
-      end
-
-      addr_hit[352]: begin
-        reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
-      end
-
-      addr_hit[353]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
-      end
-
-      addr_hit[354]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
-      end
-
-      addr_hit[355]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
-      end
-
-      addr_hit[356]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
-      end
-
-      addr_hit[357]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
-      end
-
-      addr_hit[358]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
-      end
-
-      addr_hit[359]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
+        reg_rdata_next[15] = dio_pad_sleep_status_en_15_qs;
+        reg_rdata_next[16] = dio_pad_sleep_status_en_16_qs;
+        reg_rdata_next[17] = dio_pad_sleep_status_en_17_qs;
+        reg_rdata_next[18] = dio_pad_sleep_status_en_18_qs;
+        reg_rdata_next[19] = dio_pad_sleep_status_en_19_qs;
+        reg_rdata_next[20] = dio_pad_sleep_status_en_20_qs;
       end
 
       addr_hit[360]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs;
       end
 
       addr_hit[361]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs;
       end
 
       addr_hit[362]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs;
       end
 
       addr_hit[363]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs;
       end
 
       addr_hit[364]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs;
       end
 
       addr_hit[365]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs;
       end
 
       addr_hit[366]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs;
       end
 
       addr_hit[367]: begin
-        reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs;
       end
 
       addr_hit[368]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs;
       end
 
       addr_hit[369]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs;
       end
 
       addr_hit[370]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs;
       end
 
       addr_hit[371]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs;
       end
 
       addr_hit[372]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs;
       end
 
       addr_hit[373]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs;
       end
 
       addr_hit[374]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_14_qs;
       end
 
       addr_hit[375]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_15_qs;
       end
 
       addr_hit[376]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_16_qs;
       end
 
       addr_hit[377]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_17_qs;
       end
 
       addr_hit[378]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_18_qs;
       end
 
       addr_hit[379]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_19_qs;
       end
 
       addr_hit[380]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
+        reg_rdata_next[0] = dio_pad_sleep_regwen_20_qs;
       end
 
       addr_hit[381]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_0_qs;
       end
 
       addr_hit[382]: begin
-        reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_1_qs;
       end
 
       addr_hit[383]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_2_qs;
       end
 
       addr_hit[384]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_3_qs;
       end
 
       addr_hit[385]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_2_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_4_qs;
       end
 
       addr_hit[386]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_3_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_5_qs;
       end
 
       addr_hit[387]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_4_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_6_qs;
       end
 
       addr_hit[388]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_5_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_7_qs;
       end
 
       addr_hit[389]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_6_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_8_qs;
       end
 
       addr_hit[390]: begin
-        reg_rdata_next[0] = wkup_detector_regwen_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_9_qs;
       end
 
       addr_hit[391]: begin
-        reg_rdata_next[0] = wkup_detector_en_0_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_10_qs;
       end
 
       addr_hit[392]: begin
-        reg_rdata_next[0] = wkup_detector_en_1_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_11_qs;
       end
 
       addr_hit[393]: begin
-        reg_rdata_next[0] = wkup_detector_en_2_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_12_qs;
       end
 
       addr_hit[394]: begin
-        reg_rdata_next[0] = wkup_detector_en_3_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_13_qs;
       end
 
       addr_hit[395]: begin
-        reg_rdata_next[0] = wkup_detector_en_4_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_14_qs;
       end
 
       addr_hit[396]: begin
-        reg_rdata_next[0] = wkup_detector_en_5_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_15_qs;
       end
 
       addr_hit[397]: begin
-        reg_rdata_next[0] = wkup_detector_en_6_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_16_qs;
       end
 
       addr_hit[398]: begin
-        reg_rdata_next[0] = wkup_detector_en_7_qs;
+        reg_rdata_next[0] = dio_pad_sleep_en_17_qs;
       end
 
       addr_hit[399]: begin
+        reg_rdata_next[0] = dio_pad_sleep_en_18_qs;
+      end
+
+      addr_hit[400]: begin
+        reg_rdata_next[0] = dio_pad_sleep_en_19_qs;
+      end
+
+      addr_hit[401]: begin
+        reg_rdata_next[0] = dio_pad_sleep_en_20_qs;
+      end
+
+      addr_hit[402]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs;
+      end
+
+      addr_hit[403]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs;
+      end
+
+      addr_hit[404]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs;
+      end
+
+      addr_hit[405]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs;
+      end
+
+      addr_hit[406]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs;
+      end
+
+      addr_hit[407]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs;
+      end
+
+      addr_hit[408]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs;
+      end
+
+      addr_hit[409]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs;
+      end
+
+      addr_hit[410]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs;
+      end
+
+      addr_hit[411]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs;
+      end
+
+      addr_hit[412]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs;
+      end
+
+      addr_hit[413]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs;
+      end
+
+      addr_hit[414]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs;
+      end
+
+      addr_hit[415]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs;
+      end
+
+      addr_hit[416]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_14_qs;
+      end
+
+      addr_hit[417]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_15_qs;
+      end
+
+      addr_hit[418]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_16_qs;
+      end
+
+      addr_hit[419]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_17_qs;
+      end
+
+      addr_hit[420]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_18_qs;
+      end
+
+      addr_hit[421]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_19_qs;
+      end
+
+      addr_hit[422]: begin
+        reg_rdata_next[1:0] = dio_pad_sleep_mode_20_qs;
+      end
+
+      addr_hit[423]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_0_qs;
+      end
+
+      addr_hit[424]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_1_qs;
+      end
+
+      addr_hit[425]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_2_qs;
+      end
+
+      addr_hit[426]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_3_qs;
+      end
+
+      addr_hit[427]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_4_qs;
+      end
+
+      addr_hit[428]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_5_qs;
+      end
+
+      addr_hit[429]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_6_qs;
+      end
+
+      addr_hit[430]: begin
+        reg_rdata_next[0] = wkup_detector_regwen_7_qs;
+      end
+
+      addr_hit[431]: begin
+        reg_rdata_next[0] = wkup_detector_en_0_qs;
+      end
+
+      addr_hit[432]: begin
+        reg_rdata_next[0] = wkup_detector_en_1_qs;
+      end
+
+      addr_hit[433]: begin
+        reg_rdata_next[0] = wkup_detector_en_2_qs;
+      end
+
+      addr_hit[434]: begin
+        reg_rdata_next[0] = wkup_detector_en_3_qs;
+      end
+
+      addr_hit[435]: begin
+        reg_rdata_next[0] = wkup_detector_en_4_qs;
+      end
+
+      addr_hit[436]: begin
+        reg_rdata_next[0] = wkup_detector_en_5_qs;
+      end
+
+      addr_hit[437]: begin
+        reg_rdata_next[0] = wkup_detector_en_6_qs;
+      end
+
+      addr_hit[438]: begin
+        reg_rdata_next[0] = wkup_detector_en_7_qs;
+      end
+
+      addr_hit[439]: begin
         reg_rdata_next[2:0] = wkup_detector_0_mode_0_qs;
         reg_rdata_next[3] = wkup_detector_0_filter_0_qs;
         reg_rdata_next[4] = wkup_detector_0_miodio_0_qs;
       end
 
-      addr_hit[400]: begin
+      addr_hit[440]: begin
         reg_rdata_next[2:0] = wkup_detector_1_mode_1_qs;
         reg_rdata_next[3] = wkup_detector_1_filter_1_qs;
         reg_rdata_next[4] = wkup_detector_1_miodio_1_qs;
       end
 
-      addr_hit[401]: begin
+      addr_hit[441]: begin
         reg_rdata_next[2:0] = wkup_detector_2_mode_2_qs;
         reg_rdata_next[3] = wkup_detector_2_filter_2_qs;
         reg_rdata_next[4] = wkup_detector_2_miodio_2_qs;
       end
 
-      addr_hit[402]: begin
+      addr_hit[442]: begin
         reg_rdata_next[2:0] = wkup_detector_3_mode_3_qs;
         reg_rdata_next[3] = wkup_detector_3_filter_3_qs;
         reg_rdata_next[4] = wkup_detector_3_miodio_3_qs;
       end
 
-      addr_hit[403]: begin
+      addr_hit[443]: begin
         reg_rdata_next[2:0] = wkup_detector_4_mode_4_qs;
         reg_rdata_next[3] = wkup_detector_4_filter_4_qs;
         reg_rdata_next[4] = wkup_detector_4_miodio_4_qs;
       end
 
-      addr_hit[404]: begin
+      addr_hit[444]: begin
         reg_rdata_next[2:0] = wkup_detector_5_mode_5_qs;
         reg_rdata_next[3] = wkup_detector_5_filter_5_qs;
         reg_rdata_next[4] = wkup_detector_5_miodio_5_qs;
       end
 
-      addr_hit[405]: begin
+      addr_hit[445]: begin
         reg_rdata_next[2:0] = wkup_detector_6_mode_6_qs;
         reg_rdata_next[3] = wkup_detector_6_filter_6_qs;
         reg_rdata_next[4] = wkup_detector_6_miodio_6_qs;
       end
 
-      addr_hit[406]: begin
+      addr_hit[446]: begin
         reg_rdata_next[2:0] = wkup_detector_7_mode_7_qs;
         reg_rdata_next[3] = wkup_detector_7_filter_7_qs;
         reg_rdata_next[4] = wkup_detector_7_miodio_7_qs;
       end
 
-      addr_hit[407]: begin
+      addr_hit[447]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_0_qs;
       end
 
-      addr_hit[408]: begin
+      addr_hit[448]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_1_qs;
       end
 
-      addr_hit[409]: begin
+      addr_hit[449]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_2_qs;
       end
 
-      addr_hit[410]: begin
+      addr_hit[450]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_3_qs;
       end
 
-      addr_hit[411]: begin
+      addr_hit[451]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_4_qs;
       end
 
-      addr_hit[412]: begin
+      addr_hit[452]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_5_qs;
       end
 
-      addr_hit[413]: begin
+      addr_hit[453]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_6_qs;
       end
 
-      addr_hit[414]: begin
+      addr_hit[454]: begin
         reg_rdata_next[7:0] = wkup_detector_cnt_th_7_qs;
       end
 
-      addr_hit[415]: begin
+      addr_hit[455]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_0_qs;
       end
 
-      addr_hit[416]: begin
+      addr_hit[456]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_1_qs;
       end
 
-      addr_hit[417]: begin
+      addr_hit[457]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_2_qs;
       end
 
-      addr_hit[418]: begin
+      addr_hit[458]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_3_qs;
       end
 
-      addr_hit[419]: begin
+      addr_hit[459]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_4_qs;
       end
 
-      addr_hit[420]: begin
+      addr_hit[460]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_5_qs;
       end
 
-      addr_hit[421]: begin
+      addr_hit[461]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_6_qs;
       end
 
-      addr_hit[422]: begin
+      addr_hit[462]: begin
         reg_rdata_next[5:0] = wkup_detector_padsel_7_qs;
       end
 
-      addr_hit[423]: begin
+      addr_hit[463]: begin
         reg_rdata_next[0] = wkup_cause_cause_0_qs;
         reg_rdata_next[1] = wkup_cause_cause_1_qs;
         reg_rdata_next[2] = wkup_cause_cause_2_qs;
diff --git a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
index 2e9c95d..7fdb848 100644
--- a/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
+++ b/hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
@@ -52,7 +52,7 @@
     { name: "NumSwResets",
       desc: "Number of software resets",
       type: "int",
-      default: "5",
+      default: "7",
       local: "true"
     },
 
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
index b539966..6709d99 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr.sv
@@ -208,9 +208,9 @@
   // To simplify generation, each reset generates all associated power domain outputs.
   // If a reset does not support a particular power domain, that reset is always hard-wired to 0.
 
-  lc_ctrl_pkg::lc_tx_t [14:0] leaf_rst_scanmode;
+  lc_ctrl_pkg::lc_tx_t [16:0] leaf_rst_scanmode;
   prim_lc_sync #(
-    .NumCopies(15),
+    .NumCopies(17),
     .AsyncOn(0)
     ) u_leaf_rst_scanmode_sync  (
     .clk_i,
@@ -528,6 +528,54 @@
     .clk_o(resets_o.rst_spi_device_n[Domain0Sel])
   );
 
+  logic [PowerDomains-1:0] rst_spi_host0_n;
+  assign rst_spi_host0_n[DomainAonSel] = 1'b0;
+  assign resets_o.rst_spi_host0_n[DomainAonSel] = rst_spi_host0_n[DomainAonSel];
+
+
+  prim_flop_2sync #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_0_spi_host0 (
+    .clk_i(clk_io_div2_i),
+    .rst_ni(rst_sys_src_n[Domain0Sel]),
+    .d_i(sw_rst_ctrl_n[SPI_HOST0]),
+    .q_o(rst_spi_host0_n[Domain0Sel])
+  );
+
+  prim_clock_mux2 #(
+    .NoFpgaBufG(1'b1)
+  ) u_0_spi_host0_mux (
+    .clk0_i(rst_spi_host0_n[Domain0Sel]),
+    .clk1_i(scan_rst_ni),
+    .sel_i(leaf_rst_scanmode[11] == lc_ctrl_pkg::On),
+    .clk_o(resets_o.rst_spi_host0_n[Domain0Sel])
+  );
+
+  logic [PowerDomains-1:0] rst_spi_host1_n;
+  assign rst_spi_host1_n[DomainAonSel] = 1'b0;
+  assign resets_o.rst_spi_host1_n[DomainAonSel] = rst_spi_host1_n[DomainAonSel];
+
+
+  prim_flop_2sync #(
+    .Width(1),
+    .ResetValue('0)
+  ) u_0_spi_host1 (
+    .clk_i(clk_io_div2_i),
+    .rst_ni(rst_sys_src_n[Domain0Sel]),
+    .d_i(sw_rst_ctrl_n[SPI_HOST1]),
+    .q_o(rst_spi_host1_n[Domain0Sel])
+  );
+
+  prim_clock_mux2 #(
+    .NoFpgaBufG(1'b1)
+  ) u_0_spi_host1_mux (
+    .clk0_i(rst_spi_host1_n[Domain0Sel]),
+    .clk1_i(scan_rst_ni),
+    .sel_i(leaf_rst_scanmode[12] == lc_ctrl_pkg::On),
+    .clk_o(resets_o.rst_spi_host1_n[Domain0Sel])
+  );
+
   logic [PowerDomains-1:0] rst_usb_n;
   assign rst_usb_n[DomainAonSel] = 1'b0;
   assign resets_o.rst_usb_n[DomainAonSel] = rst_usb_n[DomainAonSel];
@@ -548,7 +596,7 @@
   ) u_0_usb_mux (
     .clk0_i(rst_usb_n[Domain0Sel]),
     .clk1_i(scan_rst_ni),
-    .sel_i(leaf_rst_scanmode[11] == lc_ctrl_pkg::On),
+    .sel_i(leaf_rst_scanmode[13] == lc_ctrl_pkg::On),
     .clk_o(resets_o.rst_usb_n[Domain0Sel])
   );
 
@@ -572,7 +620,7 @@
   ) u_0_i2c0_mux (
     .clk0_i(rst_i2c0_n[Domain0Sel]),
     .clk1_i(scan_rst_ni),
-    .sel_i(leaf_rst_scanmode[12] == lc_ctrl_pkg::On),
+    .sel_i(leaf_rst_scanmode[14] == lc_ctrl_pkg::On),
     .clk_o(resets_o.rst_i2c0_n[Domain0Sel])
   );
 
@@ -596,7 +644,7 @@
   ) u_0_i2c1_mux (
     .clk0_i(rst_i2c1_n[Domain0Sel]),
     .clk1_i(scan_rst_ni),
-    .sel_i(leaf_rst_scanmode[13] == lc_ctrl_pkg::On),
+    .sel_i(leaf_rst_scanmode[15] == lc_ctrl_pkg::On),
     .clk_o(resets_o.rst_i2c1_n[Domain0Sel])
   );
 
@@ -620,7 +668,7 @@
   ) u_0_i2c2_mux (
     .clk0_i(rst_i2c2_n[Domain0Sel]),
     .clk1_i(scan_rst_ni),
-    .sel_i(leaf_rst_scanmode[14] == lc_ctrl_pkg::On),
+    .sel_i(leaf_rst_scanmode[16] == lc_ctrl_pkg::On),
     .clk_o(resets_o.rst_i2c2_n[Domain0Sel])
   );
 
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
index 85dc87b..14142e8 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_pkg.sv
@@ -24,10 +24,12 @@
 
   // positions of software controllable reset bits
   parameter int SPI_DEVICE = 0;
-  parameter int USB = 1;
-  parameter int I2C0 = 2;
-  parameter int I2C1 = 3;
-  parameter int I2C2 = 4;
+  parameter int SPI_HOST0 = 1;
+  parameter int SPI_HOST1 = 2;
+  parameter int USB = 3;
+  parameter int I2C0 = 4;
+  parameter int I2C1 = 5;
+  parameter int I2C2 = 6;
 
   // ast interface
   typedef struct packed {
@@ -54,6 +56,8 @@
     logic [PowerDomains-1:0] rst_sys_io_div4_n;
     logic [PowerDomains-1:0] rst_sys_aon_n;
     logic [PowerDomains-1:0] rst_spi_device_n;
+    logic [PowerDomains-1:0] rst_spi_host0_n;
+    logic [PowerDomains-1:0] rst_spi_host1_n;
     logic [PowerDomains-1:0] rst_usb_n;
     logic [PowerDomains-1:0] rst_i2c0_n;
     logic [PowerDomains-1:0] rst_i2c1_n;
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
index feaa3cc..505ce4d 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_pkg.sv
@@ -10,7 +10,7 @@
   parameter int RdWidth = 32;
   parameter int IdxWidth = 4;
   parameter int NumHwResets = 2;
-  parameter int NumSwResets = 5;
+  parameter int NumSwResets = 7;
 
   // Address width within the block
   parameter int BlockAw = 6;
@@ -106,25 +106,25 @@
   // Register to internal design logic //
   ///////////////////////////////////////
   typedef struct packed {
-    rstmgr_reg2hw_reset_info_reg_t reset_info; // [26:25]
-    rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [24:20]
-    rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [19:15]
-    rstmgr_reg2hw_sw_rst_regen_mreg_t [4:0] sw_rst_regen; // [14:10]
-    rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [4:0] sw_rst_ctrl_n; // [9:0]
+    rstmgr_reg2hw_reset_info_reg_t reset_info; // [32:31]
+    rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [30:26]
+    rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [25:21]
+    rstmgr_reg2hw_sw_rst_regen_mreg_t [6:0] sw_rst_regen; // [20:14]
+    rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [6:0] sw_rst_ctrl_n; // [13:0]
   } rstmgr_reg2hw_t;
 
   ///////////////////////////////////////
   // Internal design logic to register //
   ///////////////////////////////////////
   typedef struct packed {
-    rstmgr_hw2reg_reset_info_reg_t reset_info; // [87:81]
-    rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [80:79]
-    rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [78:75]
-    rstmgr_hw2reg_alert_info_reg_t alert_info; // [74:43]
-    rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [42:41]
-    rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [40:37]
-    rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [36:5]
-    rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [4:0] sw_rst_ctrl_n; // [4:0]
+    rstmgr_hw2reg_reset_info_reg_t reset_info; // [89:83]
+    rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [82:81]
+    rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [80:77]
+    rstmgr_hw2reg_alert_info_reg_t alert_info; // [76:45]
+    rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [44:43]
+    rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [42:39]
+    rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [38:7]
+    rstmgr_hw2reg_sw_rst_ctrl_n_mreg_t [6:0] sw_rst_ctrl_n; // [6:0]
   } rstmgr_hw2reg_t;
 
   // Register Address
@@ -147,12 +147,14 @@
   parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0;
   parameter logic [31:0] RSTMGR_CPU_INFO_RESVAL = 32'h 0;
   parameter logic [31:0] RSTMGR_CPU_INFO_VALUE_RESVAL = 32'h 0;
-  parameter logic [4:0] RSTMGR_SW_RST_CTRL_N_RESVAL = 5'h 1f;
+  parameter logic [6:0] RSTMGR_SW_RST_CTRL_N_RESVAL = 7'h 7f;
   parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_0_RESVAL = 1'h 1;
   parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_1_RESVAL = 1'h 1;
   parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_2_RESVAL = 1'h 1;
   parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_3_RESVAL = 1'h 1;
   parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_4_RESVAL = 1'h 1;
+  parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_5_RESVAL = 1'h 1;
+  parameter logic [0:0] RSTMGR_SW_RST_CTRL_N_VAL_6_RESVAL = 1'h 1;
 
   // Register Index
   typedef enum int {
diff --git a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
index 4727b20..5b44aa9 100644
--- a/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
+++ b/hw/top_earlgrey/ip/rstmgr/rtl/autogen/rstmgr_reg_top.sv
@@ -118,6 +118,12 @@
   logic sw_rst_regen_en_4_qs;
   logic sw_rst_regen_en_4_wd;
   logic sw_rst_regen_en_4_we;
+  logic sw_rst_regen_en_5_qs;
+  logic sw_rst_regen_en_5_wd;
+  logic sw_rst_regen_en_5_we;
+  logic sw_rst_regen_en_6_qs;
+  logic sw_rst_regen_en_6_wd;
+  logic sw_rst_regen_en_6_we;
   logic sw_rst_ctrl_n_val_0_qs;
   logic sw_rst_ctrl_n_val_0_wd;
   logic sw_rst_ctrl_n_val_0_we;
@@ -138,6 +144,14 @@
   logic sw_rst_ctrl_n_val_4_wd;
   logic sw_rst_ctrl_n_val_4_we;
   logic sw_rst_ctrl_n_val_4_re;
+  logic sw_rst_ctrl_n_val_5_qs;
+  logic sw_rst_ctrl_n_val_5_wd;
+  logic sw_rst_ctrl_n_val_5_we;
+  logic sw_rst_ctrl_n_val_5_re;
+  logic sw_rst_ctrl_n_val_6_qs;
+  logic sw_rst_ctrl_n_val_6_wd;
+  logic sw_rst_ctrl_n_val_6_we;
+  logic sw_rst_ctrl_n_val_6_re;
 
   // Register instances
   // R[reset_info]: V(False)
@@ -552,6 +566,58 @@
   );
 
 
+  // F[en_5]: 5:5
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_sw_rst_regen_en_5 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (sw_rst_regen_en_5_we),
+    .wd     (sw_rst_regen_en_5_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.sw_rst_regen[5].q ),
+
+    // to register interface (read)
+    .qs     (sw_rst_regen_en_5_qs)
+  );
+
+
+  // F[en_6]: 6:6
+  prim_subreg #(
+    .DW      (1),
+    .SWACCESS("W0C"),
+    .RESVAL  (1'h1)
+  ) u_sw_rst_regen_en_6 (
+    .clk_i   (clk_i    ),
+    .rst_ni  (rst_ni  ),
+
+    // from register interface
+    .we     (sw_rst_regen_en_6_we),
+    .wd     (sw_rst_regen_en_6_wd),
+
+    // from internal hardware
+    .de     (1'b0),
+    .d      ('0  ),
+
+    // to internal hardware
+    .qe     (),
+    .q      (reg2hw.sw_rst_regen[6].q ),
+
+    // to register interface (read)
+    .qs     (sw_rst_regen_en_6_qs)
+  );
+
+
 
 
   // Subregister 0 of Multireg sw_rst_ctrl_n
@@ -632,6 +698,36 @@
   );
 
 
+  // F[val_5]: 5:5
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_sw_rst_ctrl_n_val_5 (
+    .re     (sw_rst_ctrl_n_val_5_re),
+    .we     (sw_rst_ctrl_n_val_5_we),
+    .wd     (sw_rst_ctrl_n_val_5_wd),
+    .d      (hw2reg.sw_rst_ctrl_n[5].d),
+    .qre    (),
+    .qe     (reg2hw.sw_rst_ctrl_n[5].qe),
+    .q      (reg2hw.sw_rst_ctrl_n[5].q ),
+    .qs     (sw_rst_ctrl_n_val_5_qs)
+  );
+
+
+  // F[val_6]: 6:6
+  prim_subreg_ext #(
+    .DW    (1)
+  ) u_sw_rst_ctrl_n_val_6 (
+    .re     (sw_rst_ctrl_n_val_6_re),
+    .we     (sw_rst_ctrl_n_val_6_we),
+    .wd     (sw_rst_ctrl_n_val_6_wd),
+    .d      (hw2reg.sw_rst_ctrl_n[6].d),
+    .qre    (),
+    .qe     (reg2hw.sw_rst_ctrl_n[6].qe),
+    .q      (reg2hw.sw_rst_ctrl_n[6].q ),
+    .qs     (sw_rst_ctrl_n_val_6_qs)
+  );
+
+
 
 
 
@@ -712,6 +808,12 @@
   assign sw_rst_regen_en_4_we = addr_hit[7] & reg_we & ~wr_err;
   assign sw_rst_regen_en_4_wd = reg_wdata[4];
 
+  assign sw_rst_regen_en_5_we = addr_hit[7] & reg_we & ~wr_err;
+  assign sw_rst_regen_en_5_wd = reg_wdata[5];
+
+  assign sw_rst_regen_en_6_we = addr_hit[7] & reg_we & ~wr_err;
+  assign sw_rst_regen_en_6_wd = reg_wdata[6];
+
   assign sw_rst_ctrl_n_val_0_we = addr_hit[8] & reg_we & ~wr_err;
   assign sw_rst_ctrl_n_val_0_wd = reg_wdata[0];
   assign sw_rst_ctrl_n_val_0_re = addr_hit[8] && reg_re;
@@ -732,6 +834,14 @@
   assign sw_rst_ctrl_n_val_4_wd = reg_wdata[4];
   assign sw_rst_ctrl_n_val_4_re = addr_hit[8] && reg_re;
 
+  assign sw_rst_ctrl_n_val_5_we = addr_hit[8] & reg_we & ~wr_err;
+  assign sw_rst_ctrl_n_val_5_wd = reg_wdata[5];
+  assign sw_rst_ctrl_n_val_5_re = addr_hit[8] && reg_re;
+
+  assign sw_rst_ctrl_n_val_6_we = addr_hit[8] & reg_we & ~wr_err;
+  assign sw_rst_ctrl_n_val_6_wd = reg_wdata[6];
+  assign sw_rst_ctrl_n_val_6_re = addr_hit[8] && reg_re;
+
   // Read data return
   always_comb begin
     reg_rdata_next = '0;
@@ -775,6 +885,8 @@
         reg_rdata_next[2] = sw_rst_regen_en_2_qs;
         reg_rdata_next[3] = sw_rst_regen_en_3_qs;
         reg_rdata_next[4] = sw_rst_regen_en_4_qs;
+        reg_rdata_next[5] = sw_rst_regen_en_5_qs;
+        reg_rdata_next[6] = sw_rst_regen_en_6_qs;
       end
 
       addr_hit[8]: begin
@@ -783,6 +895,8 @@
         reg_rdata_next[2] = sw_rst_ctrl_n_val_2_qs;
         reg_rdata_next[3] = sw_rst_ctrl_n_val_3_qs;
         reg_rdata_next[4] = sw_rst_ctrl_n_val_4_qs;
+        reg_rdata_next[5] = sw_rst_ctrl_n_val_5_qs;
+        reg_rdata_next[6] = sw_rst_ctrl_n_val_6_qs;
       end
 
       default: begin
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
index 2345834..73dcaf8 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson
@@ -37,6 +37,8 @@
       pattgen
       gpio
       spi_device
+      spi_host0
+      spi_host1
       rv_timer
       usbdev
       pwrmgr_aon
@@ -48,9 +50,9 @@
       lc_ctrl
       sensor_ctrl_aon
       alert_handler
-      nmi_gen
       ast_wrapper
       sram_ctrl_ret_aon
+      nmi_gen
     ]
   }
   nodes:
@@ -247,6 +249,42 @@
       pipeline_byp: "true"
     }
     {
+      name: spi_host0
+      type: device
+      clock: clk_peri_i
+      reset: rst_peri_ni
+      pipeline: "false"
+      inst_type: spi_host
+      addr_range:
+      [
+        {
+          base_addr: 0x40060000
+          size_byte: 0x1000
+        }
+      ]
+      xbar: false
+      stub: false
+      pipeline_byp: "true"
+    }
+    {
+      name: spi_host1
+      type: device
+      clock: clk_peri_i
+      reset: rst_peri_ni
+      pipeline: "false"
+      inst_type: spi_host
+      addr_range:
+      [
+        {
+          base_addr: 0x40070000
+          size_byte: 0x1000
+        }
+      ]
+      xbar: false
+      stub: false
+      pipeline_byp: "true"
+    }
+    {
       name: rv_timer
       type: device
       clock: clk_peri_i
diff --git a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
index 8cd2158..177d4f6 100644
--- a/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
+++ b/hw/top_earlgrey/ip/xbar_peri/data/autogen/xbar_peri.hjson
@@ -81,6 +81,18 @@
     }
     { struct: "tl"
       type:   "req_rsp"
+      name:   "tl_spi_host0"
+      act:    "req"
+      package: "tlul_pkg"
+    }
+    { struct: "tl"
+      type:   "req_rsp"
+      name:   "tl_spi_host1"
+      act:    "req"
+      package: "tlul_pkg"
+    }
+    { struct: "tl"
+      type:   "req_rsp"
       name:   "tl_rv_timer"
       act:    "req"
       package: "tlul_pkg"
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
index 8006d4d..448a560 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/tb__xbar_connect.sv
@@ -27,6 +27,8 @@
 `CONNECT_TL_DEVICE_IF(pattgen, dut, clk_peri_i, rst_n)
 `CONNECT_TL_DEVICE_IF(gpio, dut, clk_peri_i, rst_n)
 `CONNECT_TL_DEVICE_IF(spi_device, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host0, dut, clk_peri_i, rst_n)
+`CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_peri_i, rst_n)
 `CONNECT_TL_DEVICE_IF(rv_timer, dut, clk_peri_i, rst_n)
 `CONNECT_TL_DEVICE_IF(usbdev, dut, clk_peri_i, rst_n)
 `CONNECT_TL_DEVICE_IF(pwrmgr_aon, dut, clk_peri_i, rst_n)
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
index 6265a2c..0981d56 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_cover.cfg
@@ -48,6 +48,12 @@
 -node tb.dut tl_spi_device_o.a_address[17:17]
 -node tb.dut tl_spi_device_o.a_address[29:19]
 -node tb.dut tl_spi_device_o.a_address[31:31]
+-node tb.dut tl_spi_host0_o.a_address[16:12]
+-node tb.dut tl_spi_host0_o.a_address[29:19]
+-node tb.dut tl_spi_host0_o.a_address[31:31]
+-node tb.dut tl_spi_host1_o.a_address[15:12]
+-node tb.dut tl_spi_host1_o.a_address[29:19]
+-node tb.dut tl_spi_host1_o.a_address[31:31]
 -node tb.dut tl_rv_timer_o.a_address[19:12]
 -node tb.dut tl_rv_timer_o.a_address[29:21]
 -node tb.dut tl_rv_timer_o.a_address[31:31]
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
index 757aeae..fcb7906 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv
@@ -37,6 +37,12 @@
     '{"spi_device", '{
         '{32'h40050000, 32'h40051fff}
     }},
+    '{"spi_host0", '{
+        '{32'h40060000, 32'h40060fff}
+    }},
+    '{"spi_host1", '{
+        '{32'h40070000, 32'h40070fff}
+    }},
     '{"rv_timer", '{
         '{32'h40100000, 32'h40100fff}
     }},
@@ -93,6 +99,8 @@
         "pattgen",
         "gpio",
         "spi_device",
+        "spi_host0",
+        "spi_host1",
         "rv_timer",
         "usbdev",
         "pwrmgr_aon",
@@ -104,7 +112,7 @@
         "lc_ctrl",
         "sensor_ctrl_aon",
         "alert_handler",
-        "nmi_gen",
         "ast_wrapper",
-        "sram_ctrl_ret_aon"}}
+        "sram_ctrl_ret_aon",
+        "nmi_gen"}}
 };
diff --git a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
index 917c029..3085472 100644
--- a/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/dv/autogen/xbar_peri_bind.sv
@@ -74,6 +74,18 @@
     .h2d    (tl_spi_device_o),
     .d2h    (tl_spi_device_i)
   );
+  bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host0 (
+    .clk_i  (clk_peri_i),
+    .rst_ni (rst_peri_ni),
+    .h2d    (tl_spi_host0_o),
+    .d2h    (tl_spi_host0_i)
+  );
+  bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_spi_host1 (
+    .clk_i  (clk_peri_i),
+    .rst_ni (rst_peri_ni),
+    .h2d    (tl_spi_host1_o),
+    .d2h    (tl_spi_host1_i)
+  );
   bind xbar_peri tlul_assert #(.EndpointType("Host")) tlul_assert_device_rv_timer (
     .clk_i  (clk_peri_i),
     .rst_ni (rst_peri_ni),
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
index c3dfaae..604910d 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv
@@ -16,6 +16,8 @@
   localparam logic [31:0] ADDR_SPACE_PATTGEN           = 32'h 400e0000;
   localparam logic [31:0] ADDR_SPACE_GPIO              = 32'h 40040000;
   localparam logic [31:0] ADDR_SPACE_SPI_DEVICE        = 32'h 40050000;
+  localparam logic [31:0] ADDR_SPACE_SPI_HOST0         = 32'h 40060000;
+  localparam logic [31:0] ADDR_SPACE_SPI_HOST1         = 32'h 40070000;
   localparam logic [31:0] ADDR_SPACE_RV_TIMER          = 32'h 40100000;
   localparam logic [31:0] ADDR_SPACE_USBDEV            = 32'h 40110000;
   localparam logic [31:0] ADDR_SPACE_PWRMGR_AON        = 32'h 40400000;
@@ -41,6 +43,8 @@
   localparam logic [31:0] ADDR_MASK_PATTGEN           = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_GPIO              = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_SPI_DEVICE        = 32'h 00001fff;
+  localparam logic [31:0] ADDR_MASK_SPI_HOST0         = 32'h 00000fff;
+  localparam logic [31:0] ADDR_MASK_SPI_HOST1         = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_RV_TIMER          = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_USBDEV            = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_PWRMGR_AON        = 32'h 00000fff;
@@ -57,7 +61,7 @@
   localparam logic [31:0] ADDR_MASK_AST_WRAPPER       = 32'h 00000fff;
 
   localparam int N_HOST   = 1;
-  localparam int N_DEVICE = 24;
+  localparam int N_DEVICE = 26;
 
   typedef enum int {
     TlUart0 = 0,
@@ -70,20 +74,22 @@
     TlPattgen = 7,
     TlGpio = 8,
     TlSpiDevice = 9,
-    TlRvTimer = 10,
-    TlUsbdev = 11,
-    TlPwrmgrAon = 12,
-    TlRstmgrAon = 13,
-    TlClkmgrAon = 14,
-    TlPinmuxAon = 15,
-    TlRamRetAon = 16,
-    TlOtpCtrl = 17,
-    TlLcCtrl = 18,
-    TlSensorCtrlAon = 19,
-    TlAlertHandler = 20,
-    TlSramCtrlRetAon = 21,
-    TlNmiGen = 22,
-    TlAstWrapper = 23
+    TlSpiHost0 = 10,
+    TlSpiHost1 = 11,
+    TlRvTimer = 12,
+    TlUsbdev = 13,
+    TlPwrmgrAon = 14,
+    TlRstmgrAon = 15,
+    TlClkmgrAon = 16,
+    TlPinmuxAon = 17,
+    TlRamRetAon = 18,
+    TlOtpCtrl = 19,
+    TlLcCtrl = 20,
+    TlSensorCtrlAon = 21,
+    TlAlertHandler = 22,
+    TlSramCtrlRetAon = 23,
+    TlNmiGen = 24,
+    TlAstWrapper = 25
   } tl_device_e;
 
   typedef enum int {
diff --git a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
index ce776a4..867f06e 100644
--- a/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
+++ b/hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv
@@ -7,7 +7,7 @@
 //
 // Interconnect
 // main
-//   -> s1n_25
+//   -> s1n_27
 //     -> uart0
 //     -> uart1
 //     -> uart2
@@ -18,6 +18,8 @@
 //     -> pattgen
 //     -> gpio
 //     -> spi_device
+//     -> spi_host0
+//     -> spi_host1
 //     -> rv_timer
 //     -> usbdev
 //     -> pwrmgr_aon
@@ -29,9 +31,9 @@
 //     -> lc_ctrl
 //     -> sensor_ctrl_aon
 //     -> alert_handler
-//     -> nmi_gen
 //     -> ast_wrapper
 //     -> sram_ctrl_ret_aon
+//     -> nmi_gen
 
 module xbar_peri (
   input clk_peri_i,
@@ -62,6 +64,10 @@
   input  tlul_pkg::tl_d2h_t tl_gpio_i,
   output tlul_pkg::tl_h2d_t tl_spi_device_o,
   input  tlul_pkg::tl_d2h_t tl_spi_device_i,
+  output tlul_pkg::tl_h2d_t tl_spi_host0_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_host0_i,
+  output tlul_pkg::tl_h2d_t tl_spi_host1_o,
+  input  tlul_pkg::tl_d2h_t tl_spi_host1_i,
   output tlul_pkg::tl_h2d_t tl_rv_timer_o,
   input  tlul_pkg::tl_d2h_t tl_rv_timer_i,
   output tlul_pkg::tl_h2d_t tl_usbdev_o,
@@ -102,167 +108,179 @@
   lc_ctrl_pkg::lc_tx_t unused_scanmode;
   assign unused_scanmode = scanmode_i;
 
-  tl_h2d_t tl_s1n_25_us_h2d ;
-  tl_d2h_t tl_s1n_25_us_d2h ;
+  tl_h2d_t tl_s1n_27_us_h2d ;
+  tl_d2h_t tl_s1n_27_us_d2h ;
 
 
-  tl_h2d_t tl_s1n_25_ds_h2d [24];
-  tl_d2h_t tl_s1n_25_ds_d2h [24];
+  tl_h2d_t tl_s1n_27_ds_h2d [26];
+  tl_d2h_t tl_s1n_27_ds_d2h [26];
 
   // Create steering signal
-  logic [4:0] dev_sel_s1n_25;
+  logic [4:0] dev_sel_s1n_27;
 
 
 
-  assign tl_uart0_o = tl_s1n_25_ds_h2d[0];
-  assign tl_s1n_25_ds_d2h[0] = tl_uart0_i;
+  assign tl_uart0_o = tl_s1n_27_ds_h2d[0];
+  assign tl_s1n_27_ds_d2h[0] = tl_uart0_i;
 
-  assign tl_uart1_o = tl_s1n_25_ds_h2d[1];
-  assign tl_s1n_25_ds_d2h[1] = tl_uart1_i;
+  assign tl_uart1_o = tl_s1n_27_ds_h2d[1];
+  assign tl_s1n_27_ds_d2h[1] = tl_uart1_i;
 
-  assign tl_uart2_o = tl_s1n_25_ds_h2d[2];
-  assign tl_s1n_25_ds_d2h[2] = tl_uart2_i;
+  assign tl_uart2_o = tl_s1n_27_ds_h2d[2];
+  assign tl_s1n_27_ds_d2h[2] = tl_uart2_i;
 
-  assign tl_uart3_o = tl_s1n_25_ds_h2d[3];
-  assign tl_s1n_25_ds_d2h[3] = tl_uart3_i;
+  assign tl_uart3_o = tl_s1n_27_ds_h2d[3];
+  assign tl_s1n_27_ds_d2h[3] = tl_uart3_i;
 
-  assign tl_i2c0_o = tl_s1n_25_ds_h2d[4];
-  assign tl_s1n_25_ds_d2h[4] = tl_i2c0_i;
+  assign tl_i2c0_o = tl_s1n_27_ds_h2d[4];
+  assign tl_s1n_27_ds_d2h[4] = tl_i2c0_i;
 
-  assign tl_i2c1_o = tl_s1n_25_ds_h2d[5];
-  assign tl_s1n_25_ds_d2h[5] = tl_i2c1_i;
+  assign tl_i2c1_o = tl_s1n_27_ds_h2d[5];
+  assign tl_s1n_27_ds_d2h[5] = tl_i2c1_i;
 
-  assign tl_i2c2_o = tl_s1n_25_ds_h2d[6];
-  assign tl_s1n_25_ds_d2h[6] = tl_i2c2_i;
+  assign tl_i2c2_o = tl_s1n_27_ds_h2d[6];
+  assign tl_s1n_27_ds_d2h[6] = tl_i2c2_i;
 
-  assign tl_pattgen_o = tl_s1n_25_ds_h2d[7];
-  assign tl_s1n_25_ds_d2h[7] = tl_pattgen_i;
+  assign tl_pattgen_o = tl_s1n_27_ds_h2d[7];
+  assign tl_s1n_27_ds_d2h[7] = tl_pattgen_i;
 
-  assign tl_gpio_o = tl_s1n_25_ds_h2d[8];
-  assign tl_s1n_25_ds_d2h[8] = tl_gpio_i;
+  assign tl_gpio_o = tl_s1n_27_ds_h2d[8];
+  assign tl_s1n_27_ds_d2h[8] = tl_gpio_i;
 
-  assign tl_spi_device_o = tl_s1n_25_ds_h2d[9];
-  assign tl_s1n_25_ds_d2h[9] = tl_spi_device_i;
+  assign tl_spi_device_o = tl_s1n_27_ds_h2d[9];
+  assign tl_s1n_27_ds_d2h[9] = tl_spi_device_i;
 
-  assign tl_rv_timer_o = tl_s1n_25_ds_h2d[10];
-  assign tl_s1n_25_ds_d2h[10] = tl_rv_timer_i;
+  assign tl_spi_host0_o = tl_s1n_27_ds_h2d[10];
+  assign tl_s1n_27_ds_d2h[10] = tl_spi_host0_i;
 
-  assign tl_usbdev_o = tl_s1n_25_ds_h2d[11];
-  assign tl_s1n_25_ds_d2h[11] = tl_usbdev_i;
+  assign tl_spi_host1_o = tl_s1n_27_ds_h2d[11];
+  assign tl_s1n_27_ds_d2h[11] = tl_spi_host1_i;
 
-  assign tl_pwrmgr_aon_o = tl_s1n_25_ds_h2d[12];
-  assign tl_s1n_25_ds_d2h[12] = tl_pwrmgr_aon_i;
+  assign tl_rv_timer_o = tl_s1n_27_ds_h2d[12];
+  assign tl_s1n_27_ds_d2h[12] = tl_rv_timer_i;
 
-  assign tl_rstmgr_aon_o = tl_s1n_25_ds_h2d[13];
-  assign tl_s1n_25_ds_d2h[13] = tl_rstmgr_aon_i;
+  assign tl_usbdev_o = tl_s1n_27_ds_h2d[13];
+  assign tl_s1n_27_ds_d2h[13] = tl_usbdev_i;
 
-  assign tl_clkmgr_aon_o = tl_s1n_25_ds_h2d[14];
-  assign tl_s1n_25_ds_d2h[14] = tl_clkmgr_aon_i;
+  assign tl_pwrmgr_aon_o = tl_s1n_27_ds_h2d[14];
+  assign tl_s1n_27_ds_d2h[14] = tl_pwrmgr_aon_i;
 
-  assign tl_pinmux_aon_o = tl_s1n_25_ds_h2d[15];
-  assign tl_s1n_25_ds_d2h[15] = tl_pinmux_aon_i;
+  assign tl_rstmgr_aon_o = tl_s1n_27_ds_h2d[15];
+  assign tl_s1n_27_ds_d2h[15] = tl_rstmgr_aon_i;
 
-  assign tl_ram_ret_aon_o = tl_s1n_25_ds_h2d[16];
-  assign tl_s1n_25_ds_d2h[16] = tl_ram_ret_aon_i;
+  assign tl_clkmgr_aon_o = tl_s1n_27_ds_h2d[16];
+  assign tl_s1n_27_ds_d2h[16] = tl_clkmgr_aon_i;
 
-  assign tl_otp_ctrl_o = tl_s1n_25_ds_h2d[17];
-  assign tl_s1n_25_ds_d2h[17] = tl_otp_ctrl_i;
+  assign tl_pinmux_aon_o = tl_s1n_27_ds_h2d[17];
+  assign tl_s1n_27_ds_d2h[17] = tl_pinmux_aon_i;
 
-  assign tl_lc_ctrl_o = tl_s1n_25_ds_h2d[18];
-  assign tl_s1n_25_ds_d2h[18] = tl_lc_ctrl_i;
+  assign tl_ram_ret_aon_o = tl_s1n_27_ds_h2d[18];
+  assign tl_s1n_27_ds_d2h[18] = tl_ram_ret_aon_i;
 
-  assign tl_sensor_ctrl_aon_o = tl_s1n_25_ds_h2d[19];
-  assign tl_s1n_25_ds_d2h[19] = tl_sensor_ctrl_aon_i;
+  assign tl_otp_ctrl_o = tl_s1n_27_ds_h2d[19];
+  assign tl_s1n_27_ds_d2h[19] = tl_otp_ctrl_i;
 
-  assign tl_alert_handler_o = tl_s1n_25_ds_h2d[20];
-  assign tl_s1n_25_ds_d2h[20] = tl_alert_handler_i;
+  assign tl_lc_ctrl_o = tl_s1n_27_ds_h2d[20];
+  assign tl_s1n_27_ds_d2h[20] = tl_lc_ctrl_i;
 
-  assign tl_nmi_gen_o = tl_s1n_25_ds_h2d[21];
-  assign tl_s1n_25_ds_d2h[21] = tl_nmi_gen_i;
+  assign tl_sensor_ctrl_aon_o = tl_s1n_27_ds_h2d[21];
+  assign tl_s1n_27_ds_d2h[21] = tl_sensor_ctrl_aon_i;
 
-  assign tl_ast_wrapper_o = tl_s1n_25_ds_h2d[22];
-  assign tl_s1n_25_ds_d2h[22] = tl_ast_wrapper_i;
+  assign tl_alert_handler_o = tl_s1n_27_ds_h2d[22];
+  assign tl_s1n_27_ds_d2h[22] = tl_alert_handler_i;
 
-  assign tl_sram_ctrl_ret_aon_o = tl_s1n_25_ds_h2d[23];
-  assign tl_s1n_25_ds_d2h[23] = tl_sram_ctrl_ret_aon_i;
+  assign tl_ast_wrapper_o = tl_s1n_27_ds_h2d[23];
+  assign tl_s1n_27_ds_d2h[23] = tl_ast_wrapper_i;
 
-  assign tl_s1n_25_us_h2d = tl_main_i;
-  assign tl_main_o = tl_s1n_25_us_d2h;
+  assign tl_sram_ctrl_ret_aon_o = tl_s1n_27_ds_h2d[24];
+  assign tl_s1n_27_ds_d2h[24] = tl_sram_ctrl_ret_aon_i;
+
+  assign tl_nmi_gen_o = tl_s1n_27_ds_h2d[25];
+  assign tl_s1n_27_ds_d2h[25] = tl_nmi_gen_i;
+
+  assign tl_s1n_27_us_h2d = tl_main_i;
+  assign tl_main_o = tl_s1n_27_us_d2h;
 
   always_comb begin
     // default steering to generate error response if address is not within the range
-    dev_sel_s1n_25 = 5'd24;
-    if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
-      dev_sel_s1n_25 = 5'd0;
+    dev_sel_s1n_27 = 5'd26;
+    if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_UART0)) == ADDR_SPACE_UART0) begin
+      dev_sel_s1n_27 = 5'd0;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
-      dev_sel_s1n_25 = 5'd1;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_UART1)) == ADDR_SPACE_UART1) begin
+      dev_sel_s1n_27 = 5'd1;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
-      dev_sel_s1n_25 = 5'd2;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_UART2)) == ADDR_SPACE_UART2) begin
+      dev_sel_s1n_27 = 5'd2;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
-      dev_sel_s1n_25 = 5'd3;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_UART3)) == ADDR_SPACE_UART3) begin
+      dev_sel_s1n_27 = 5'd3;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
-      dev_sel_s1n_25 = 5'd4;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_I2C0)) == ADDR_SPACE_I2C0) begin
+      dev_sel_s1n_27 = 5'd4;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
-      dev_sel_s1n_25 = 5'd5;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_I2C1)) == ADDR_SPACE_I2C1) begin
+      dev_sel_s1n_27 = 5'd5;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
-      dev_sel_s1n_25 = 5'd6;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_I2C2)) == ADDR_SPACE_I2C2) begin
+      dev_sel_s1n_27 = 5'd6;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
-      dev_sel_s1n_25 = 5'd7;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PATTGEN)) == ADDR_SPACE_PATTGEN) begin
+      dev_sel_s1n_27 = 5'd7;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
-      dev_sel_s1n_25 = 5'd8;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
+      dev_sel_s1n_27 = 5'd8;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
-      dev_sel_s1n_25 = 5'd9;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
+      dev_sel_s1n_27 = 5'd9;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
-      dev_sel_s1n_25 = 5'd10;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST0)) == ADDR_SPACE_SPI_HOST0) begin
+      dev_sel_s1n_27 = 5'd10;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
-      dev_sel_s1n_25 = 5'd11;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SPI_HOST1)) == ADDR_SPACE_SPI_HOST1) begin
+      dev_sel_s1n_27 = 5'd11;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin
-      dev_sel_s1n_25 = 5'd12;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
+      dev_sel_s1n_27 = 5'd12;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin
-      dev_sel_s1n_25 = 5'd13;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
+      dev_sel_s1n_27 = 5'd13;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin
-      dev_sel_s1n_25 = 5'd14;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PWRMGR_AON)) == ADDR_SPACE_PWRMGR_AON) begin
+      dev_sel_s1n_27 = 5'd14;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin
-      dev_sel_s1n_25 = 5'd15;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RSTMGR_AON)) == ADDR_SPACE_RSTMGR_AON) begin
+      dev_sel_s1n_27 = 5'd15;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_RAM_RET_AON)) == ADDR_SPACE_RAM_RET_AON) begin
-      dev_sel_s1n_25 = 5'd16;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_CLKMGR_AON)) == ADDR_SPACE_CLKMGR_AON) begin
+      dev_sel_s1n_27 = 5'd16;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
-      dev_sel_s1n_25 = 5'd17;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_PINMUX_AON)) == ADDR_SPACE_PINMUX_AON) begin
+      dev_sel_s1n_27 = 5'd17;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
-      dev_sel_s1n_25 = 5'd18;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_RAM_RET_AON)) == ADDR_SPACE_RAM_RET_AON) begin
+      dev_sel_s1n_27 = 5'd18;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin
-      dev_sel_s1n_25 = 5'd19;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_OTP_CTRL)) == ADDR_SPACE_OTP_CTRL) begin
+      dev_sel_s1n_27 = 5'd19;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
-      dev_sel_s1n_25 = 5'd20;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_LC_CTRL)) == ADDR_SPACE_LC_CTRL) begin
+      dev_sel_s1n_27 = 5'd20;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
-      dev_sel_s1n_25 = 5'd21;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SENSOR_CTRL_AON)) == ADDR_SPACE_SENSOR_CTRL_AON) begin
+      dev_sel_s1n_27 = 5'd21;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
-      dev_sel_s1n_25 = 5'd22;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
+      dev_sel_s1n_27 = 5'd22;
 
-    end else if ((tl_s1n_25_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin
-      dev_sel_s1n_25 = 5'd23;
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_AST_WRAPPER)) == ADDR_SPACE_AST_WRAPPER) begin
+      dev_sel_s1n_27 = 5'd23;
+
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_SRAM_CTRL_RET_AON)) == ADDR_SPACE_SRAM_CTRL_RET_AON) begin
+      dev_sel_s1n_27 = 5'd24;
+
+    end else if ((tl_s1n_27_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
+      dev_sel_s1n_27 = 5'd25;
 end
   end
 
@@ -271,17 +289,17 @@
   tlul_socket_1n #(
     .HReqDepth (4'h0),
     .HRspDepth (4'h0),
-    .DReqDepth (96'h0),
-    .DRspDepth (96'h0),
-    .N         (24)
-  ) u_s1n_25 (
+    .DReqDepth (104'h0),
+    .DRspDepth (104'h0),
+    .N         (26)
+  ) u_s1n_27 (
     .clk_i        (clk_peri_i),
     .rst_ni       (rst_peri_ni),
-    .tl_h_i       (tl_s1n_25_us_h2d),
-    .tl_h_o       (tl_s1n_25_us_d2h),
-    .tl_d_o       (tl_s1n_25_ds_h2d),
-    .tl_d_i       (tl_s1n_25_ds_d2h),
-    .dev_select_i (dev_sel_s1n_25)
+    .tl_h_i       (tl_s1n_27_us_h2d),
+    .tl_h_o       (tl_s1n_27_us_d2h),
+    .tl_d_o       (tl_s1n_27_ds_h2d),
+    .tl_d_i       (tl_s1n_27_ds_d2h),
+    .dev_select_i (dev_sel_s1n_27)
   );
 
 endmodule
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
index 1df9d97..3d7d08e 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -44,9 +44,9 @@
   output logic [31:0] mio_out_o,
   output logic [31:0] mio_oe_o,
   // Dedicated I/O
-  input        [14:0] dio_in_i,
-  output logic [14:0] dio_out_o,
-  output logic [14:0] dio_oe_o,
+  input        [20:0] dio_in_i,
+  output logic [20:0] dio_out_o,
+  output logic [20:0] dio_oe_o,
 
   // pad attributes to padring
   output logic[pinmux_reg_pkg::NMioPads-1:0]
@@ -110,12 +110,12 @@
   import top_earlgrey_rnd_cnst_pkg::*;
 
   // Signals
-  logic [40:0] mio_p2d;
-  logic [44:0] mio_d2p;
-  logic [44:0] mio_d2p_en;
-  logic [14:0] dio_p2d;
-  logic [14:0] dio_d2p;
-  logic [14:0] dio_d2p_en;
+  logic [45:0] mio_p2d;
+  logic [51:0] mio_d2p;
+  logic [51:0] mio_d2p_en;
+  logic [20:0] dio_p2d;
+  logic [20:0] dio_d2p;
+  logic [20:0] dio_d2p_en;
   // uart0
   logic        cio_uart0_rx_p2d;
   logic        cio_uart0_tx_d2p;
@@ -139,9 +139,25 @@
   // spi_device
   logic        cio_spi_device_sck_p2d;
   logic        cio_spi_device_csb_p2d;
-  logic        cio_spi_device_sdi_p2d;
-  logic        cio_spi_device_sdo_d2p;
-  logic        cio_spi_device_sdo_en_d2p;
+  logic [3:0]  cio_spi_device_sd_p2d;
+  logic [3:0]  cio_spi_device_sd_d2p;
+  logic [3:0]  cio_spi_device_sd_en_d2p;
+  // spi_host0
+  logic [3:0]  cio_spi_host0_sd_p2d;
+  logic        cio_spi_host0_sck_d2p;
+  logic        cio_spi_host0_sck_en_d2p;
+  logic        cio_spi_host0_csb_d2p;
+  logic        cio_spi_host0_csb_en_d2p;
+  logic [3:0]  cio_spi_host0_sd_d2p;
+  logic [3:0]  cio_spi_host0_sd_en_d2p;
+  // spi_host1
+  logic [3:0]  cio_spi_host1_sd_p2d;
+  logic        cio_spi_host1_sck_d2p;
+  logic        cio_spi_host1_sck_en_d2p;
+  logic        cio_spi_host1_csb_d2p;
+  logic        cio_spi_host1_csb_en_d2p;
+  logic [3:0]  cio_spi_host1_sd_d2p;
+  logic [3:0]  cio_spi_host1_sd_en_d2p;
   // i2c0
   logic        cio_i2c0_sda_p2d;
   logic        cio_i2c0_scl_p2d;
@@ -499,6 +515,10 @@
   tlul_pkg::tl_d2h_t       gpio_tl_rsp;
   tlul_pkg::tl_h2d_t       spi_device_tl_req;
   tlul_pkg::tl_d2h_t       spi_device_tl_rsp;
+  tlul_pkg::tl_h2d_t       spi_host0_tl_req;
+  tlul_pkg::tl_d2h_t       spi_host0_tl_rsp;
+  tlul_pkg::tl_h2d_t       spi_host1_tl_req;
+  tlul_pkg::tl_d2h_t       spi_host1_tl_rsp;
   tlul_pkg::tl_h2d_t       rv_timer_tl_req;
   tlul_pkg::tl_d2h_t       rv_timer_tl_rsp;
   tlul_pkg::tl_h2d_t       usbdev_tl_req;
@@ -566,6 +586,8 @@
   logic unused_daon_rst_lc;
   logic unused_daon_rst_lc_io_div4;
   logic unused_daon_rst_spi_device;
+  logic unused_daon_rst_spi_host0;
+  logic unused_daon_rst_spi_host1;
   logic unused_daon_rst_usb;
   logic unused_daon_rst_i2c0;
   logic unused_daon_rst_i2c1;
@@ -579,6 +601,8 @@
   assign unused_daon_rst_lc = rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::DomainAonSel];
   assign unused_daon_rst_lc_io_div4 = rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::DomainAonSel];
   assign unused_daon_rst_spi_device = rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::DomainAonSel];
+  assign unused_daon_rst_spi_host0 = rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::DomainAonSel];
+  assign unused_daon_rst_spi_host1 = rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::DomainAonSel];
   assign unused_daon_rst_usb = rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::DomainAonSel];
   assign unused_daon_rst_i2c0 = rstmgr_aon_resets.rst_i2c0_n[rstmgr_pkg::DomainAonSel];
   assign unused_daon_rst_i2c1 = rstmgr_aon_resets.rst_i2c1_n[rstmgr_pkg::DomainAonSel];
@@ -1047,11 +1071,11 @@
       // Input
       .cio_sck_i    (cio_spi_device_sck_p2d),
       .cio_csb_i    (cio_spi_device_csb_p2d),
-      .cio_sdi_i    (cio_spi_device_sdi_p2d),
+      .cio_sd_i     (cio_spi_device_sd_p2d),
 
       // Output
-      .cio_sdo_o    (cio_spi_device_sdo_d2p),
-      .cio_sdo_en_o (cio_spi_device_sdo_en_d2p),
+      .cio_sd_o     (cio_spi_device_sd_d2p),
+      .cio_sd_en_o  (cio_spi_device_sd_en_d2p),
 
       // Interrupt
       .intr_rxf_o         (intr_spi_device_rxf),
@@ -1072,6 +1096,52 @@
       .rst_ni (rstmgr_aon_resets.rst_spi_device_n[rstmgr_pkg::Domain0Sel])
   );
 
+  spi_host u_spi_host0 (
+
+      // Input
+      .cio_sd_i     (cio_spi_host0_sd_p2d),
+
+      // Output
+      .cio_sck_o    (cio_spi_host0_sck_d2p),
+      .cio_sck_en_o (cio_spi_host0_sck_en_d2p),
+      .cio_csb_o    (cio_spi_host0_csb_d2p),
+      .cio_csb_en_o (cio_spi_host0_csb_en_d2p),
+      .cio_sd_o     (cio_spi_host0_sd_d2p),
+      .cio_sd_en_o  (cio_spi_host0_sd_en_d2p),
+
+      // Inter-module signals
+      .tl_i(spi_host0_tl_req),
+      .tl_o(spi_host0_tl_rsp),
+      .scanmode_i   (scanmode_i),
+
+      // Clock and reset connections
+      .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+      .rst_ni (rstmgr_aon_resets.rst_spi_host0_n[rstmgr_pkg::Domain0Sel])
+  );
+
+  spi_host u_spi_host1 (
+
+      // Input
+      .cio_sd_i     (cio_spi_host1_sd_p2d),
+
+      // Output
+      .cio_sck_o    (cio_spi_host1_sck_d2p),
+      .cio_sck_en_o (cio_spi_host1_sck_en_d2p),
+      .cio_csb_o    (cio_spi_host1_csb_d2p),
+      .cio_csb_en_o (cio_spi_host1_csb_en_d2p),
+      .cio_sd_o     (cio_spi_host1_sd_d2p),
+      .cio_sd_en_o  (cio_spi_host1_sd_en_d2p),
+
+      // Inter-module signals
+      .tl_i(spi_host1_tl_req),
+      .tl_o(spi_host1_tl_rsp),
+      .scanmode_i   (scanmode_i),
+
+      // Clock and reset connections
+      .clk_i (clkmgr_aon_clocks.clk_io_div4_peri),
+      .rst_ni (rstmgr_aon_resets.rst_spi_host1_n[rstmgr_pkg::Domain0Sel])
+  );
+
   i2c u_i2c0 (
 
       // Input
@@ -2238,6 +2308,14 @@
     .tl_spi_device_o(spi_device_tl_req),
     .tl_spi_device_i(spi_device_tl_rsp),
 
+    // port: tl_spi_host0
+    .tl_spi_host0_o(spi_host0_tl_req),
+    .tl_spi_host0_i(spi_host0_tl_rsp),
+
+    // port: tl_spi_host1
+    .tl_spi_host1_o(spi_host1_tl_req),
+    .tl_spi_host1_i(spi_host1_tl_rsp),
+
     // port: tl_rv_timer
     .tl_rv_timer_o(rv_timer_tl_req),
     .tl_rv_timer_i(rv_timer_tl_rsp),
@@ -2300,6 +2378,8 @@
 
   // Pinmux connections
   assign mio_d2p = {
+    cio_spi_host1_csb_d2p,
+    cio_spi_host1_sck_d2p,
     cio_pattgen_pcl1_tx_d2p,
     cio_pattgen_pda1_tx_d2p,
     cio_pattgen_pcl0_tx_d2p,
@@ -2307,6 +2387,8 @@
     cio_uart3_tx_d2p,
     cio_uart2_tx_d2p,
     cio_uart1_tx_d2p,
+    cio_uart0_tx_d2p,
+    cio_spi_host1_sd_d2p,
     cio_i2c2_scl_d2p,
     cio_i2c2_sda_d2p,
     cio_i2c1_scl_d2p,
@@ -2316,6 +2398,8 @@
     cio_gpio_gpio_d2p
   };
   assign mio_d2p_en = {
+    cio_spi_host1_csb_en_d2p,
+    cio_spi_host1_sck_en_d2p,
     cio_pattgen_pcl1_tx_en_d2p,
     cio_pattgen_pda1_tx_en_d2p,
     cio_pattgen_pcl0_tx_en_d2p,
@@ -2323,6 +2407,8 @@
     cio_uart3_tx_en_d2p,
     cio_uart2_tx_en_d2p,
     cio_uart1_tx_en_d2p,
+    cio_uart0_tx_en_d2p,
+    cio_spi_host1_sd_en_d2p,
     cio_i2c2_scl_en_d2p,
     cio_i2c2_sda_en_d2p,
     cio_i2c1_scl_en_d2p,
@@ -2335,6 +2421,8 @@
     cio_uart3_rx_p2d,
     cio_uart2_rx_p2d,
     cio_uart1_rx_p2d,
+    cio_uart0_rx_p2d,
+    cio_spi_host1_sd_p2d,
     cio_i2c2_scl_p2d,
     cio_i2c2_sda_p2d,
     cio_i2c1_scl_p2d,
@@ -2347,12 +2435,18 @@
   // Dedicated IO connections
   // Input-only DIOs have no d2p signals
   assign dio_d2p = {
-    1'b0, // DIO14: cio_spi_device_sck
-    1'b0, // DIO13: cio_spi_device_csb
-    1'b0, // DIO12: cio_spi_device_sdi
-    cio_spi_device_sdo_d2p, // DIO11
-    1'b0, // DIO10: cio_uart0_rx
-    cio_uart0_tx_d2p, // DIO9
+    1'b0, // DIO20: cio_spi_device_sck
+    1'b0, // DIO19: cio_spi_device_csb
+    cio_spi_device_sd_d2p[3], // DIO18
+    cio_spi_device_sd_d2p[2], // DIO17
+    cio_spi_device_sd_d2p[1], // DIO16
+    cio_spi_device_sd_d2p[0], // DIO15
+    cio_spi_host0_sck_d2p, // DIO14
+    cio_spi_host0_csb_d2p, // DIO13
+    cio_spi_host0_sd_d2p[3], // DIO12
+    cio_spi_host0_sd_d2p[2], // DIO11
+    cio_spi_host0_sd_d2p[1], // DIO10
+    cio_spi_host0_sd_d2p[0], // DIO9
     1'b0, // DIO8: cio_usbdev_sense
     cio_usbdev_se0_d2p, // DIO7
     cio_usbdev_dp_pullup_d2p, // DIO6
@@ -2365,12 +2459,18 @@
   };
 
   assign dio_d2p_en = {
-    1'b0, // DIO14: cio_spi_device_sck
-    1'b0, // DIO13: cio_spi_device_csb
-    1'b0, // DIO12: cio_spi_device_sdi
-    cio_spi_device_sdo_en_d2p, // DIO11
-    1'b0, // DIO10: cio_uart0_rx
-    cio_uart0_tx_en_d2p, // DIO9
+    1'b0, // DIO20: cio_spi_device_sck
+    1'b0, // DIO19: cio_spi_device_csb
+    cio_spi_device_sd_en_d2p[3], // DIO18
+    cio_spi_device_sd_en_d2p[2], // DIO17
+    cio_spi_device_sd_en_d2p[1], // DIO16
+    cio_spi_device_sd_en_d2p[0], // DIO15
+    cio_spi_host0_sck_en_d2p, // DIO14
+    cio_spi_host0_csb_en_d2p, // DIO13
+    cio_spi_host0_sd_en_d2p[3], // DIO12
+    cio_spi_host0_sd_en_d2p[2], // DIO11
+    cio_spi_host0_sd_en_d2p[1], // DIO10
+    cio_spi_host0_sd_en_d2p[0], // DIO9
     1'b0, // DIO8: cio_usbdev_sense
     cio_usbdev_se0_en_d2p, // DIO7
     cio_usbdev_dp_pullup_en_d2p, // DIO6
@@ -2383,18 +2483,24 @@
   };
 
   // Output-only DIOs have no p2d signal
-  assign cio_spi_device_sck_p2d    = dio_p2d[14]; // DIO14
-  assign cio_spi_device_csb_p2d    = dio_p2d[13]; // DIO13
-  assign cio_spi_device_sdi_p2d    = dio_p2d[12]; // DIO12
-  // DIO11: cio_spi_device_sdo
-  assign cio_uart0_rx_p2d          = dio_p2d[10]; // DIO10
-  // DIO9: cio_uart0_tx
+  assign cio_spi_device_sck_p2d    = dio_p2d[20]; // DIO20
+  assign cio_spi_device_csb_p2d    = dio_p2d[19]; // DIO19
+  assign cio_spi_device_sd_p2d[3]  = dio_p2d[18]; // DIO18
+  assign cio_spi_device_sd_p2d[2]  = dio_p2d[17]; // DIO17
+  assign cio_spi_device_sd_p2d[1]  = dio_p2d[16]; // DIO16
+  assign cio_spi_device_sd_p2d[0]  = dio_p2d[15]; // DIO15
+  // DIO14: cio_spi_host0_sck // DIO14
+  // DIO13: cio_spi_host0_csb // DIO13
+  assign cio_spi_host0_sd_p2d[3]   = dio_p2d[12]; // DIO12
+  assign cio_spi_host0_sd_p2d[2]   = dio_p2d[11]; // DIO11
+  assign cio_spi_host0_sd_p2d[1]   = dio_p2d[10]; // DIO10
+  assign cio_spi_host0_sd_p2d[0]   = dio_p2d[9]; // DIO9
   assign cio_usbdev_sense_p2d      = dio_p2d[8]; // DIO8
-  // DIO7: cio_usbdev_se0
-  // DIO6: cio_usbdev_dp_pullup
-  // DIO5: cio_usbdev_dn_pullup
-  // DIO4: cio_usbdev_tx_mode_se
-  // DIO3: cio_usbdev_suspend
+  // DIO7: cio_usbdev_se0 // DIO7
+  // DIO6: cio_usbdev_dp_pullup // DIO6
+  // DIO5: cio_usbdev_dn_pullup // DIO5
+  // DIO4: cio_usbdev_tx_mode_se // DIO4
+  // DIO3: cio_usbdev_suspend // DIO3
   assign cio_usbdev_d_p2d          = dio_p2d[2]; // DIO2
   assign cio_usbdev_dp_p2d         = dio_p2d[1]; // DIO1
   assign cio_usbdev_dn_p2d         = dio_p2d[0]; // DIO0
diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
index 46a5b25..b068a4e 100644
--- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
+++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv
@@ -72,6 +72,26 @@
   parameter int unsigned TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES = 32'h2000;
 
   /**
+   * Peripheral base address for spi_host0 in top earlgrey.
+   */
+  parameter int unsigned TOP_EARLGREY_SPI_HOST0_BASE_ADDR = 32'h40060000;
+
+  /**
+   * Peripheral size in bytes for spi_host0 in top earlgrey.
+   */
+  parameter int unsigned TOP_EARLGREY_SPI_HOST0_SIZE_BYTES = 32'h1000;
+
+  /**
+   * Peripheral base address for spi_host1 in top earlgrey.
+   */
+  parameter int unsigned TOP_EARLGREY_SPI_HOST1_BASE_ADDR = 32'h40070000;
+
+  /**
+   * Peripheral size in bytes for spi_host1 in top earlgrey.
+   */
+  parameter int unsigned TOP_EARLGREY_SPI_HOST1_SIZE_BYTES = 32'h1000;
+
+  /**
    * Peripheral base address for i2c0 in top earlgrey.
    */
   parameter int unsigned TOP_EARLGREY_I2C0_BASE_ADDR = 32'h40080000;
@@ -402,13 +422,13 @@
     TopEarlgreyDioPinUsbdevDpPullup = 6,
     TopEarlgreyDioPinUsbdevSe0 = 7,
     TopEarlgreyDioPinUsbdevSense = 8,
-    TopEarlgreyDioPinUart0Tx = 9,
-    TopEarlgreyDioPinUart0Rx = 10,
-    TopEarlgreyDioPinSpiDeviceSdo = 11,
-    TopEarlgreyDioPinSpiDeviceSdi = 12,
-    TopEarlgreyDioPinSpiDeviceCsb = 13,
-    TopEarlgreyDioPinSpiDeviceSck = 14,
-    TopEarlgreyDioPinCount = 15
+    TopEarlgreyDioPinSpiHost0Sd[4] = 9,
+    TopEarlgreyDioPinSpiHost0Csb = 13,
+    TopEarlgreyDioPinSpiHost0Sck = 14,
+    TopEarlgreyDioPinSpiDeviceSd[4] = 15,
+    TopEarlgreyDioPinSpiDeviceCsb = 19,
+    TopEarlgreyDioPinSpiDeviceSck = 20,
+    TopEarlgreyDioPinCount = 21
   } top_earlgrey_dio_pin_e;
 
   // TODO: Enumeration for PLIC Interrupt source peripheral.
diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
index 9b2e33c..45df468 100644
--- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h
+++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h
@@ -134,6 +134,42 @@
 #define TOP_EARLGREY_SPI_DEVICE_SIZE_BYTES 0x2000u
 
 /**
+ * Peripheral base address for spi_host0 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST0_BASE_ADDR 0x40060000u
+
+/**
+ * Peripheral size for spi_host0 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_SPI_HOST0_BASE_ADDR and
+ * `TOP_EARLGREY_SPI_HOST0_BASE_ADDR + TOP_EARLGREY_SPI_HOST0_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_SPI_HOST0_SIZE_BYTES 0x1000u
+
+/**
+ * Peripheral base address for spi_host1 in top earlgrey.
+ *
+ * This should be used with #mmio_region_from_addr to access the memory-mapped
+ * registers associated with the peripheral (usually via a DIF).
+ */
+#define TOP_EARLGREY_SPI_HOST1_BASE_ADDR 0x40070000u
+
+/**
+ * Peripheral size for spi_host1 in top earlgrey.
+ *
+ * This is the size (in bytes) of the peripheral's reserved memory area. All
+ * memory-mapped registers associated with this peripheral should have an
+ * address between #TOP_EARLGREY_SPI_HOST1_BASE_ADDR and
+ * `TOP_EARLGREY_SPI_HOST1_BASE_ADDR + TOP_EARLGREY_SPI_HOST1_SIZE_BYTES`.
+ */
+#define TOP_EARLGREY_SPI_HOST1_SIZE_BYTES 0x1000u
+
+/**
  * Peripheral base address for i2c0 in top earlgrey.
  *
  * This should be used with #mmio_region_from_addr to access the memory-mapped
@@ -985,7 +1021,7 @@
 // PERIPH_INSEL ranges from 0 to NUM_MIO + 2 -1}
 //  0 and 1 are tied to value 0 and 1
 #define NUM_MIO 32
-#define NUM_DIO 15
+#define NUM_DIO 21
 
 #define PINMUX_PERIPH_OUTSEL_IDX_OFFSET 3
 
@@ -1031,10 +1067,15 @@
   kTopEarlgreyPinmuxPeripheralInI2c1Scl = 35, /**< i2c1_scl */
   kTopEarlgreyPinmuxPeripheralInI2c2Sda = 36, /**< i2c2_sda */
   kTopEarlgreyPinmuxPeripheralInI2c2Scl = 37, /**< i2c2_scl */
-  kTopEarlgreyPinmuxPeripheralInUart1Rx = 38, /**< uart1_rx */
-  kTopEarlgreyPinmuxPeripheralInUart2Rx = 39, /**< uart2_rx */
-  kTopEarlgreyPinmuxPeripheralInUart3Rx = 40, /**< uart3_rx */
-  kTopEarlgreyPinmuxPeripheralInLast = 40, /**< \internal Last valid peripheral input */
+  kTopEarlgreyPinmuxPeripheralInSpiHost1Sd0 = 38, /**< spi_host1_sd 0 */
+  kTopEarlgreyPinmuxPeripheralInSpiHost1Sd1 = 39, /**< spi_host1_sd 1 */
+  kTopEarlgreyPinmuxPeripheralInSpiHost1Sd2 = 40, /**< spi_host1_sd 2 */
+  kTopEarlgreyPinmuxPeripheralInSpiHost1Sd3 = 41, /**< spi_host1_sd 3 */
+  kTopEarlgreyPinmuxPeripheralInUart0Rx = 42, /**< uart0_rx */
+  kTopEarlgreyPinmuxPeripheralInUart1Rx = 43, /**< uart1_rx */
+  kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< uart2_rx */
+  kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< uart3_rx */
+  kTopEarlgreyPinmuxPeripheralInLast = 45, /**< \internal Last valid peripheral input */
 } top_earlgrey_pinmux_peripheral_in_t;
 
 /**
@@ -1162,14 +1203,21 @@
   kTopEarlgreyPinmuxOutselI2c1Scl = 38, /**< i2c1_scl */
   kTopEarlgreyPinmuxOutselI2c2Sda = 39, /**< i2c2_sda */
   kTopEarlgreyPinmuxOutselI2c2Scl = 40, /**< i2c2_scl */
-  kTopEarlgreyPinmuxOutselUart1Tx = 41, /**< uart1_tx */
-  kTopEarlgreyPinmuxOutselUart2Tx = 42, /**< uart2_tx */
-  kTopEarlgreyPinmuxOutselUart3Tx = 43, /**< uart3_tx */
-  kTopEarlgreyPinmuxOutselPattgenPda0Tx = 44, /**< pattgen_pda0_tx */
-  kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 45, /**< pattgen_pcl0_tx */
-  kTopEarlgreyPinmuxOutselPattgenPda1Tx = 46, /**< pattgen_pda1_tx */
-  kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 47, /**< pattgen_pcl1_tx */
-  kTopEarlgreyPinmuxOutselLast = 47, /**< \internal Last valid outsel value */
+  kTopEarlgreyPinmuxOutselSpiHost1Sd0 = 41, /**< spi_host1_sd 0 */
+  kTopEarlgreyPinmuxOutselSpiHost1Sd1 = 42, /**< spi_host1_sd 1 */
+  kTopEarlgreyPinmuxOutselSpiHost1Sd2 = 43, /**< spi_host1_sd 2 */
+  kTopEarlgreyPinmuxOutselSpiHost1Sd3 = 44, /**< spi_host1_sd 3 */
+  kTopEarlgreyPinmuxOutselUart0Tx = 45, /**< uart0_tx */
+  kTopEarlgreyPinmuxOutselUart1Tx = 46, /**< uart1_tx */
+  kTopEarlgreyPinmuxOutselUart2Tx = 47, /**< uart2_tx */
+  kTopEarlgreyPinmuxOutselUart3Tx = 48, /**< uart3_tx */
+  kTopEarlgreyPinmuxOutselPattgenPda0Tx = 49, /**< pattgen_pda0_tx */
+  kTopEarlgreyPinmuxOutselPattgenPcl0Tx = 50, /**< pattgen_pcl0_tx */
+  kTopEarlgreyPinmuxOutselPattgenPda1Tx = 51, /**< pattgen_pda1_tx */
+  kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52, /**< pattgen_pcl1_tx */
+  kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< spi_host1_sck */
+  kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< spi_host1_csb */
+  kTopEarlgreyPinmuxOutselLast = 54, /**< \internal Last valid outsel value */
 } top_earlgrey_pinmux_outsel_t;
 
 /**
@@ -1186,11 +1234,13 @@
  */
 typedef enum top_earlgrey_reset_manager_sw_resets {
   kTopEarlgreyResetManagerSwResetsSpiDevice = 0, /**<  */
-  kTopEarlgreyResetManagerSwResetsUsb = 1, /**<  */
-  kTopEarlgreyResetManagerSwResetsI2c0 = 2, /**<  */
-  kTopEarlgreyResetManagerSwResetsI2c1 = 3, /**<  */
-  kTopEarlgreyResetManagerSwResetsI2c2 = 4, /**<  */
-  kTopEarlgreyResetManagerSwResetsLast = 4, /**< \internal Last valid rstmgr software reset request */
+  kTopEarlgreyResetManagerSwResetsSpiHost0 = 1, /**<  */
+  kTopEarlgreyResetManagerSwResetsSpiHost1 = 2, /**<  */
+  kTopEarlgreyResetManagerSwResetsUsb = 3, /**<  */
+  kTopEarlgreyResetManagerSwResetsI2c0 = 4, /**<  */
+  kTopEarlgreyResetManagerSwResetsI2c1 = 5, /**<  */
+  kTopEarlgreyResetManagerSwResetsI2c2 = 6, /**<  */
+  kTopEarlgreyResetManagerSwResetsLast = 6, /**< \internal Last valid rstmgr software reset request */
 } top_earlgrey_reset_manager_sw_resets_t;
 
 /**
diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core
index 8d285d9..748daf6 100644
--- a/hw/top_earlgrey/top_earlgrey.core
+++ b/hw/top_earlgrey/top_earlgrey.core
@@ -18,6 +18,7 @@
       - lowrisc:ip:rv_timer
       - lowrisc:ip:tlul
       - lowrisc:ip:spi_device
+      - lowrisc:ip:spi_host
       - lowrisc:ip:i2c
       - lowrisc:ip:pattgen
       - lowrisc:ip:aes
@@ -48,6 +49,7 @@
       - "fileset_partner ? (partner:systems:ast_pkg)"
       - lowrisc:tlul:headers
       - lowrisc:prim:all
+      - lowrisc:prim:usb_diff_rx
     files:
       - rtl/autogen/top_earlgrey_rnd_cnst_pkg.sv
       - rtl/autogen/top_earlgrey.sv