tree ca3a385747f1774be2c3aa21077568101c877a5c
parent b37566f81e04dfdc8060b29b9eaf2242ca5e3626
author Rupert Swarbrick <rswarbrick@lowrisc.org> 1623158080 +0100
committer Rupert Swarbrick <rswarbrick@gmail.com> 1623320646 +0100

[reggen] Optionally expose register interface in reg2hw signal

If a block sets expose_reg_if in the hjson, the generated reg2hw
structure will contain an extra field called "reg_if", which has the
register interface signals. This could be useful for things like
checksumming writes over the interface. For example, OTBN is
considering a register that checksums all the writes from Ibex, in
order to beef up data integrity checking between Ibex and OTBN (see
issue #6175). This could also be used for more elaborate things like
port knocking schemes.

This exposes all the signals that come from the TLUL interface:
reg_we, reg_re, reg_addr, reg_wdata and reg_be. It doesn't expose
reg_rdata and reg_error because we don't really have a use for that at
the moment and it causes lint problems (where it looks like a
combinatorial loop between reg2hw and hw2reg).

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>