diff --git a/hw/ip/aes/syn/aes_syn_cfg.hjson b/hw/ip/aes/syn/aes_syn_cfg.hjson
new file mode 100644
index 0000000..d748d1e
--- /dev/null
+++ b/hw/ip/aes/syn/aes_syn_cfg.hjson
@@ -0,0 +1,18 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  // Top level dut name (sv module).
+  name: aes
+
+  // Fusesoc core file used for building the file list.
+  fusesoc_core: lowrisc:ip:aes:0.6
+
+  import_cfgs: [// Project wide common synthesis config file
+                "{proj_root}/hw/syn/data/common_syn_cfg.hjson"]
+
+  // Timing constraints for this module
+  sdc_file: "{proj_root}/hw/ip/aes/syn/constraints.sdc"
+
+  // TODO: add support for loading the constraints here
+ }
diff --git a/hw/ip/aes/syn/constraints.sdc b/hw/ip/aes/syn/constraints.sdc
new file mode 100644
index 0000000..151bea0
--- /dev/null
+++ b/hw/ip/aes/syn/constraints.sdc
@@ -0,0 +1,46 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Generic constraints file for simple testsynthesis flow
+
+# note that we do not fix hold timing in this flow
+set SETUP_CLOCK_UNCERTAINTY 0.5
+
+puts "Applying constraints for AES block"
+
+#####################
+# main clock        #
+#####################
+set MAIN_CLK_PIN clk_i
+set MAIN_RST_PIN rst_ni
+# set main clock to 125 MHz
+set MAIN_TCK  8.0
+set_ideal_network ${MAIN_CLK_PIN}
+set_ideal_network ${MAIN_RST_PIN}
+set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN}
+
+# other timing constraint in ns
+set IN_DEL    1.0
+set OUT_DEL   1.0
+set DELAY     ${MAIN_TCK}
+
+create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK}
+
+# in to out
+set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs]
+# in to reg / reg to out
+set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${MAIN_CLK_PIN}}] -clock ${MAIN_CLK_PIN}
+set_output_delay ${OUT_DEL}  [all_outputs] -clock ${MAIN_CLK_PIN}
+
+#####################
+# I/O drive/load    #
+#####################
+
+# attach load and drivers to IOs to get a more realistic estimate
+set_driving_cell  -no_design_rule -lib_cell ${driving_cell} -pin X [all_inputs]
+set_load [load_of ${load_lib}/${load_cell}/A] [all_outputs]
+
+# set a nonzero critical range to be able to spot the violating paths better
+# in the report
+set_critical_range 0.5 ${DUT}
diff --git a/hw/syn/data/dc.hjson b/hw/syn/data/dc.hjson
index bc57374..35c65ce 100644
--- a/hw/syn/data/dc.hjson
+++ b/hw/syn/data/dc.hjson
@@ -6,7 +6,7 @@
   // the main synthesis run script and the constraints file
   tool_srcs: ["{proj_root}/hw/foundry/syn/{tool}/setup.tcl"
               "{proj_root}/hw/syn/tools/{tool}/run-syn.tcl"
-              "{proj_root}/hw/syn/tools/{tool}/constraints.sdc"]
+              "{sdc_file}"]
 
   // Environment variables that are needed in the synthesis script
   exports: [{"DUT"       : "{dut}"},
diff --git a/hw/syn/tools/dc/constraints.sdc b/hw/top_earlgrey/syn/constraints.sdc
similarity index 83%
rename from hw/syn/tools/dc/constraints.sdc
rename to hw/top_earlgrey/syn/constraints.sdc
index 4791cbe..4891634 100644
--- a/hw/syn/tools/dc/constraints.sdc
+++ b/hw/top_earlgrey/syn/constraints.sdc
@@ -3,14 +3,10 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Generic constraints file for simple testsynthesis flow
-# This held very simple for now and needs to be refined
 
 # note that we do not fix hold timing in this flow
 set SETUP_CLOCK_UNCERTAINTY 0.5
 
-# TODO: consider splitting this into per-IP .sdc files
-if {$DUT == "top_earlgrey"} {
-
 puts "Applying constraints for top level"
 
 # note: this does not account for clock insertion delay and
@@ -120,36 +116,8 @@
 # loopback path can be considered to be a false path
 set_false_path -from dio_uart_rx_i -to dio_uart_tx_o
 
-} else {
-
 #####################
-# main clock        #
-#####################
-set MAIN_CLK_PIN clk_i
-set MAIN_RST_PIN rst_ni
-# set main clock to 125 MHz
-set MAIN_TCK  8.0
-set_ideal_network ${MAIN_CLK_PIN}
-set_ideal_network ${MAIN_RST_PIN}
-set_clock_uncertainty ${SETUP_CLOCK_UNCERTAINTY} ${MAIN_CLK_PIN}
-
-# other timing constraint in ns
-set IN_DEL    1.0
-set OUT_DEL   1.0
-set DELAY     ${MAIN_TCK}
-
-create_clock ${MAIN_CLK_PIN} -period ${MAIN_TCK}
-
-# in to out
-set_max_delay ${DELAY} -from [all_inputs] -to [all_outputs]
-# in to reg / reg to out
-set_input_delay ${IN_DEL} [remove_from_collection [all_inputs] {${MAIN_CLK_PIN}}] -clock ${MAIN_CLK_PIN}
-set_output_delay ${OUT_DEL}  [all_outputs] -clock ${MAIN_CLK_PIN}
-
-}
-
-#####################
-# Common            #
+# I/O drive/load    #
 #####################
 
 # attach load and drivers to IOs to get a more realistic estimate
diff --git a/hw/top_earlgrey/syn/top_earlgrey_syn_cfg.hjson b/hw/top_earlgrey/syn/top_earlgrey_syn_cfg.hjson
index fb03be8..f1496ac 100644
--- a/hw/top_earlgrey/syn/top_earlgrey_syn_cfg.hjson
+++ b/hw/top_earlgrey/syn/top_earlgrey_syn_cfg.hjson
@@ -11,5 +11,8 @@
   import_cfgs: [// Project wide common synthesis config file
                 "{proj_root}/hw/syn/data/common_syn_cfg.hjson"]
 
+  // Timing constraints for this module
+  sdc_file: "{proj_root}/hw/top_earlgrey/syn/constraints.sdc"
+
   // TODO: add support for loading the constraints here
  }